2a5c9f6162acb75cb209fde168f363f261f98c91
[gem5.git] / src / arch / alpha / process.cc
1 /*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32 #include "arch/alpha/process.hh"
33
34 #include "arch/alpha/isa_traits.hh"
35 #include "base/loader/elf_object.hh"
36 #include "base/loader/object_file.hh"
37 #include "base/misc.hh"
38 #include "cpu/thread_context.hh"
39 #include "debug/Loader.hh"
40 #include "mem/page_table.hh"
41 #include "sim/aux_vector.hh"
42 #include "sim/byteswap.hh"
43 #include "sim/process_impl.hh"
44 #include "sim/syscall_return.hh"
45 #include "sim/system.hh"
46
47 using namespace AlphaISA;
48 using namespace std;
49
50 AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
51 : Process(params, objFile)
52 {
53 Addr brk_point = objFile->dataBase() + objFile->dataSize() +
54 objFile->bssSize();
55 brk_point = roundUp(brk_point, PageBytes);
56
57 // Set up stack. On Alpha, stack goes below text section. This
58 // code should get moved to some architecture-specific spot.
59 Addr stack_base = objFile->textBase() - (409600+4096);
60
61 // Set up region for mmaps.
62 Addr mmap_end = 0x10000;
63
64 Addr max_stack_size = 8 * 1024 * 1024;
65
66 // Set pointer for next thread stack. Reserve 8M for main stack.
67 Addr next_thread_stack_base = stack_base - max_stack_size;
68
69 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
70 next_thread_stack_base, mmap_end);
71 }
72
73 void
74 AlphaProcess::argsInit(int intSize, int pageSize)
75 {
76 // Patch the ld_bias for dynamic executables.
77 updateBias();
78
79 objFile->loadSections(initVirtMem);
80
81 typedef AuxVector<uint64_t> auxv_t;
82 std::vector<auxv_t> auxv;
83
84 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
85 if (elfObject)
86 {
87 // modern glibc uses a bunch of auxiliary vectors to set up
88 // TLS as well as do a bunch of other stuff
89 // these vectors go on the bottom of the stack, below argc/argv/envp
90 // pointers but above actual arg strings
91 // I don't have all the ones glibc looks at here, but so far it doesn't
92 // seem to be a problem.
93 // check out _dl_aux_init() in glibc/elf/dl-support.c for details
94 // --Lisa
95 auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
96 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
97 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
98 DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
99 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
100 // This is the base address of the ELF interpreter; it should be
101 // zero for static executables or contain the base address for
102 // dynamic executables.
103 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
104 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
105 auxv.push_back(auxv_t(M5_AT_UID, uid()));
106 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
107 auxv.push_back(auxv_t(M5_AT_GID, gid()));
108 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
109
110 }
111
112 // Calculate how much space we need for arg & env & auxv arrays.
113 int argv_array_size = intSize * (argv.size() + 1);
114 int envp_array_size = intSize * (envp.size() + 1);
115 int auxv_array_size = intSize * 2 * (auxv.size() + 1);
116
117 int arg_data_size = 0;
118 for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
119 arg_data_size += argv[i].size() + 1;
120 }
121 int env_data_size = 0;
122 for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
123 env_data_size += envp[i].size() + 1;
124 }
125
126 int space_needed =
127 argv_array_size +
128 envp_array_size +
129 auxv_array_size +
130 arg_data_size +
131 env_data_size;
132
133 if (space_needed < 32*1024)
134 space_needed = 32*1024;
135
136 // set bottom of stack
137 memState->setStackMin(memState->getStackBase() - space_needed);
138 // align it
139 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
140 memState->setStackSize(memState->getStackBase() - memState->getStackMin());
141 // map memory
142 allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(),
143 pageSize));
144
145 // map out initial stack contents
146 Addr argv_array_base = memState->getStackMin() + intSize; // room for argc
147 Addr envp_array_base = argv_array_base + argv_array_size;
148 Addr auxv_array_base = envp_array_base + envp_array_size;
149 Addr arg_data_base = auxv_array_base + auxv_array_size;
150 Addr env_data_base = arg_data_base + arg_data_size;
151
152 // write contents to stack
153 uint64_t argc = argv.size();
154 if (intSize == 8)
155 argc = htog((uint64_t)argc);
156 else if (intSize == 4)
157 argc = htog((uint32_t)argc);
158 else
159 panic("Unknown int size");
160
161 initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*)&argc, intSize);
162
163 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
164 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
165
166 //Copy the aux stuff
167 for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
168 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
169 (uint8_t*)&(auxv[x].a_type), intSize);
170 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
171 (uint8_t*)&(auxv[x].a_val), intSize);
172 }
173
174 ThreadContext *tc = system->getThreadContext(contextIds[0]);
175
176 setSyscallArg(tc, 0, argc);
177 setSyscallArg(tc, 1, argv_array_base);
178 tc->setIntReg(StackPointerReg, memState->getStackMin());
179
180 tc->pcState(getStartPC());
181 }
182
183 void
184 AlphaProcess::setupASNReg()
185 {
186 ThreadContext *tc = system->getThreadContext(contextIds[0]);
187 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
188 }
189
190
191 void
192 AlphaProcess::unserialize(CheckpointIn &cp)
193 {
194 Process::unserialize(cp);
195 // need to set up ASN after unserialization since _pid value may
196 // come from checkpoint
197 setupASNReg();
198 }
199
200
201 void
202 AlphaProcess::initState()
203 {
204 // need to set up ASN before further initialization since init
205 // will involve writing to virtual memory addresses
206 setupASNReg();
207
208 Process::initState();
209
210 argsInit(MachineBytes, PageBytes);
211
212 ThreadContext *tc = system->getThreadContext(contextIds[0]);
213 tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
214 //Operate in user mode
215 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
216 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
217 //No super page mapping
218 tc->setMiscRegNoEffect(IPR_MCSR, 0);
219 }
220
221 AlphaISA::IntReg
222 AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
223 {
224 assert(i < 6);
225 return tc->readIntReg(FirstArgumentReg + i++);
226 }
227
228 void
229 AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
230 {
231 assert(i < 6);
232 tc->setIntReg(FirstArgumentReg + i, val);
233 }
234
235 void
236 AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
237 {
238 // check for error condition. Alpha syscall convention is to
239 // indicate success/failure in reg a3 (r19) and put the
240 // return value itself in the standard return value reg (v0).
241 if (sysret.successful()) {
242 // no error
243 tc->setIntReg(SyscallSuccessReg, 0);
244 tc->setIntReg(ReturnValueReg, sysret.returnValue());
245 } else {
246 // got an error, return details
247 tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
248 tc->setIntReg(ReturnValueReg, sysret.errnoValue());
249 }
250 }