src/arch/arm/insts/static_inst.hh

   1 /*
   2  * Copyright (c) 2010-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Stephen Hines
  41  */
  42 #ifndef __ARCH_ARM_INSTS_STATICINST_HH__
  43 #define __ARCH_ARM_INSTS_STATICINST_HH__
  44
  45 #include "arch/arm/faults.hh"
  46 #include "arch/arm/utility.hh"
  47 #include "arch/arm/system.hh"
  48 #include "base/trace.hh"
  49 #include "cpu/static_inst.hh"
  50 #include "sim/byteswap.hh"
  51 #include "sim/full_system.hh"
  52
  53 namespace ArmISA
  54 {
  55
  56 class ArmStaticInst : public StaticInst
  57 {
  58   protected:
  59     bool aarch64;
  60     uint8_t intWidth;
  61
  62     int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
  63                          uint32_t type, uint32_t cfval) const;
  64     int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
  65                         uint32_t type, uint32_t cfval) const;
  66
  67     bool shift_carry_imm(uint32_t base, uint32_t shamt,
  68                          uint32_t type, uint32_t cfval) const;
  69     bool shift_carry_rs(uint32_t base, uint32_t shamt,
  70                         uint32_t type, uint32_t cfval) const;
  71
  72     int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
  73                        ArmShiftType type, uint8_t width) const;
  74     int64_t extendReg64(uint64_t base, ArmExtendType type,
  75                         uint64_t shiftAmt, uint8_t width) const;
  76
  77     template<int width>
  78     static inline bool
  79     saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
  80     {
  81         int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
  82         if (bits(midRes, width) != bits(midRes, width - 1)) {
  83             if (midRes > 0)
  84                 res = (LL(1) << (width - 1)) - 1;
  85             else
  86                 res = -(LL(1) << (width - 1));
  87             return true;
  88         } else {
  89             res = midRes;
  90             return false;
  91         }
  92     }
  93
  94     static inline bool
  95     satInt(int32_t &res, int64_t op, int width)
  96     {
  97         width--;
  98         if (op >= (LL(1) << width)) {
  99             res = (LL(1) << width) - 1;
 100             return true;
 101         } else if (op < -(LL(1) << width)) {
 102             res = -(LL(1) << width);
 103             return true;
 104         } else {
 105             res = op;
 106             return false;
 107         }
 108     }
 109
 110     template<int width>
 111     static inline bool
 112     uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
 113     {
 114         int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
 115         if (midRes >= (LL(1) << width)) {
 116             res = (LL(1) << width) - 1;
 117             return true;
 118         } else if (midRes < 0) {
 119             res = 0;
 120             return true;
 121         } else {
 122             res = midRes;
 123             return false;
 124         }
 125     }
 126
 127     static inline bool
 128     uSatInt(int32_t &res, int64_t op, int width)
 129     {
 130         if (op >= (LL(1) << width)) {
 131             res = (LL(1) << width) - 1;
 132             return true;
 133         } else if (op < 0) {
 134             res = 0;
 135             return true;
 136         } else {
 137             res = op;
 138             return false;
 139         }
 140     }
 141
 142     // Constructor
 143     ArmStaticInst(const char *mnem, ExtMachInst _machInst,
 144                   OpClass __opClass)
 145         : StaticInst(mnem, _machInst, __opClass)
 146     {
 147         aarch64 = machInst.aarch64;
 148         if (bits(machInst, 28, 24) == 0x10)
 149             intWidth = 64;  // Force 64-bit width for ADR/ADRP
 150         else
 151             intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
 152     }
 153
 154     /// Print a register name for disassembly given the unique
 155     /// dependence tag number (FP or int).
 156     void printReg(std::ostream &os, int reg) const;
 157     void printMnemonic(std::ostream &os,
 158                        const std::string &suffix = "",
 159                        bool withPred = true,
 160                        bool withCond64 = false,
 161                        ConditionCode cond64 = COND_UC) const;
 162     void printTarget(std::ostream &os, Addr target,
 163                      const SymbolTable *symtab) const;
 164     void printCondition(std::ostream &os, unsigned code,
 165                         bool noImplicit=false) const;
 166     void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
 167                         const std::string &prefix, const Addr addr,
 168                         const std::string &suffix) const;
 169     void printShiftOperand(std::ostream &os, IntRegIndex rm,
 170                            bool immShift, uint32_t shiftAmt,
 171                            IntRegIndex rs, ArmShiftType type) const;
 172     void printExtendOperand(bool firstOperand, std::ostream &os,
 173                             IntRegIndex rm, ArmExtendType type,
 174                             int64_t shiftAmt) const;
 175
 176
 177     void printDataInst(std::ostream &os, bool withImm) const;
 178     void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
 179                        IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
 180                        IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
 181                        uint32_t imm) const;
 182
 183     void
 184     advancePC(PCState &pcState) const
 185     {
 186         pcState.advance();
 187     }
 188
 189     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 190
 191     static inline uint32_t
 192     cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
 193             uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
 194     {
 195         bool privileged   = (cpsr.mode != MODE_USER);
 196         bool haveVirt     = ArmSystem::haveVirtualization(tc);
 197         bool haveSecurity = ArmSystem::haveSecurity(tc);
 198         bool isSecure     = inSecureState(scr, cpsr) || !haveSecurity;
 199
 200         uint32_t bitMask = 0;
 201
 202         if (bits(byteMask, 3)) {
 203             unsigned lowIdx = affectState ? 24 : 27;
 204             bitMask = bitMask | mask(31, lowIdx);
 205         }
 206         if (bits(byteMask, 2)) {
 207             bitMask = bitMask | mask(19, 16);
 208         }
 209         if (bits(byteMask, 1)) {
 210             unsigned highIdx = affectState ? 15 : 9;
 211             unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
 212                             ? 8 : 9;
 213             bitMask = bitMask | mask(highIdx, lowIdx);
 214         }
 215         if (bits(byteMask, 0)) {
 216             if (privileged) {
 217                 bitMask |= 1 << 7;
 218                 if ( (!nmfi || !((val >> 6) & 0x1)) &&
 219                      (isSecure || scr.fw || haveVirt) ) {
 220                     bitMask |= 1 << 6;
 221                 }
 222                 // Now check the new mode is allowed
 223                 OperatingMode newMode = (OperatingMode) (val & mask(5));
 224                 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
 225                 if (!badMode(newMode)) {
 226                     bool validModeChange = true;
 227                     // Check for attempts to enter modes only permitted in
 228                     // Secure state from Non-secure state. These are Monitor
 229                     // mode ('10110'), and FIQ mode ('10001') if the Security
 230                     // Extensions have reserved it.
 231                     if (!isSecure && newMode == MODE_MON)
 232                         validModeChange = false;
 233                     if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
 234                         validModeChange = false;
 235                     // There is no Hyp mode ('11010') in Secure state, so that
 236                     // is UNPREDICTABLE
 237                     if (scr.ns == '0' && newMode == MODE_HYP)
 238                         validModeChange = false;
 239                     // Cannot move into Hyp mode directly from a Non-secure
 240                     // PL1 mode
 241                     if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
 242                         validModeChange = false;
 243                     // Cannot move out of Hyp mode with this function except
 244                     // on an exception return
 245                     if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
 246                         validModeChange = false;
 247                     // Must not change to 64 bit when running in 32 bit mode
 248                     if (!opModeIs64(oldMode) && opModeIs64(newMode))
 249                         validModeChange = false;
 250
 251                     // If we passed all of the above then set the bit mask to
 252                     // copy the mode accross
 253                     if (validModeChange) {
 254                         bitMask = bitMask | mask(5);
 255                     } else {
 256                         warn_once("Illegal change to CPSR mode attempted\n");
 257                     }
 258                 } else {
 259                     warn_once("Ignoring write of bad mode to CPSR.\n");
 260                 }
 261             }
 262             if (affectState)
 263                 bitMask = bitMask | (1 << 5);
 264         }
 265
 266         return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
 267     }
 268
 269     static inline uint32_t
 270     spsrWriteByInstr(uint32_t spsr, uint32_t val,
 271             uint8_t byteMask, bool affectState)
 272     {
 273         uint32_t bitMask = 0;
 274
 275         if (bits(byteMask, 3))
 276             bitMask = bitMask | mask(31, 24);
 277         if (bits(byteMask, 2))
 278             bitMask = bitMask | mask(19, 16);
 279         if (bits(byteMask, 1))
 280             bitMask = bitMask | mask(15, 8);
 281         if (bits(byteMask, 0))
 282             bitMask = bitMask | mask(7, 0);
 283
 284         return ((spsr & ~bitMask) | (val & bitMask));
 285     }
 286
 287     template<class XC>
 288     static inline Addr
 289     readPC(XC *xc)
 290     {
 291         return xc->pcState().instPC();
 292     }
 293
 294     template<class XC>
 295     static inline void
 296     setNextPC(XC *xc, Addr val)
 297     {
 298         PCState pc = xc->pcState();
 299         pc.instNPC(val);
 300         xc->pcState(pc);
 301     }
 302
 303     template<class T>
 304     static inline T
 305     cSwap(T val, bool big)
 306     {
 307         if (big) {
 308             return gtobe(val);
 309         } else {
 310             return gtole(val);
 311         }
 312     }
 313
 314     template<class T, class E>
 315     static inline T
 316     cSwap(T val, bool big)
 317     {
 318         const unsigned count = sizeof(T) / sizeof(E);
 319         union {
 320             T tVal;
 321             E eVals[count];
 322         } conv;
 323         conv.tVal = htog(val);
 324         if (big) {
 325             for (unsigned i = 0; i < count; i++) {
 326                 conv.eVals[i] = gtobe(conv.eVals[i]);
 327             }
 328         } else {
 329             for (unsigned i = 0; i < count; i++) {
 330                 conv.eVals[i] = gtole(conv.eVals[i]);
 331             }
 332         }
 333         return gtoh(conv.tVal);
 334     }
 335
 336     // Perform an interworking branch.
 337     template<class XC>
 338     static inline void
 339     setIWNextPC(XC *xc, Addr val)
 340     {
 341         PCState pc = xc->pcState();
 342         pc.instIWNPC(val);
 343         xc->pcState(pc);
 344     }
 345
 346     // Perform an interworking branch in ARM mode, a regular branch
 347     // otherwise.
 348     template<class XC>
 349     static inline void
 350     setAIWNextPC(XC *xc, Addr val)
 351     {
 352         PCState pc = xc->pcState();
 353         pc.instAIWNPC(val);
 354         xc->pcState(pc);
 355     }
 356
 357     inline Fault
 358     disabledFault() const
 359     {
 360         return new UndefinedInstruction(machInst, false, mnemonic, true);
 361     }
 362
 363   public:
 364     virtual void
 365     annotateFault(ArmFault *fault) {}
 366 };
 367 }
 368
 369 #endif //__ARCH_ARM_INSTS_STATICINST_HH__