src/arch/arm/pagetable.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * Copyright (c) 2007-2008 The Florida State University
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are
   9  * met: redistributions of source code must retain the above copyright
  10  * notice, this list of conditions and the following disclaimer;
  11  * redistributions in binary form must reproduce the above copyright
  12  * notice, this list of conditions and the following disclaimer in the
  13  * documentation and/or other materials provided with the distribution;
  14  * neither the name of the copyright holders nor the names of its
  15  * contributors may be used to endorse or promote products derived from
  16  * this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * Authors: Nathan Binkert
  31  *          Steve Reinhardt
  32  *          Jaidev Patwardhan
  33  *          Stephen Hines
  34  */
  35
  36 #ifndef __ARCH_ARM_PAGETABLE_H__
  37 #define __ARCH_ARM_PAGETABLE_H__
  38
  39 #include "arch/arm/isa_traits.hh"
  40 #include "arch/arm/utility.hh"
  41 #include "arch/arm/vtophys.hh"
  42 #include "config/full_system.hh"
  43
  44 namespace ArmISA {
  45
  46     struct VAddr
  47     {
  48         static const int ImplBits = 43;
  49         static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
  50         static const Addr UnImplMask = ~ImplMask;
  51
  52         VAddr(Addr a) : addr(a) {}
  53         Addr addr;
  54         operator Addr() const { return addr; }
  55         const VAddr &operator=(Addr a) { addr = a; return *this; }
  56
  57         Addr vpn() const { return (addr & ImplMask) >> PageShift; }
  58         Addr page() const { return addr & Page_Mask; }
  59         Addr offset() const { return addr & PageOffset; }
  60
  61         Addr level3() const
  62         { return ArmISA::PteAddr(addr >> PageShift); }
  63         Addr level2() const
  64         { return ArmISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
  65         Addr level1() const
  66         { return ArmISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
  67     };
  68
  69     // ITB/DTB page table entry
  70     struct PTE
  71     {
  72       Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
  73       Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
  74       uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
  75
  76       bool G;    // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
  77
  78       /* Contents of Entry Lo0 */
  79       Addr PFN0; // Physical Frame Number - Even
  80       bool D0;   // Even entry Dirty Bit
  81       bool V0;   // Even entry Valid Bit
  82       uint8_t C0; // Cache Coherency Bits - Even
  83
  84       /* Contents of Entry Lo1 */
  85       Addr PFN1; // Physical Frame Number - Odd
  86       bool D1;   // Odd entry Dirty Bit
  87       bool V1;   // Odd entry Valid Bit
  88       uint8_t C1; // Cache Coherency Bits (3 bits)
  89
  90       /* The next few variables are put in as optimizations to reduce TLB lookup overheads */
  91       /* For a given Mask, what is the address shift amount, and what is the OffsetMask */
  92       int AddrShiftAmount;
  93       int OffsetMask;
  94
  95       bool Valid() { return (V0 | V1);};
  96         void serialize(std::ostream &os);
  97         void unserialize(Checkpoint *cp, const std::string &section);
  98     };
  99
 100 };
 101 #endif // __ARCH_ARM_PAGETABLE_H__
 102