mem: Use the new unbound port reporting mechanism in the mem ports.
[gem5.git] / src / arch / hsail / gpu_isa.hh
1 /*
2 * Copyright (c) 2016 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef __ARCH_HSAIL_GPU_ISA_HH__
35 #define __ARCH_HSAIL_GPU_ISA_HH__
36
37 #include <cstdint>
38
39 #include "arch/hsail/gpu_types.hh"
40 #include "base/logging.hh"
41 #include "base/types.hh"
42 #include "gpu-compute/misc.hh"
43
44 namespace HsailISA
45 {
46 class GPUISA
47 {
48 public:
49 GPUISA()
50 {
51 }
52
53 void
54 writeMiscReg(int opIdx, RegVal operandVal)
55 {
56 fatal("HSAIL does not implement misc registers yet\n");
57 }
58
59 RegVal
60 readMiscReg(int opIdx) const
61 {
62 fatal("HSAIL does not implement misc registers yet\n");
63 }
64
65 bool hasScalarUnit() const { return false; }
66
67 uint32_t
68 advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
69 {
70 return old_pc + sizeof(RawMachInst);
71 }
72 };
73 }
74
75 #endif // __ARCH_HSAIL_GPU_ISA_HH__