src/arch/mips/isa/formats/branch.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007 MIPS Technologies, Inc.
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  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // Control transfer instructions
  32 //
  33
  34 output header {{
  35
  36 #include <iostream>
  37     using namespace std;
  38
  39     /**
  40      * Base class for instructions whose disassembly is not purely a
  41      * function of the machine instruction (i.e., it depends on the
  42      * PC).  This class overrides the disassemble() method to check
  43      * the PC and symbol table values before re-using a cached
  44      * disassembly string.  This is necessary for branches and jumps,
  45      * where the disassembly string includes the target address (which
  46      * may depend on the PC and/or symbol table).
  47      */
  48     class PCDependentDisassembly : public MipsStaticInst
  49     {
  50       protected:
  51         /// Cached program counter from last disassembly
  52         mutable Addr cachedPC;
  53
  54         /// Cached symbol table pointer from last disassembly
  55         mutable const Loader::SymbolTable *cachedSymtab;
  56
  57         /// Constructor
  58         PCDependentDisassembly(const char *mnem, MachInst _machInst,
  59                                OpClass __opClass)
  60             : MipsStaticInst(mnem, _machInst, __opClass),
  61               cachedPC(0), cachedSymtab(0)
  62         {
  63         }
  64
  65         const std::string &
  66         disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
  67     };
  68
  69     /**
  70      * Base class for branches (PC-relative control transfers),
  71      * conditional or unconditional.
  72      */
  73     class Branch : public PCDependentDisassembly
  74     {
  75       protected:
  76         /// target address (signed) Displacement .
  77         int32_t disp;
  78
  79         /// Constructor.
  80         Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
  81             : PCDependentDisassembly(mnem, _machInst, __opClass),
  82               disp(OFFSET << 2)
  83         {
  84             //If Bit 17 is 1 then Sign Extend
  85             if ( (disp & 0x00020000) > 0  ) {
  86                 disp |= 0xFFFE0000;
  87             }
  88         }
  89
  90         MipsISA::PCState branchTarget(
  91                 const MipsISA::PCState &branchPC) const override;
  92
  93         /// Explicitly import the otherwise hidden branchTarget
  94         using StaticInst::branchTarget;
  95
  96         std::string generateDisassembly(
  97                 Addr pc, const Loader::SymbolTable *symtab) const override;
  98     };
  99
 100     /**
 101      * Base class for jumps (register-indirect control transfers).  In
 102      * the Mips ISA, these are always unconditional.
 103      */
 104     class Jump : public PCDependentDisassembly
 105     {
 106       protected:
 107
 108         /// Displacement to target address (signed).
 109         int32_t disp;
 110
 111         uint32_t target;
 112
 113       public:
 114         /// Constructor
 115         Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
 116             : PCDependentDisassembly(mnem, _machInst, __opClass),
 117               disp(JMPTARG << 2)
 118         {
 119         }
 120
 121         MipsISA::PCState branchTarget(ThreadContext *tc) const override;
 122
 123         /// Explicitly import the otherwise hidden branchTarget
 124         using StaticInst::branchTarget;
 125
 126         std::string generateDisassembly(
 127                 Addr pc, const Loader::SymbolTable *symtab) const override;
 128     };
 129 }};
 130
 131 output decoder {{
 132     MipsISA::PCState
 133     Branch::branchTarget(const MipsISA::PCState &branchPC) const
 134     {
 135         MipsISA::PCState target = branchPC;
 136         target.advance();
 137         target.npc(branchPC.pc() + sizeof(MachInst) + disp);
 138         target.nnpc(target.npc() + sizeof(MachInst));
 139         return target;
 140     }
 141
 142     MipsISA::PCState
 143     Jump::branchTarget(ThreadContext *tc) const
 144     {
 145         MipsISA::PCState target = tc->pcState();
 146         Addr pc = target.pc();
 147         target.advance();
 148         target.npc((pc & 0xF0000000) | disp);
 149         target.nnpc(target.npc() + sizeof(MachInst));
 150         return target;
 151     }
 152
 153     const std::string &
 154     PCDependentDisassembly::disassemble(
 155             Addr pc, const Loader::SymbolTable *symtab) const
 156     {
 157         if (!cachedDisassembly ||
 158             pc != cachedPC || symtab != cachedSymtab)
 159         {
 160             if (cachedDisassembly)
 161                 delete cachedDisassembly;
 162
 163             cachedDisassembly =
 164                 new std::string(generateDisassembly(pc, symtab));
 165             cachedPC = pc;
 166             cachedSymtab = symtab;
 167         }
 168
 169         return *cachedDisassembly;
 170     }
 171
 172     std::string
 173     Branch::generateDisassembly(
 174             Addr pc, const Loader::SymbolTable *symtab) const
 175     {
 176         std::stringstream ss;
 177
 178         ccprintf(ss, "%-10s ", mnemonic);
 179
 180         // There's only one register arg (RA), but it could be
 181         // either a source (the condition for conditional
 182         // branches) or a destination (the link reg for
 183         // unconditional branches)
 184         if (_numSrcRegs == 1) {
 185             printReg(ss, _srcRegIdx[0]);
 186             ss << ", ";
 187         } else if(_numSrcRegs == 2) {
 188             printReg(ss, _srcRegIdx[0]);
 189             ss << ", ";
 190             printReg(ss, _srcRegIdx[1]);
 191             ss << ", ";
 192         }
 193
 194         Addr target = pc + 4 + disp;
 195
 196         std::string str;
 197         if (symtab && symtab->findSymbol(target, str))
 198             ss << str;
 199         else
 200             ccprintf(ss, "0x%x", target);
 201
 202         return ss.str();
 203     }
 204
 205     std::string
 206     Jump::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 207     {
 208         std::stringstream ss;
 209
 210         ccprintf(ss, "%-10s ", mnemonic);
 211
 212         if ( strcmp(mnemonic,"jal") == 0 ) {
 213             Addr npc = pc + 4;
 214             ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
 215         } else if (_numSrcRegs == 0) {
 216             std::string str;
 217             if (symtab && symtab->findSymbol(disp, str))
 218                 ss << str;
 219             else
 220                 ccprintf(ss, "0x%x", disp);
 221         } else if (_numSrcRegs == 1) {
 222              printReg(ss, _srcRegIdx[0]);
 223         } else if(_numSrcRegs == 2) {
 224             printReg(ss, _srcRegIdx[0]);
 225             ss << ", ";
 226             printReg(ss, _srcRegIdx[1]);
 227         }
 228
 229         return ss.str();
 230     }
 231 }};
 232
 233 def format Branch(code, *opt_flags) {{
 234     not_taken_code = 'NNPC = NNPC; NPC = NPC;'
 235
 236     #Build Instruction Flags
 237     #Use Link & Likely Flags to Add Link/Condition Code
 238     inst_flags = ('IsDirectControl', )
 239     for x in opt_flags:
 240         if x == 'Link':
 241             code += 'R31 = NNPC;\n'
 242         elif x == 'Likely':
 243             not_taken_code = 'NNPC = NPC; NPC = PC;'
 244             inst_flags += ('IsCondDelaySlot', )
 245         else:
 246             inst_flags += (x, )
 247
 248     #Take into account uncond. branch instruction
 249     if 'cond = 1' in code:
 250          inst_flags += ('IsUncondControl', )
 251     else:
 252          inst_flags += ('IsCondControl', )
 253
 254     #Condition code
 255     code = '''
 256     bool cond;
 257     %(code)s
 258     if (cond) {
 259         NNPC = NPC + disp;
 260     } else {
 261         %(not_taken_code)s
 262     }
 263     ''' % { "code" : code, "not_taken_code" : not_taken_code }
 264
 265     iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
 266     header_output = BasicDeclare.subst(iop)
 267     decoder_output = BasicConstructor.subst(iop)
 268     decode_block = BasicDecode.subst(iop)
 269     exec_output = BasicExecute.subst(iop)
 270 }};
 271
 272 def format DspBranch(code, *opt_flags) {{
 273     not_taken_code = 'NNPC = NNPC; NPC = NPC;'
 274
 275     #Build Instruction Flags
 276     #Use Link & Likely Flags to Add Link/Condition Code
 277     inst_flags = ('IsDirectControl', )
 278     for x in opt_flags:
 279         if x == 'Link':
 280             code += 'R32 = NNPC;'
 281         elif x == 'Likely':
 282             not_taken_code = 'NNPC = NPC, NPC = PC;'
 283             inst_flags += ('IsCondDelaySlot', )
 284         else:
 285             inst_flags += (x, )
 286
 287     #Take into account uncond. branch instruction
 288     if 'cond = 1' in code:
 289          inst_flags += ('IsUncondControl', )
 290     else:
 291          inst_flags += ('IsCondControl', )
 292
 293     #Condition code
 294     code = '''
 295     bool cond;
 296     uint32_t dspctl = DSPControl;
 297     %(code)s
 298     if (cond) {
 299         NNPC = NPC + disp;
 300     } else {
 301         %(not_taken_code)s
 302     }
 303     ''' % { "code" : code, "not_taken_code" : not_taken_code }
 304
 305     iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
 306     header_output = BasicDeclare.subst(iop)
 307     decoder_output = BasicConstructor.subst(iop)
 308     decode_block = BasicDecode.subst(iop)
 309     exec_output = BasicExecute.subst(iop)
 310 }};
 311
 312 def format Jump(code, *opt_flags) {{
 313     #Build Instruction Flags
 314     #Use Link Flag to Add Link Code
 315     inst_flags = ('IsIndirectControl', 'IsUncondControl')
 316     for x in opt_flags:
 317         if x == 'Link':
 318             code = '''
 319             R31 = NNPC;
 320             ''' + code
 321         elif x == 'ClearHazards':
 322             code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
 323         else:
 324             inst_flags += (x, )
 325
 326     iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
 327     header_output = BasicDeclare.subst(iop)
 328     decoder_output = BasicConstructor.subst(iop)
 329     decode_block = BasicDecode.subst(iop)
 330     exec_output = BasicExecute.subst(iop)
 331 }};
 332
 333
 334
 335