src/arch/mips/utility.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Nathan Binkert
  30  *          Steve Reinhardt
  31  *          Korey Sewell
  32  */
  33
  34 #ifndef __ARCH_MIPS_UTILITY_HH__
  35 #define __ARCH_MIPS_UTILITY_HH__
  36 #include "arch/mips/isa_traits.hh"
  37 #include "arch/mips/types.hh"
  38 #include "base/misc.hh"
  39 #include "base/types.hh"
  40 #include "cpu/static_inst.hh"
  41 #include "cpu/thread_context.hh"
  42
  43 class ThreadContext;
  44
  45 namespace MipsISA {
  46
  47 inline PCState
  48 buildRetPC(const PCState &curPC, const PCState &callPC)
  49 {
  50     PCState ret = callPC;
  51     ret.advance();
  52     ret.pc(curPC.npc());
  53     return ret;
  54 }
  55
  56 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
  57
  58 ////////////////////////////////////////////////////////////////////////
  59 //
  60 // Floating Point Utility Functions
  61 //
  62 uint64_t fpConvert(ConvertType cvt_type, double fp_val);
  63 double roundFP(double val, int digits);
  64 double truncFP(double val);
  65
  66 bool getCondCode(uint32_t fcsr, int cc);
  67 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
  68 uint32_t genInvalidVector(uint32_t fcsr);
  69
  70 bool isNan(void *val_ptr, int size);
  71 bool isQnan(void *val_ptr, int size);
  72 bool isSnan(void *val_ptr, int size);
  73
  74 static inline bool
  75 inUserMode(ThreadContext *tc)
  76 {
  77     MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
  78     MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
  79
  80     if ((Stat & 0x10000006) == 0 &&  // EXL, ERL or CU0 set, CP0 accessible
  81         (Dbg & 0x40000000) == 0 &&   // DM bit set, CP0 accessible
  82         (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
  83         // Unable to use Status_CU0, etc directly, using bitfields & masks
  84         return true;
  85     } else {
  86         return false;
  87     }
  88 }
  89
  90 template <class CPU>
  91 void zeroRegisters(CPU *cpu);
  92
  93 ////////////////////////////////////////////////////////////////////////
  94 //
  95 //  Translation stuff
  96 //
  97 inline Addr
  98 TruncPage(Addr addr)
  99 { return addr & ~(PageBytes - 1); }
 100
 101 inline Addr
 102 RoundPage(Addr addr)
 103 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 104
 105 ////////////////////////////////////////////////////////////////////////
 106 //
 107 // CPU Utility
 108 //
 109 void startupCPU(ThreadContext *tc, int cpuId);
 110 void initCPU(ThreadContext *tc, int cpuId);
 111
 112 void copyRegs(ThreadContext *src, ThreadContext *dest);
 113 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 114
 115 void skipFunction(ThreadContext *tc);
 116
 117 inline void
 118 advancePC(PCState &pc, const StaticInstPtr &inst)
 119 {
 120     pc.advance();
 121 }
 122
 123 inline uint64_t
 124 getExecutingAsid(ThreadContext *tc)
 125 {
 126     return 0;
 127 }
 128
 129 };
 130
 131
 132 #endif