src/arch/power/isa/formats/condition.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
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   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
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  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  28 //
  29 // Authors: Timothy M. Jones
  30
  31 // Logical instructions that manipulate the condition register
  32 def format CondLogicOp(code, *flags) {{
  33         iop = InstObjParams(name, Name, 'CondLogicOp', code, flags)
  34         header_output = BasicDeclare.subst(iop)
  35         decoder_output = BasicConstructor.subst(iop)
  36         decode_block = BasicDecode.subst(iop)
  37         exec_output = BasicExecute.subst(iop)
  38 }};
  39
  40 // Instructions that condition register fields
  41 def format CondMoveOp(code, *flags) {{
  42         iop = InstObjParams(name, Name, 'CondMoveOp', code, flags)
  43         header_output = BasicDeclare.subst(iop)
  44         decoder_output = BasicConstructor.subst(iop)
  45         decode_block = BasicDecode.subst(iop)
  46         exec_output = BasicExecute.subst(iop)
  47 }};