src/arch/power/isa/formats/integer.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // Integer ALU instructions
  32 //
  33
  34
  35 // Instruction class constructor template when Rc is set.
  36 def template IntRcConstructor {{
  37     %(class_name)s::%(class_name)s(ExtMachInst machInst) :
  38         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
  39     {
  40         %(set_reg_idx_arr)s;
  41         %(constructor)s;
  42         rcSet = true;
  43     }
  44 }};
  45
  46
  47 // Instruction class constructor template when OE is set.
  48 def template IntOeConstructor {{
  49     %(class_name)s::%(class_name)s(ExtMachInst machInst) :
  50         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
  51     {
  52         %(set_reg_idx_arr)s;
  53         %(constructor)s;
  54         oeSet = true;
  55     }
  56 }};
  57
  58
  59 // Instruction class constructor template when both Rc and OE are set.
  60 def template IntRcOeConstructor {{
  61     %(class_name)s::%(class_name)s(ExtMachInst machInst) :
  62         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
  63     {
  64         %(set_reg_idx_arr)s;
  65         %(constructor)s;
  66         rcSet = true;
  67         oeSet = true;
  68     }
  69 }};
  70
  71
  72 let {{
  73
  74 readXERCode = 'Xer xer = XER;'
  75
  76 setXERCode = 'XER = xer;'
  77
  78 computeCR0Code = '''
  79     Cr cr = CR;
  80     cr.cr0 = makeCRField((int64_t)%(result)s, (int64_t)0, xer.so);
  81     CR = cr;
  82 '''
  83
  84 computeCACode = '''
  85     if (findCarry(64, %(result)s, %(inputa)s, %(inputb)s)) {
  86         xer.ca = 1;
  87     } else {
  88         xer.ca = 0;
  89     }
  90
  91     if (findCarry(32, %(result)s, %(inputa)s, %(inputb)s)) {
  92         xer.ca32 = 1;
  93     } else {
  94         xer.ca32 = 0;
  95     }
  96 '''
  97
  98 computeOVCode = '''
  99     if (findOverflow(64, %(result)s, %(inputa)s, %(inputb)s)) {
 100         xer.ov = 1;
 101         xer.so = 1;
 102     } else {
 103         xer.ov = 0;
 104     }
 105
 106     if (findOverflow(32, %(result)s, %(inputa)s, %(inputb)s)) {
 107         xer.ov32 = 1;
 108     } else {
 109         xer.ov32 = 0;
 110     }
 111 '''
 112
 113 setOVCode = '''
 114     if (setOV) {
 115         xer.ov = 1;
 116         xer.ov32 = 1;
 117         xer.so = 1;
 118     } else {
 119         xer.ov = 0;
 120         xer.ov32 = 0;
 121     }
 122 '''
 123
 124 }};
 125
 126
 127 // A basic integer instruction.
 128 def format IntOp(code, inst_flags = []) {{
 129     (header_output, decoder_output, decode_block, exec_output) = \
 130         GenAluOp(name, Name, 'IntOp', code, inst_flags, BasicDecode,
 131                  BasicConstructor)
 132 }};
 133
 134
 135 // Integer instructions with immediate (signed or unsigned).
 136 def format IntImmOp(code, inst_flags = []) {{
 137     (header_output, decoder_output, decode_block, exec_output) = \
 138         GenAluOp(name, Name, 'IntImmOp', code, inst_flags, BasicDecode,
 139                  BasicConstructor)
 140 }};
 141
 142
 143 // Integer instructions with immediate that perform arithmetic.
 144 // These instructions all write to Rt and use an altered form of the
 145 // value in source register Ra, hence the use of src to hold the actual
 146 // value. The control flags include the use of code to compute the
 147 // carry bit or the CR0 code.
 148 def format IntImmArithOp(code, computeCA = 0, computeCR0 = 0,
 149                          inst_flags = []) {{
 150
 151     # Set up the dictionary
 152     dict = {'result':'Rt', 'inputa':'src', 'inputb':'simm'}
 153
 154     # Deal with computing CR0 and carry
 155     if computeCA or computeCR0:
 156         code += readXERCode
 157     if computeCA:
 158         code += computeCACode % dict + setXERCode
 159     if computeCR0:
 160         code += computeCR0Code % dict
 161
 162     # Generate the class
 163     (header_output, decoder_output, decode_block, exec_output) = \
 164         GenAluOp(name, Name, 'IntImmArithOp', code, inst_flags, BasicDecode,
 165                  BasicConstructor)
 166 }};
 167
 168
 169 // Integer instructions with immediate that perform arithmetic but use
 170 // the value 0 when Ra == 0. We generate two versions of each instruction
 171 // corresponding to these two different scenarios. The correct version is
 172 // determined at decode (see the CheckRaDecode template).
 173 def format IntImmArithCheckRaOp(code, code_ra0, inst_flags = []) {{
 174
 175     # First the version where Ra is non-zero
 176     (header_output, decoder_output, decode_block, exec_output) = \
 177         GenAluOp(name, Name, 'IntImmArithOp', code, inst_flags,
 178                  CheckRaDecode, BasicConstructor)
 179
 180     # Now another version where Ra == 0
 181     (header_output_ra0, decoder_output_ra0, _, exec_output_ra0) = \
 182         GenAluOp(name, Name + 'RaZero', 'IntImmArithOp', code_ra0, inst_flags,
 183                  CheckRaDecode, BasicConstructor)
 184
 185     # Finally, add to the other outputs
 186     header_output += header_output_ra0
 187     decoder_output += decoder_output_ra0
 188     exec_output += exec_output_ra0
 189 }};
 190
 191
 192 // Integer instructions with immediate that perform logic operations.
 193 // All instructions write to Ra and use Rs as a source register. Some
 194 // also compute the CR0 code too.
 195 def format IntImmLogicOp(code, computeCR0 = 0, inst_flags = []) {{
 196
 197     # Set up the dictionary and deal with computing CR0
 198     dict = {'result':'Ra'}
 199     if computeCR0:
 200         code += readXERCode + computeCR0Code % dict
 201
 202     # Generate the class
 203     (header_output, decoder_output, decode_block, exec_output) = \
 204         GenAluOp(name, Name, 'IntImmOp', code, inst_flags, BasicDecode,
 205                  BasicConstructor)
 206 }};
 207
 208
 209 // Integer instructions with displacement that perform arithmetic.
 210 // There are no control flags to set.
 211 def format IntDispArithOp(code, inst_flags = []) {{
 212
 213     # Generate the class
 214     (header_output, decoder_output, decode_block, exec_output) = \
 215         GenAluOp(name, Name, 'IntDispArithOp', code, inst_flags, BasicDecode,
 216                  BasicConstructor)
 217 }};
 218
 219
 220 // Integer instructions that perform logic operations. The result is
 221 // always written into Ra. All instructions have 2 versions depending on
 222 // whether the Rc bit is set to compute the CR0 code. This is determined
 223 // at decode as before.
 224 def format IntLogicOp(code, inst_flags = []) {{
 225     dict = {'result':'Ra'}
 226
 227     # Code when Rc is set
 228     code_rc1 = code + readXERCode + computeCR0Code % dict
 229
 230     # Generate the first class
 231     (header_output, decoder_output, decode_block, exec_output) = \
 232         GenAluOp(name, Name, 'IntOp', code, inst_flags,
 233                  CheckRcDecode, BasicConstructor)
 234
 235     # Generate the second class
 236     (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
 237         GenAluOp(name, Name + 'RcSet', 'IntOp', code_rc1, inst_flags,
 238                  CheckRcDecode, IntRcConstructor)
 239
 240     # Finally, add to the other outputs
 241     header_output += header_output_rc1
 242     decoder_output += decoder_output_rc1
 243     exec_output += exec_output_rc1
 244 }};
 245
 246
 247 // Integer instructions with a shift amount. As above, except inheriting
 248 // from the IntShiftOp class.
 249 def format IntShiftOp(code, inst_flags = []) {{
 250     dict = {'result':'Ra'}
 251
 252     # Code when Rc is set
 253     code_rc1 = code + readXERCode + computeCR0Code % dict
 254
 255     # Generate the first class
 256     (header_output, decoder_output, decode_block, exec_output) = \
 257         GenAluOp(name, Name, 'IntShiftOp', code, inst_flags,
 258                  CheckRcDecode, BasicConstructor)
 259
 260     # Generate the second class
 261     (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
 262         GenAluOp(name, Name + 'RcSet', 'IntShiftOp', code_rc1, inst_flags,
 263                  CheckRcDecode, IntRcConstructor)
 264
 265     # Finally, add to the other outputs
 266     header_output += header_output_rc1
 267     decoder_output += decoder_output_rc1
 268     exec_output += exec_output_rc1
 269 }};
 270
 271
 272 // Instructions in this format are all reduced to the form Rt = src1 + src2,
 273 // therefore we just give src1 and src2 definitions. In working out the
 274 // template we first put in the definitions of the variables and then
 275 // the code for the addition. We also deal with computing the carry flag
 276 // if required.
 277 //
 278 // We generate 4 versions of each instruction. This correspond to the
 279 // different combinations of having the OE bit set or unset (which controls
 280 // whether the overflow flag is computed) and the Rc bit set or unset too
 281 // (which controls whether the CR0 code is computed).
 282 def format IntSumOp(src1, src2, ca = {{ 0 }}, computeCA = 0,
 283                     inst_flags = []) {{
 284
 285     # The result is always in Rt, but the source values vary
 286     dict = {'result':'Rt', 'inputa':'src1', 'inputb':'src2'}
 287
 288     # Add code to set up variables and do the sum
 289     code  = 'uint64_t src1 = ' + src1 + ';\n'
 290     code += 'uint64_t src2 = ' + src2 + ';\n'
 291     code += 'uint64_t ca = ' + ca + ';\n'
 292     code += 'Rt = src1 + src2 + ca;\n'
 293
 294     # Add code for calculating the carry, if needed
 295     if computeCA:
 296         code += computeCACode % dict + setXERCode
 297
 298     # Setup the 4 code versions and add code to access XER if necessary
 299     code_rc1 = readXERCode + code
 300     code_oe1 = readXERCode + code + computeOVCode % dict + setXERCode
 301     code_rc1_oe1 = readXERCode + code + computeOVCode % dict + setXERCode
 302     if (computeCA or ca == 'xer.ca'):
 303         code = readXERCode + code
 304     code_rc1 += computeCR0Code % dict
 305     code_rc1_oe1 += computeCR0Code % dict
 306
 307     # Generate the classes
 308     (header_output, decoder_output, decode_block, exec_output) = \
 309         GenAluOp(name, Name, 'IntArithOp', code, inst_flags,
 310                  CheckRcOeDecode, BasicConstructor)
 311     (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
 312         GenAluOp(name, Name + 'RcSet', 'IntArithOp', code_rc1, inst_flags,
 313                  CheckRcOeDecode, IntRcConstructor)
 314     (header_output_oe1, decoder_output_oe1, _, exec_output_oe1) = \
 315         GenAluOp(name, Name + 'OeSet', 'IntArithOp', code_oe1, inst_flags,
 316                  CheckRcOeDecode, IntOeConstructor)
 317     (header_output_rc1_oe1, decoder_output_rc1_oe1, _, exec_output_rc1_oe1) = \
 318         GenAluOp(name, Name + 'RcSetOeSet', 'IntArithOp', code_rc1_oe1,
 319                  inst_flags, CheckRcOeDecode, IntRcOeConstructor)
 320
 321     # Finally, add to the other outputs
 322     header_output += \
 323         header_output_rc1 + header_output_oe1 + header_output_rc1_oe1
 324     decoder_output += \
 325         decoder_output_rc1 + decoder_output_oe1 + decoder_output_rc1_oe1
 326     exec_output += \
 327         exec_output_rc1 + exec_output_oe1 + exec_output_rc1_oe1
 328
 329 }};
 330
 331
 332 // Instructions that use source registers Ra and Rb, with the result
 333 // placed into Rt. Basically multiply and divide instructions. The
 334 // carry bit is never set, but overflow can be calculated. In certain
 335 // situations, the overflow bits have to be set and this is dealt with
 336 // using the 'setOV' boolean in decoder.isa.
 337 //
 338 // In case overflow is to be calculated, we generate four versions of
 339 // each instruction to deal with different combinations of having the
 340 // OE bit set or unset and the Rc bit set or unset too. Otherwise, we
 341 // generate two versions of each instruction to deal with the Rc bit.
 342 def format IntArithCheckRcOp(code, computeOV = 0, inst_flags = []) {{
 343
 344     # The result is always in Rt, but the source values vary
 345     dict = {'result':'Rt', 'inputa':'src1', 'inputb':'src2'}
 346
 347     # Deal with setting the overflow flag
 348     if computeOV:
 349         # Setup the 4 code versions and add code to access XER if necessary
 350         code  = 'M5_VAR_USED bool setOV = false;\n' + code
 351         code_rc1 = readXERCode + code + computeCR0Code % dict
 352         code_oe1 = readXERCode + code + setOVCode + setXERCode
 353         code_rc1_oe1 = readXERCode + code + setOVCode + setXERCode
 354         code_rc1_oe1 += computeCR0Code % dict
 355
 356         # Generate the classes
 357         (header_output, decoder_output, decode_block, exec_output) = \
 358             GenAluOp(name, Name, 'IntArithOp', code, inst_flags,
 359                      CheckRcOeDecode, BasicConstructor)
 360         (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
 361             GenAluOp(name, Name + 'RcSet', 'IntArithOp', code_rc1, inst_flags,
 362                      CheckRcOeDecode, IntRcConstructor)
 363         (header_output_oe1, decoder_output_oe1, _, exec_output_oe1) = \
 364             GenAluOp(name, Name + 'OeSet', 'IntArithOp', code_oe1, inst_flags,
 365                      CheckRcOeDecode, IntOeConstructor)
 366         (header_output_rc1_oe1, decoder_output_rc1_oe1, _,
 367          exec_output_rc1_oe1) = \
 368             GenAluOp(name, Name + 'RcSetOeSet', 'IntArithOp', code_rc1_oe1,
 369                      inst_flags, CheckRcOeDecode, IntRcOeConstructor)
 370
 371         # Finally, add to the other outputs
 372         header_output += \
 373             header_output_rc1 + header_output_oe1 + header_output_rc1_oe1
 374         decoder_output += \
 375             decoder_output_rc1 + decoder_output_oe1 + decoder_output_rc1_oe1
 376         exec_output += \
 377             exec_output_rc1 + exec_output_oe1 + exec_output_rc1_oe1
 378
 379     else:
 380         # Setup the 2 code versions and add code to access XER if necessary
 381         code_rc1 = readXERCode + code + computeCR0Code % dict
 382
 383         # Generate the first class
 384         (header_output, decoder_output, decode_block, exec_output) = \
 385             GenAluOp(name, Name, 'IntArithOp', code, inst_flags,
 386                      CheckRcDecode, BasicConstructor)
 387
 388         # Generate the second class
 389         (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
 390             GenAluOp(name, Name + 'RcSet', 'IntArithOp', code_rc1, inst_flags,
 391                      CheckRcDecode, IntRcConstructor)
 392
 393         # Finally, add to the other outputs
 394         header_output += header_output_rc1
 395         decoder_output += decoder_output_rc1
 396         exec_output += exec_output_rc1
 397 }};
 398
 399
 400 // A special format for rotate instructions which use certain fields
 401 // from the instruction's binary encoding. We need two versions for each
 402 // instruction to deal with the Rc bit.
 403 def format IntRotateOp(code, inst_flags = []) {{
 404
 405     # The result is always in Ra
 406     dict = {'result':'Ra'}
 407
 408     # Setup the code for when Rc is set
 409     code_rc1 = readXERCode + code + computeCR0Code % dict
 410
 411     # Generate the first class
 412     (header_output, decoder_output, decode_block, exec_output) = \
 413         GenAluOp(name, Name, 'IntRotateOp', code, inst_flags,
 414                  CheckRcDecode, BasicConstructor)
 415
 416     # Generate the second class
 417     (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
 418         GenAluOp(name, Name + 'RcSet', 'IntRotateOp', code_rc1, inst_flags,
 419                  CheckRcDecode, IntRcConstructor)
 420
 421     # Finally, add to the other outputs
 422     header_output += header_output_rc1
 423     decoder_output += decoder_output_rc1
 424     exec_output += exec_output_rc1
 425 }};