2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include "arch/x86/process.hh"
50 #include "arch/x86/isa_traits.hh"
51 #include "arch/x86/regs/misc.hh"
52 #include "arch/x86/regs/segment.hh"
53 #include "arch/x86/system.hh"
54 #include "arch/x86/types.hh"
55 #include "base/loader/elf_object.hh"
56 #include "base/loader/object_file.hh"
57 #include "base/logging.hh"
58 #include "base/trace.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/Stack.hh"
61 #include "mem/multi_level_page_table.hh"
62 #include "mem/page_table.hh"
63 #include "sim/aux_vector.hh"
64 #include "sim/process_impl.hh"
65 #include "sim/syscall_desc.hh"
66 #include "sim/syscall_return.hh"
67 #include "sim/system.hh"
70 using namespace X86ISA
;
72 static const int ArgumentReg
[] = {
76 // This argument register is r10 for syscalls and rcx for C.
83 static const int NumArgumentRegs M5_VAR_USED
=
84 sizeof(ArgumentReg
) / sizeof(const int);
86 static const int ArgumentReg32
[] = {
95 static const int NumArgumentRegs32 M5_VAR_USED
=
96 sizeof(ArgumentReg
) / sizeof(const int);
98 X86Process::X86Process(ProcessParams
* params
, ObjectFile
*objFile
,
99 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
100 : Process(params
, objFile
), syscallDescs(_syscallDescs
),
101 numSyscallDescs(_numSyscallDescs
)
105 void X86Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
106 Process
*p
, TheISA::IntReg flags
)
108 Process::clone(old_tc
, new_tc
, p
, flags
);
109 X86Process
*process
= (X86Process
*)p
;
113 X86_64Process::X86_64Process(ProcessParams
*params
, ObjectFile
*objFile
,
114 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
115 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
118 vsyscallPage
.base
= 0xffffffffff600000ULL
;
119 vsyscallPage
.size
= PageBytes
;
120 vsyscallPage
.vtimeOffset
= 0x400;
121 vsyscallPage
.vgettimeofdayOffset
= 0x0;
123 Addr brk_point
= roundUp(objFile
->dataBase() + objFile
->dataSize() +
124 objFile
->bssSize(), PageBytes
);
125 Addr stack_base
= 0x7FFFFFFFF000ULL
;
126 Addr max_stack_size
= 8 * 1024 * 1024;
127 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
128 Addr mmap_end
= 0x7FFFF7FFF000ULL
;
130 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
131 next_thread_stack_base
, mmap_end
);
135 I386Process::syscall(int64_t callnum
, ThreadContext
*tc
, Fault
*fault
)
137 TheISA::PCState pc
= tc
->pcState();
139 if (eip
>= vsyscallPage
.base
&&
140 eip
< vsyscallPage
.base
+ vsyscallPage
.size
) {
141 pc
.npc(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
);
144 X86Process::syscall(callnum
, tc
, fault
);
148 I386Process::I386Process(ProcessParams
*params
, ObjectFile
*objFile
,
149 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
150 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
152 _gdtStart
= ULL(0xffffd000);
153 _gdtSize
= PageBytes
;
155 vsyscallPage
.base
= 0xffffe000ULL
;
156 vsyscallPage
.size
= PageBytes
;
157 vsyscallPage
.vsyscallOffset
= 0x400;
158 vsyscallPage
.vsysexitOffset
= 0x410;
160 Addr brk_point
= roundUp(objFile
->dataBase() + objFile
->dataSize() +
161 objFile
->bssSize(), PageBytes
);
162 Addr stack_base
= _gdtStart
;
163 Addr max_stack_size
= 8 * 1024 * 1024;
164 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
165 Addr mmap_end
= 0xB7FFF000ULL
;
167 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
168 next_thread_stack_base
, mmap_end
);
172 X86Process::getDesc(int callnum
)
174 if (callnum
< 0 || callnum
>= numSyscallDescs
)
176 return &syscallDescs
[callnum
];
180 X86_64Process::initState()
182 X86Process::initState();
186 // Set up the vsyscall page for this process.
187 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
188 uint8_t vtimeBlob
[] = {
189 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
190 0x0f,0x05, // syscall
193 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vtimeOffset
,
194 vtimeBlob
, sizeof(vtimeBlob
));
196 uint8_t vgettimeofdayBlob
[] = {
197 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
198 0x0f,0x05, // syscall
201 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vgettimeofdayOffset
,
202 vgettimeofdayBlob
, sizeof(vgettimeofdayBlob
));
205 PortProxy physProxy
= system
->physProxy
;
210 uint8_t numGDTEntries
= 0;
211 uint64_t nullDescriptor
= 0;
212 physProxy
.writeBlob(GDTPhysAddr
+ numGDTEntries
* 8,
213 (uint8_t *)(&nullDescriptor
), 8);
216 SegDescriptor initDesc
= 0;
217 initDesc
.type
.codeOrData
= 0; // code or data type
218 initDesc
.type
.c
= 0; // conforming
219 initDesc
.type
.r
= 1; // readable
220 initDesc
.dpl
= 0; // privilege
221 initDesc
.p
= 1; // present
222 initDesc
.l
= 1; // longmode - 64 bit
223 initDesc
.d
= 0; // operand size
224 initDesc
.g
= 1; // granularity
225 initDesc
.s
= 1; // system segment
226 initDesc
.limitHigh
= 0xFFFF;
227 initDesc
.limitLow
= 0xF;
228 initDesc
.baseHigh
= 0x0;
229 initDesc
.baseLow
= 0x0;
231 //64 bit code segment
232 SegDescriptor csLowPLDesc
= initDesc
;
233 csLowPLDesc
.type
.codeOrData
= 1;
235 uint64_t csLowPLDescVal
= csLowPLDesc
;
236 physProxy
.writeBlob(GDTPhysAddr
+ numGDTEntries
* 8,
237 (uint8_t *)(&csLowPLDescVal
), 8);
241 SegSelector csLowPL
= 0;
242 csLowPL
.si
= numGDTEntries
- 1;
245 //64 bit data segment
246 SegDescriptor dsLowPLDesc
= initDesc
;
247 dsLowPLDesc
.type
.codeOrData
= 0;
249 uint64_t dsLowPLDescVal
= dsLowPLDesc
;
250 physProxy
.writeBlob(GDTPhysAddr
+ numGDTEntries
* 8,
251 (uint8_t *)(&dsLowPLDescVal
), 8);
255 SegSelector dsLowPL
= 0;
256 dsLowPL
.si
= numGDTEntries
- 1;
259 //64 bit data segment
260 SegDescriptor dsDesc
= initDesc
;
261 dsDesc
.type
.codeOrData
= 0;
263 uint64_t dsDescVal
= dsDesc
;
264 physProxy
.writeBlob(GDTPhysAddr
+ numGDTEntries
* 8,
265 (uint8_t *)(&dsDescVal
), 8);
270 ds
.si
= numGDTEntries
- 1;
273 //64 bit code segment
274 SegDescriptor csDesc
= initDesc
;
275 csDesc
.type
.codeOrData
= 1;
277 uint64_t csDescVal
= csDesc
;
278 physProxy
.writeBlob(GDTPhysAddr
+ numGDTEntries
* 8,
279 (uint8_t *)(&csDescVal
), 8);
284 cs
.si
= numGDTEntries
- 1;
287 SegSelector scall
= 0;
288 scall
.si
= csLowPL
.si
;
291 SegSelector sret
= 0;
292 sret
.si
= dsLowPL
.si
;
295 /* In long mode the TSS has been extended to 16 Bytes */
296 TSSlow TSSDescLow
= 0;
297 TSSDescLow
.type
= 0xB;
298 TSSDescLow
.dpl
= 0; // Privelege level 0
299 TSSDescLow
.p
= 1; // Present
300 TSSDescLow
.g
= 1; // Page granularity
301 TSSDescLow
.limitHigh
= 0xF;
302 TSSDescLow
.limitLow
= 0xFFFF;
303 TSSDescLow
.baseLow
= bits(TSSVirtAddr
, 23, 0);
304 TSSDescLow
.baseHigh
= bits(TSSVirtAddr
, 31, 24);
306 TSShigh TSSDescHigh
= 0;
307 TSSDescHigh
.base
= bits(TSSVirtAddr
, 63, 32);
312 } tssDescVal
= {TSSDescLow
, TSSDescHigh
};
314 physProxy
.writeBlob(GDTPhysAddr
+ numGDTEntries
* 8,
315 (uint8_t *)(&tssDescVal
), sizeof(tssDescVal
));
319 SegSelector tssSel
= 0;
320 tssSel
.si
= numGDTEntries
- 1;
322 uint64_t tss_base_addr
= (TSSDescHigh
.base
<< 32) |
323 (TSSDescLow
.baseHigh
<< 24) |
325 uint64_t tss_limit
= TSSDescLow
.limitLow
| (TSSDescLow
.limitHigh
<< 16);
327 SegAttr tss_attr
= 0;
329 tss_attr
.type
= TSSDescLow
.type
;
330 tss_attr
.dpl
= TSSDescLow
.dpl
;
331 tss_attr
.present
= TSSDescLow
.p
;
332 tss_attr
.granularity
= TSSDescLow
.g
;
333 tss_attr
.unusable
= 0;
335 for (int i
= 0; i
< contextIds
.size(); i
++) {
336 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
338 tc
->setMiscReg(MISCREG_CS
, cs
);
339 tc
->setMiscReg(MISCREG_DS
, ds
);
340 tc
->setMiscReg(MISCREG_ES
, ds
);
341 tc
->setMiscReg(MISCREG_FS
, ds
);
342 tc
->setMiscReg(MISCREG_GS
, ds
);
343 tc
->setMiscReg(MISCREG_SS
, ds
);
346 tc
->setMiscReg(MISCREG_TSL
, 0);
350 tc
->setMiscReg(MISCREG_TSL_ATTR
, tslAttr
);
352 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
353 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
355 tc
->setMiscReg(MISCREG_TR
, tssSel
);
356 tc
->setMiscReg(MISCREG_TR_BASE
, tss_base_addr
);
357 tc
->setMiscReg(MISCREG_TR_EFF_BASE
, 0);
358 tc
->setMiscReg(MISCREG_TR_LIMIT
, tss_limit
);
359 tc
->setMiscReg(MISCREG_TR_ATTR
, tss_attr
);
361 //Start using longmode segments.
362 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
363 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
364 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
365 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
366 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
367 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
370 efer
.sce
= 1; // Enable system call extensions.
371 efer
.lme
= 1; // Enable long mode.
372 efer
.lma
= 1; // Activate long mode.
373 efer
.nxe
= 0; // Enable nx support.
374 efer
.svme
= 1; // Enable svm support for now.
375 efer
.ffxsr
= 0; // Turn on fast fxsave and fxrstor.
376 tc
->setMiscReg(MISCREG_EFER
, efer
);
378 //Set up the registers that describe the operating mode.
380 cr0
.pg
= 1; // Turn on paging.
381 cr0
.cd
= 0; // Don't disable caching.
382 cr0
.nw
= 0; // This is bit is defined to be ignored.
383 cr0
.am
= 1; // No alignment checking
384 cr0
.wp
= 1; // Supervisor mode can write read only pages
386 cr0
.et
= 1; // This should always be 1
387 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
388 // would be pointless.
389 cr0
.em
= 0; // Allow x87 instructions to execute natively.
390 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
391 // setting it to one.
392 cr0
.pe
= 1; // We're definitely in protected mode.
393 tc
->setMiscReg(MISCREG_CR0
, cr0
);
396 tc
->setMiscReg(MISCREG_CR2
, cr2
);
398 CR3 cr3
= pageTablePhysAddr
;
399 tc
->setMiscReg(MISCREG_CR3
, cr3
);
403 cr4
.osxsave
= 1; // Enable XSAVE and Proc Extended States
404 cr4
.osxmmexcpt
= 1; // Operating System Unmasked Exception
405 cr4
.osfxsr
= 1; // Operating System FXSave/FSRSTOR Support
406 cr4
.pce
= 0; // Performance-Monitoring Counter Enable
407 cr4
.pge
= 0; // Page-Global Enable
408 cr4
.mce
= 0; // Machine Check Enable
409 cr4
.pae
= 1; // Physical-Address Extension
410 cr4
.pse
= 0; // Page Size Extensions
411 cr4
.de
= 0; // Debugging Extensions
412 cr4
.tsd
= 0; // Time Stamp Disable
413 cr4
.pvi
= 0; // Protected-Mode Virtual Interrupts
414 cr4
.vme
= 0; // Virtual-8086 Mode Extensions
416 tc
->setMiscReg(MISCREG_CR4
, cr4
);
419 tc
->setMiscReg(MISCREG_CR8
, cr8
);
421 const Addr PageMapLevel4
= pageTablePhysAddr
;
422 //Point to the page tables.
423 tc
->setMiscReg(MISCREG_CR3
, PageMapLevel4
);
425 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
427 tc
->setMiscReg(MISCREG_APIC_BASE
, 0xfee00900);
429 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
430 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
432 tc
->setMiscReg(MISCREG_IDTR_BASE
, IDTVirtAddr
);
433 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
435 /* enabling syscall and sysret */
436 MiscReg star
= ((MiscReg
)sret
<< 48) | ((MiscReg
)scall
<< 32);
437 tc
->setMiscReg(MISCREG_STAR
, star
);
438 MiscReg lstar
= (MiscReg
)syscallCodeVirtAddr
;
439 tc
->setMiscReg(MISCREG_LSTAR
, lstar
);
440 MiscReg sfmask
= (1 << 8) | (1 << 10); // TF | DF
441 tc
->setMiscReg(MISCREG_SF_MASK
, sfmask
);
444 /* Set up the content of the TSS and write it to physical memory. */
447 uint32_t reserved0
; // +00h
448 uint32_t RSP0_low
; // +04h
449 uint32_t RSP0_high
; // +08h
450 uint32_t RSP1_low
; // +0Ch
451 uint32_t RSP1_high
; // +10h
452 uint32_t RSP2_low
; // +14h
453 uint32_t RSP2_high
; // +18h
454 uint32_t reserved1
; // +1Ch
455 uint32_t reserved2
; // +20h
456 uint32_t IST1_low
; // +24h
457 uint32_t IST1_high
; // +28h
458 uint32_t IST2_low
; // +2Ch
459 uint32_t IST2_high
; // +30h
460 uint32_t IST3_low
; // +34h
461 uint32_t IST3_high
; // +38h
462 uint32_t IST4_low
; // +3Ch
463 uint32_t IST4_high
; // +40h
464 uint32_t IST5_low
; // +44h
465 uint32_t IST5_high
; // +48h
466 uint32_t IST6_low
; // +4Ch
467 uint32_t IST6_high
; // +50h
468 uint32_t IST7_low
; // +54h
469 uint32_t IST7_high
; // +58h
470 uint32_t reserved3
; // +5Ch
471 uint32_t reserved4
; // +60h
472 uint16_t reserved5
; // +64h
473 uint16_t IO_MapBase
; // +66h
476 /** setting Interrupt Stack Table */
477 uint64_t IST_start
= ISTVirtAddr
+ PageBytes
;
478 tss
.IST1_low
= IST_start
;
479 tss
.IST1_high
= IST_start
>> 32;
480 tss
.RSP0_low
= tss
.IST1_low
;
481 tss
.RSP0_high
= tss
.IST1_high
;
482 tss
.RSP1_low
= tss
.IST1_low
;
483 tss
.RSP1_high
= tss
.IST1_high
;
484 tss
.RSP2_low
= tss
.IST1_low
;
485 tss
.RSP2_high
= tss
.IST1_high
;
486 physProxy
.writeBlob(TSSPhysAddr
, (uint8_t *)(&tss
), sizeof(tss
));
488 /* Setting IDT gates */
489 GateDescriptorLow PFGateLow
= 0;
490 PFGateLow
.offsetHigh
= bits(PFHandlerVirtAddr
, 31, 16);
491 PFGateLow
.offsetLow
= bits(PFHandlerVirtAddr
, 15, 0);
492 PFGateLow
.selector
= csLowPL
;
495 PFGateLow
.type
= 0xe; // gate interrupt type
496 PFGateLow
.IST
= 0; // setting IST to 0 and using RSP0
498 GateDescriptorHigh PFGateHigh
= 0;
499 PFGateHigh
.offset
= bits(PFHandlerVirtAddr
, 63, 32);
504 } PFGate
= {PFGateLow
, PFGateHigh
};
506 physProxy
.writeBlob(IDTPhysAddr
+ 0xE0,
507 (uint8_t *)(&PFGate
), sizeof(PFGate
));
509 /* System call handler */
510 uint8_t syscallBlob
[] = {
511 // mov %rax, (0xffffc90000005600)
512 0x48, 0xa3, 0x00, 0x60, 0x00,
513 0x00, 0x00, 0xc9, 0xff, 0xff,
518 physProxy
.writeBlob(syscallCodePhysAddr
,
519 syscallBlob
, sizeof(syscallBlob
));
521 /** Page fault handler */
522 uint8_t faultBlob
[] = {
523 // mov %rax, (0xffffc90000005700)
524 0x48, 0xa3, 0x00, 0x61, 0x00,
525 0x00, 0x00, 0xc9, 0xff, 0xff,
526 // add $0x8, %rsp # skip error
527 0x48, 0x83, 0xc4, 0x08,
532 physProxy
.writeBlob(PFHandlerPhysAddr
, faultBlob
, sizeof(faultBlob
));
534 MultiLevelPageTable
<PageTableOps
> *pt
=
535 dynamic_cast<MultiLevelPageTable
<PageTableOps
> *>(pTable
);
537 /* Syscall handler */
538 pt
->map(syscallCodeVirtAddr
, syscallCodePhysAddr
, PageBytes
, false);
540 pt
->map(GDTVirtAddr
, GDTPhysAddr
, PageBytes
, false);
542 pt
->map(IDTVirtAddr
, IDTPhysAddr
, PageBytes
, false);
544 pt
->map(TSSVirtAddr
, TSSPhysAddr
, PageBytes
, false);
546 pt
->map(ISTVirtAddr
, ISTPhysAddr
, PageBytes
, false);
548 pt
->map(PFHandlerVirtAddr
, PFHandlerPhysAddr
, PageBytes
, false);
549 /* MMIO region for m5ops */
550 pt
->map(MMIORegionVirtAddr
, MMIORegionPhysAddr
, 16*PageBytes
, false);
552 for (int i
= 0; i
< contextIds
.size(); i
++) {
553 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
555 SegAttr dataAttr
= 0;
557 dataAttr
.unusable
= 0;
558 dataAttr
.defaultSize
= 1;
559 dataAttr
.longMode
= 1;
561 dataAttr
.granularity
= 1;
562 dataAttr
.present
= 1;
564 dataAttr
.writable
= 1;
565 dataAttr
.readable
= 1;
566 dataAttr
.expandDown
= 0;
569 // Initialize the segment registers.
570 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
571 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
572 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
573 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
579 csAttr
.defaultSize
= 0;
582 csAttr
.granularity
= 1;
587 csAttr
.expandDown
= 0;
590 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
593 efer
.sce
= 1; // Enable system call extensions.
594 efer
.lme
= 1; // Enable long mode.
595 efer
.lma
= 1; // Activate long mode.
596 efer
.nxe
= 1; // Enable nx support.
597 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
598 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
599 tc
->setMiscReg(MISCREG_EFER
, efer
);
601 // Set up the registers that describe the operating mode.
603 cr0
.pg
= 1; // Turn on paging.
604 cr0
.cd
= 0; // Don't disable caching.
605 cr0
.nw
= 0; // This is bit is defined to be ignored.
606 cr0
.am
= 0; // No alignment checking
607 cr0
.wp
= 0; // Supervisor mode can write read only pages
609 cr0
.et
= 1; // This should always be 1
610 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
611 // would be pointless.
612 cr0
.em
= 0; // Allow x87 instructions to execute natively.
613 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
614 // setting it to one.
615 cr0
.pe
= 1; // We're definitely in protected mode.
616 tc
->setMiscReg(MISCREG_CR0
, cr0
);
618 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
624 I386Process::initState()
626 X86Process::initState();
631 * Set up a GDT for this process. The whole GDT wouldn't really be for
632 * this process, but the only parts we care about are.
634 allocateMem(_gdtStart
, _gdtSize
);
636 assert(_gdtSize
% sizeof(zero
) == 0);
637 for (Addr gdtCurrent
= _gdtStart
;
638 gdtCurrent
< _gdtStart
+ _gdtSize
; gdtCurrent
+= sizeof(zero
)) {
639 initVirtMem
.write(gdtCurrent
, zero
);
642 // Set up the vsyscall page for this process.
643 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
644 uint8_t vsyscallBlob
[] = {
648 0x89, 0xe5, // mov %esp, %ebp
649 0x0f, 0x34 // sysenter
651 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
,
652 vsyscallBlob
, sizeof(vsyscallBlob
));
654 uint8_t vsysexitBlob
[] = {
660 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
,
661 vsysexitBlob
, sizeof(vsysexitBlob
));
663 for (int i
= 0; i
< contextIds
.size(); i
++) {
664 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
666 SegAttr dataAttr
= 0;
668 dataAttr
.unusable
= 0;
669 dataAttr
.defaultSize
= 1;
670 dataAttr
.longMode
= 0;
672 dataAttr
.granularity
= 1;
673 dataAttr
.present
= 1;
675 dataAttr
.writable
= 1;
676 dataAttr
.readable
= 1;
677 dataAttr
.expandDown
= 0;
680 // Initialize the segment registers.
681 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
682 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
683 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
684 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
685 tc
->setMiscRegNoEffect(MISCREG_SEG_SEL(seg
), 0xB);
686 tc
->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
), (uint32_t)(-1));
692 csAttr
.defaultSize
= 1;
695 csAttr
.granularity
= 1;
700 csAttr
.expandDown
= 0;
703 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
705 tc
->setMiscRegNoEffect(MISCREG_TSG_BASE
, _gdtStart
);
706 tc
->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE
, _gdtStart
);
707 tc
->setMiscRegNoEffect(MISCREG_TSG_LIMIT
, _gdtStart
+ _gdtSize
- 1);
709 // Set the LDT selector to 0 to deactivate it.
710 tc
->setMiscRegNoEffect(MISCREG_TSL
, 0);
713 efer
.sce
= 1; // Enable system call extensions.
714 efer
.lme
= 1; // Enable long mode.
715 efer
.lma
= 0; // Deactivate long mode.
716 efer
.nxe
= 1; // Enable nx support.
717 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
718 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
719 tc
->setMiscReg(MISCREG_EFER
, efer
);
721 // Set up the registers that describe the operating mode.
723 cr0
.pg
= 1; // Turn on paging.
724 cr0
.cd
= 0; // Don't disable caching.
725 cr0
.nw
= 0; // This is bit is defined to be ignored.
726 cr0
.am
= 0; // No alignment checking
727 cr0
.wp
= 0; // Supervisor mode can write read only pages
729 cr0
.et
= 1; // This should always be 1
730 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
731 // would be pointless.
732 cr0
.em
= 0; // Allow x87 instructions to execute natively.
733 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
734 // setting it to one.
735 cr0
.pe
= 1; // We're definitely in protected mode.
736 tc
->setMiscReg(MISCREG_CR0
, cr0
);
738 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
742 template<class IntType
>
744 X86Process::argsInit(int pageSize
,
745 std::vector
<AuxVector
<IntType
> > extraAuxvs
)
747 int intSize
= sizeof(IntType
);
749 typedef AuxVector
<IntType
> auxv_t
;
750 std::vector
<auxv_t
> auxv
= extraAuxvs
;
758 // We want 16 byte alignment
761 // Patch the ld_bias for dynamic executables.
764 // load object file into target memory
765 objFile
->loadSections(initVirtMem
);
768 X86_OnboardFPU
= 1 << 0,
769 X86_VirtualModeExtensions
= 1 << 1,
770 X86_DebuggingExtensions
= 1 << 2,
771 X86_PageSizeExtensions
= 1 << 3,
773 X86_TimeStampCounter
= 1 << 4,
774 X86_ModelSpecificRegisters
= 1 << 5,
775 X86_PhysicalAddressExtensions
= 1 << 6,
776 X86_MachineCheckExtensions
= 1 << 7,
778 X86_CMPXCHG8Instruction
= 1 << 8,
779 X86_OnboardAPIC
= 1 << 9,
780 X86_SYSENTER_SYSEXIT
= 1 << 11,
782 X86_MemoryTypeRangeRegisters
= 1 << 12,
783 X86_PageGlobalEnable
= 1 << 13,
784 X86_MachineCheckArchitecture
= 1 << 14,
785 X86_CMOVInstruction
= 1 << 15,
787 X86_PageAttributeTable
= 1 << 16,
788 X86_36BitPSEs
= 1 << 17,
789 X86_ProcessorSerialNumber
= 1 << 18,
790 X86_CLFLUSHInstruction
= 1 << 19,
792 X86_DebugTraceStore
= 1 << 21,
793 X86_ACPIViaMSR
= 1 << 22,
794 X86_MultimediaExtensions
= 1 << 23,
796 X86_FXSAVE_FXRSTOR
= 1 << 24,
797 X86_StreamingSIMDExtensions
= 1 << 25,
798 X86_StreamingSIMDExtensions2
= 1 << 26,
799 X86_CPUSelfSnoop
= 1 << 27,
801 X86_HyperThreading
= 1 << 28,
802 X86_AutomaticClockControl
= 1 << 29,
803 X86_IA64Processor
= 1 << 30
806 // Setup the auxiliary vectors. These will already have endian
807 // conversion. Auxiliary vectors are loaded only for elf formatted
808 // executables; the auxv is responsible for passing information from
809 // the OS to the interpreter.
810 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
814 X86_VirtualModeExtensions
|
815 X86_DebuggingExtensions
|
816 X86_PageSizeExtensions
|
817 X86_TimeStampCounter
|
818 X86_ModelSpecificRegisters
|
819 X86_PhysicalAddressExtensions
|
820 X86_MachineCheckExtensions
|
821 X86_CMPXCHG8Instruction
|
823 X86_SYSENTER_SYSEXIT
|
824 X86_MemoryTypeRangeRegisters
|
825 X86_PageGlobalEnable
|
826 X86_MachineCheckArchitecture
|
827 X86_CMOVInstruction
|
828 X86_PageAttributeTable
|
830 // X86_ProcessorSerialNumber |
831 X86_CLFLUSHInstruction
|
832 // X86_DebugTraceStore |
834 X86_MultimediaExtensions
|
836 X86_StreamingSIMDExtensions
|
837 X86_StreamingSIMDExtensions2
|
838 // X86_CPUSelfSnoop |
839 // X86_HyperThreading |
840 // X86_AutomaticClockControl |
841 // X86_IA64Processor |
844 // Bits which describe the system hardware capabilities
845 // XXX Figure out what these should be
846 auxv
.push_back(auxv_t(M5_AT_HWCAP
, features
));
847 // The system page size
848 auxv
.push_back(auxv_t(M5_AT_PAGESZ
, X86ISA::PageBytes
));
849 // Frequency at which times() increments
850 // Defined to be 100 in the kernel source.
851 auxv
.push_back(auxv_t(M5_AT_CLKTCK
, 100));
852 // This is the virtual address of the program header tables if they
853 // appear in the executable image.
854 auxv
.push_back(auxv_t(M5_AT_PHDR
, elfObject
->programHeaderTable()));
855 // This is the size of a program header entry from the elf file.
856 auxv
.push_back(auxv_t(M5_AT_PHENT
, elfObject
->programHeaderSize()));
857 // This is the number of program headers from the original elf file.
858 auxv
.push_back(auxv_t(M5_AT_PHNUM
, elfObject
->programHeaderCount()));
859 // This is the base address of the ELF interpreter; it should be
860 // zero for static executables or contain the base address for
861 // dynamic executables.
862 auxv
.push_back(auxv_t(M5_AT_BASE
, getBias()));
863 // XXX Figure out what this should be.
864 auxv
.push_back(auxv_t(M5_AT_FLAGS
, 0));
865 // The entry point to the program
866 auxv
.push_back(auxv_t(M5_AT_ENTRY
, objFile
->entryPoint()));
867 // Different user and group IDs
868 auxv
.push_back(auxv_t(M5_AT_UID
, uid()));
869 auxv
.push_back(auxv_t(M5_AT_EUID
, euid()));
870 auxv
.push_back(auxv_t(M5_AT_GID
, gid()));
871 auxv
.push_back(auxv_t(M5_AT_EGID
, egid()));
872 // Whether to enable "secure mode" in the executable
873 auxv
.push_back(auxv_t(M5_AT_SECURE
, 0));
874 // The address of 16 "random" bytes.
875 auxv
.push_back(auxv_t(M5_AT_RANDOM
, 0));
876 // The name of the program
877 auxv
.push_back(auxv_t(M5_AT_EXECFN
, 0));
878 // The platform string
879 auxv
.push_back(auxv_t(M5_AT_PLATFORM
, 0));
882 // Figure out how big the initial stack needs to be
884 // A sentry NULL void pointer at the top of the stack.
885 int sentry_size
= intSize
;
887 // This is the name of the file which is present on the initial stack
888 // It's purpose is to let the user space linker examine the original file.
889 int file_name_size
= filename
.size() + 1;
891 const int numRandomBytes
= 16;
892 int aux_data_size
= numRandomBytes
;
894 string platform
= "x86_64";
895 aux_data_size
+= platform
.size() + 1;
897 int env_data_size
= 0;
898 for (int i
= 0; i
< envp
.size(); ++i
)
899 env_data_size
+= envp
[i
].size() + 1;
900 int arg_data_size
= 0;
901 for (int i
= 0; i
< argv
.size(); ++i
)
902 arg_data_size
+= argv
[i
].size() + 1;
904 // The info_block needs to be padded so its size is a multiple of the
905 // alignment mask. Also, it appears that there needs to be at least some
906 // padding, so if the size is already a multiple, we need to increase it
908 int base_info_block_size
=
909 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
911 int info_block_size
= roundUp(base_info_block_size
, align
);
913 int info_block_padding
= info_block_size
- base_info_block_size
;
915 // Each auxiliary vector is two 8 byte words
916 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
918 int envp_array_size
= intSize
* (envp
.size() + 1);
919 int argv_array_size
= intSize
* (argv
.size() + 1);
921 int argc_size
= intSize
;
923 // Figure out the size of the contents of the actual initial frame
930 // There needs to be padding after the auxiliary vector data so that the
931 // very bottom of the stack is aligned properly.
932 int partial_size
= frame_size
+ aux_data_size
;
933 int aligned_partial_size
= roundUp(partial_size
, align
);
934 int aux_padding
= aligned_partial_size
- partial_size
;
942 Addr stack_base
= memState
->getStackBase();
944 Addr stack_min
= stack_base
- space_needed
;
945 stack_min
= roundDown(stack_min
, align
);
947 unsigned stack_size
= stack_base
- stack_min
;
948 stack_size
= roundUp(stack_size
, pageSize
);
949 memState
->setStackSize(stack_size
);
952 Addr stack_end
= roundDown(stack_base
- stack_size
, pageSize
);
954 DPRINTF(Stack
, "Mapping the stack: 0x%x %dB\n", stack_end
, stack_size
);
955 allocateMem(stack_end
, stack_size
);
957 // map out initial stack contents
958 IntType sentry_base
= stack_base
- sentry_size
;
959 IntType file_name_base
= sentry_base
- file_name_size
;
960 IntType env_data_base
= file_name_base
- env_data_size
;
961 IntType arg_data_base
= env_data_base
- arg_data_size
;
962 IntType aux_data_base
= arg_data_base
- info_block_padding
- aux_data_size
;
963 IntType auxv_array_base
= aux_data_base
- aux_array_size
- aux_padding
;
964 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
965 IntType argv_array_base
= envp_array_base
- argv_array_size
;
966 IntType argc_base
= argv_array_base
- argc_size
;
968 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
969 DPRINTF(Stack
, "0x%x - file name\n", file_name_base
);
970 DPRINTF(Stack
, "0x%x - env data\n", env_data_base
);
971 DPRINTF(Stack
, "0x%x - arg data\n", arg_data_base
);
972 DPRINTF(Stack
, "0x%x - aux data\n", aux_data_base
);
973 DPRINTF(Stack
, "0x%x - auxv array\n", auxv_array_base
);
974 DPRINTF(Stack
, "0x%x - envp array\n", envp_array_base
);
975 DPRINTF(Stack
, "0x%x - argv array\n", argv_array_base
);
976 DPRINTF(Stack
, "0x%x - argc \n", argc_base
);
977 DPRINTF(Stack
, "0x%x - stack min\n", stack_min
);
979 // write contents to stack
982 IntType argc
= argv
.size();
983 IntType guestArgc
= X86ISA::htog(argc
);
985 // Write out the sentry void *
986 IntType sentry_NULL
= 0;
987 initVirtMem
.writeBlob(sentry_base
, (uint8_t*)&sentry_NULL
, sentry_size
);
989 // Write the file name
990 initVirtMem
.writeString(file_name_base
, filename
.c_str());
992 // Fix up the aux vectors which point to data
993 assert(auxv
[auxv
.size() - 3].a_type
== M5_AT_RANDOM
);
994 auxv
[auxv
.size() - 3].a_val
= aux_data_base
;
995 assert(auxv
[auxv
.size() - 2].a_type
== M5_AT_EXECFN
);
996 auxv
[auxv
.size() - 2].a_val
= argv_array_base
;
997 assert(auxv
[auxv
.size() - 1].a_type
== M5_AT_PLATFORM
);
998 auxv
[auxv
.size() - 1].a_val
= aux_data_base
+ numRandomBytes
;
1001 // Copy the aux stuff
1002 for (int x
= 0; x
< auxv
.size(); x
++) {
1003 initVirtMem
.writeBlob(auxv_array_base
+ x
* 2 * intSize
,
1004 (uint8_t*)&(auxv
[x
].a_type
), intSize
);
1005 initVirtMem
.writeBlob(auxv_array_base
+ (x
* 2 + 1) * intSize
,
1006 (uint8_t*)&(auxv
[x
].a_val
), intSize
);
1008 // Write out the terminating zeroed auxiliary vector
1009 const uint64_t zero
= 0;
1010 initVirtMem
.writeBlob(auxv_array_base
+ auxv
.size() * 2 * intSize
,
1011 (uint8_t*)&zero
, intSize
);
1012 initVirtMem
.writeBlob(auxv_array_base
+ (auxv
.size() * 2 + 1) * intSize
,
1013 (uint8_t*)&zero
, intSize
);
1015 initVirtMem
.writeString(aux_data_base
, platform
.c_str());
1017 copyStringArray(envp
, envp_array_base
, env_data_base
, initVirtMem
);
1018 copyStringArray(argv
, argv_array_base
, arg_data_base
, initVirtMem
);
1020 initVirtMem
.writeBlob(argc_base
, (uint8_t*)&guestArgc
, intSize
);
1022 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
1023 // Set the stack pointer register
1024 tc
->setIntReg(StackPointerReg
, stack_min
);
1026 // There doesn't need to be any segment base added in since we're dealing
1027 // with the flat segmentation model.
1028 tc
->pcState(getStartPC());
1030 // Align the "stack_min" to a page boundary.
1031 memState
->setStackMin(roundDown(stack_min
, pageSize
));
1035 X86_64Process::argsInit(int pageSize
)
1037 std::vector
<AuxVector
<uint64_t> > extraAuxvs
;
1038 extraAuxvs
.push_back(AuxVector
<uint64_t>(M5_AT_SYSINFO_EHDR
,
1039 vsyscallPage
.base
));
1040 X86Process::argsInit
<uint64_t>(pageSize
, extraAuxvs
);
1044 I386Process::argsInit(int pageSize
)
1046 std::vector
<AuxVector
<uint32_t> > extraAuxvs
;
1047 //Tell the binary where the vsyscall part of the vsyscall page is.
1048 extraAuxvs
.push_back(AuxVector
<uint32_t>(M5_AT_SYSINFO
,
1049 vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
));
1050 extraAuxvs
.push_back(AuxVector
<uint32_t>(M5_AT_SYSINFO_EHDR
,
1051 vsyscallPage
.base
));
1052 X86Process::argsInit
<uint32_t>(pageSize
, extraAuxvs
);
1056 X86Process::setSyscallReturn(ThreadContext
*tc
, SyscallReturn retval
)
1058 tc
->setIntReg(INTREG_RAX
, retval
.encodedValue());
1062 X86_64Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1064 assert(i
< NumArgumentRegs
);
1065 return tc
->readIntReg(ArgumentReg
[i
++]);
1069 X86_64Process::setSyscallArg(ThreadContext
*tc
, int i
, X86ISA::IntReg val
)
1071 assert(i
< NumArgumentRegs
);
1072 return tc
->setIntReg(ArgumentReg
[i
], val
);
1076 X86_64Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1077 Process
*p
, TheISA::IntReg flags
)
1079 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1080 ((X86_64Process
*)p
)->vsyscallPage
= vsyscallPage
;
1084 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1086 assert(i
< NumArgumentRegs32
);
1087 return tc
->readIntReg(ArgumentReg32
[i
++]);
1091 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
, int width
)
1093 assert(width
== 32 || width
== 64);
1094 assert(i
< NumArgumentRegs
);
1095 uint64_t retVal
= tc
->readIntReg(ArgumentReg32
[i
++]) & mask(32);
1097 retVal
|= ((uint64_t)tc
->readIntReg(ArgumentReg
[i
++]) << 32);
1102 I386Process::setSyscallArg(ThreadContext
*tc
, int i
, X86ISA::IntReg val
)
1104 assert(i
< NumArgumentRegs
);
1105 return tc
->setIntReg(ArgumentReg
[i
], val
);
1109 I386Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1110 Process
*p
, TheISA::IntReg flags
)
1112 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1113 ((I386Process
*)p
)->vsyscallPage
= vsyscallPage
;