src/cpu/o3/alpha_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "cpu/o3/alpha_dyn_inst.hh"
  30
  31 template <class Impl>
  32 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
  33                                  InstSeqNum seq_num, FullCPU *cpu)
  34     : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
  35 {
  36     // Make sure to have the renamed register entries set to the same
  37     // as the normal register entries.  It will allow the IQ to work
  38     // without any modifications.
  39     for (int i = 0; i < this->staticInst->numDestRegs(); i++)
  40     {
  41         _destRegIdx[i] = this->staticInst->destRegIdx(i);
  42     }
  43
  44     for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
  45     {
  46         _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
  47         this->_readySrcRegIdx[i] = 0;
  48     }
  49
  50 }
  51
  52 template <class Impl>
  53 AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
  54     : BaseDynInst<Impl>(_staticInst)
  55 {
  56     // Make sure to have the renamed register entries set to the same
  57     // as the normal register entries.  It will allow the IQ to work
  58     // without any modifications.
  59     for (int i = 0; i < _staticInst->numDestRegs(); i++)
  60     {
  61         _destRegIdx[i] = _staticInst->destRegIdx(i);
  62     }
  63
  64     for (int i = 0; i < _staticInst->numSrcRegs(); i++)
  65     {
  66         _srcRegIdx[i] = _staticInst->srcRegIdx(i);
  67     }
  68 }
  69
  70 #if FULL_SYSTEM
  71 template <class Impl>
  72 Fault
  73 AlphaDynInst<Impl>::hwrei()
  74 {
  75     return this->cpu->hwrei();
  76 }
  77
  78 template <class Impl>
  79 int
  80 AlphaDynInst<Impl>::readIntrFlag()
  81 {
  82 return this->cpu->readIntrFlag();
  83 }
  84
  85 template <class Impl>
  86 void
  87 AlphaDynInst<Impl>::setIntrFlag(int val)
  88 {
  89     this->cpu->setIntrFlag(val);
  90 }
  91
  92 template <class Impl>
  93 bool
  94 AlphaDynInst<Impl>::inPalMode()
  95 {
  96     return this->cpu->inPalMode();
  97 }
  98
  99 template <class Impl>
 100 void
 101 AlphaDynInst<Impl>::trap(Fault fault)
 102 {
 103     this->cpu->trap(fault);
 104 }
 105
 106 template <class Impl>
 107 bool
 108 AlphaDynInst<Impl>::simPalCheck(int palFunc)
 109 {
 110     return this->cpu->simPalCheck(palFunc);
 111 }
 112 #else
 113 template <class Impl>
 114 void
 115 AlphaDynInst<Impl>::syscall()
 116 {
 117     this->cpu->syscall(this->threadNumber);
 118 }
 119 #endif
 120