src/dev/arm/pl111.hh

   1 /*
   2  * Copyright (c) 2010-2012, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: William Wang
  38  *          Ali Saidi
  39  */
  40
  41
  42 /** @file
  43  * Implementiation of a PL111 CLCD controller
  44  */
  45
  46 #ifndef __DEV_ARM_PL111_HH__
  47 #define __DEV_ARM_PL111_HH__
  48
  49 #include <fstream>
  50 #include <memory>
  51
  52 #include "base/bitmap.hh"
  53 #include "base/framebuffer.hh"
  54 #include "dev/arm/amba_device.hh"
  55 #include "params/Pl111.hh"
  56 #include "sim/serialize.hh"
  57
  58 class VncInput;
  59
  60 class Pl111: public AmbaDmaDevice
  61 {
  62   protected:
  63     static const uint64_t AMBA_ID       = ULL(0xb105f00d00141111);
  64     /** ARM PL111 register map*/
  65     static const int LcdTiming0       = 0x000;
  66     static const int LcdTiming1       = 0x004;
  67     static const int LcdTiming2       = 0x008;
  68     static const int LcdTiming3       = 0x00C;
  69     static const int LcdUpBase        = 0x010;
  70     static const int LcdLpBase        = 0x014;
  71     static const int LcdControl       = 0x018;
  72     static const int LcdImsc          = 0x01C;
  73     static const int LcdRis           = 0x020;
  74     static const int LcdMis           = 0x024;
  75     static const int LcdIcr           = 0x028;
  76     static const int LcdUpCurr        = 0x02C;
  77     static const int LcdLpCurr        = 0x030;
  78     static const int LcdPalette       = 0x200;
  79     static const int CrsrImage        = 0x800;
  80     static const int ClcdCrsrCtrl     = 0xC00;
  81     static const int ClcdCrsrConfig   = 0xC04;
  82     static const int ClcdCrsrPalette0 = 0xC08;
  83     static const int ClcdCrsrPalette1 = 0xC0C;
  84     static const int ClcdCrsrXY       = 0xC10;
  85     static const int ClcdCrsrClip     = 0xC14;
  86     static const int ClcdCrsrImsc     = 0xC20;
  87     static const int ClcdCrsrIcr      = 0xC24;
  88     static const int ClcdCrsrRis      = 0xC28;
  89     static const int ClcdCrsrMis      = 0xC2C;
  90
  91     static const int LcdPaletteSize   = 128;
  92     static const int CrsrImageSize    = 256;
  93
  94     static const int LcdMaxWidth      = 1024; // pixels per line
  95     static const int LcdMaxHeight     = 768;  // lines per panel
  96
  97     static const int dmaSize            = 8;    // 64 bits
  98     static const int maxOutstandingDma  = 16;   // 16 deep FIFO of 64 bits
  99
 100     static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
 101
 102     enum LcdMode {
 103         bpp1 = 0,
 104         bpp2,
 105         bpp4,
 106         bpp8,
 107         bpp16,
 108         bpp24,
 109         bpp16m565,
 110         bpp12
 111     };
 112
 113     BitUnion8(InterruptReg)
 114         Bitfield<1> underflow;
 115         Bitfield<2> baseaddr;
 116         Bitfield<3> vcomp;
 117         Bitfield<4> ahbmaster;
 118     EndBitUnion(InterruptReg)
 119
 120     BitUnion32(TimingReg0)
 121         Bitfield<7,2> ppl;
 122         Bitfield<15,8> hsw;
 123         Bitfield<23,16> hfp;
 124         Bitfield<31,24> hbp;
 125     EndBitUnion(TimingReg0)
 126
 127     BitUnion32(TimingReg1)
 128         Bitfield<9,0> lpp;
 129         Bitfield<15,10> vsw;
 130         Bitfield<23,16> vfp;
 131         Bitfield<31,24> vbp;
 132     EndBitUnion(TimingReg1)
 133
 134     BitUnion32(TimingReg2)
 135         Bitfield<4,0> pcdlo;
 136         Bitfield<5> clksel;
 137         Bitfield<10,6> acb;
 138         Bitfield<11> avs;
 139         Bitfield<12> ihs;
 140         Bitfield<13> ipc;
 141         Bitfield<14> ioe;
 142         Bitfield<25,16> cpl;
 143         Bitfield<26> bcd;
 144         Bitfield<31,27> pcdhi;
 145     EndBitUnion(TimingReg2)
 146
 147     BitUnion32(TimingReg3)
 148         Bitfield<6,0> led;
 149         Bitfield<16> lee;
 150     EndBitUnion(TimingReg3)
 151
 152     BitUnion32(ControlReg)
 153         Bitfield<0> lcden;
 154         Bitfield<3,1> lcdbpp;
 155         Bitfield<4> lcdbw;
 156         Bitfield<5> lcdtft;
 157         Bitfield<6> lcdmono8;
 158         Bitfield<7> lcddual;
 159         Bitfield<8> bgr;
 160         Bitfield<9> bebo;
 161         Bitfield<10> bepo;
 162         Bitfield<11> lcdpwr;
 163         Bitfield<13,12> lcdvcomp;
 164         Bitfield<16> watermark;
 165     EndBitUnion(ControlReg)
 166
 167     /**
 168      * Event wrapper for dmaDone()
 169      *
 170      * This event calls pushes its this pointer onto the freeDoneEvent
 171      * vector and calls dmaDone() when triggered.
 172      */
 173     class DmaDoneEvent : public Event
 174     {
 175       private:
 176         Pl111 &obj;
 177
 178       public:
 179         DmaDoneEvent(Pl111 *_obj)
 180             : Event(), obj(*_obj) {}
 181
 182         void process() {
 183             obj.dmaDoneEventFree.push_back(this);
 184             obj.dmaDone();
 185         }
 186
 187         const std::string name() const {
 188             return obj.name() + ".DmaDoneEvent";
 189         }
 190     };
 191
 192     /** Horizontal axis panel control register */
 193     TimingReg0 lcdTiming0;
 194
 195     /** Vertical axis panel control register */
 196     TimingReg1 lcdTiming1;
 197
 198     /** Clock and signal polarity control register */
 199     TimingReg2 lcdTiming2;
 200
 201     /** Line end control register */
 202     TimingReg3 lcdTiming3;
 203
 204     /** Upper panel frame base address register */
 205     uint32_t lcdUpbase;
 206
 207     /** Lower panel frame base address register */
 208     uint32_t lcdLpbase;
 209
 210     /** Control register */
 211     ControlReg lcdControl;
 212
 213     /** Interrupt mask set/clear register */
 214     InterruptReg lcdImsc;
 215
 216     /** Raw interrupt status register - const */
 217     InterruptReg lcdRis;
 218
 219     /** Masked interrupt status register */
 220     InterruptReg lcdMis;
 221
 222     /** 256x16-bit color palette registers
 223      * 256 palette entries organized as 128 locations of two entries per word */
 224     uint32_t lcdPalette[LcdPaletteSize];
 225
 226     /** Cursor image RAM register
 227      * 256-word wide values defining images overlaid by the hw cursor mechanism */
 228     uint32_t cursorImage[CrsrImageSize];
 229
 230     /** Cursor control register */
 231     uint32_t clcdCrsrCtrl;
 232
 233     /** Cursor configuration register */
 234     uint32_t clcdCrsrConfig;
 235
 236     /** Cursor palette registers */
 237     uint32_t clcdCrsrPalette0;
 238     uint32_t clcdCrsrPalette1;
 239
 240     /** Cursor XY position register */
 241     uint32_t clcdCrsrXY;
 242
 243     /** Cursor clip position register */
 244     uint32_t clcdCrsrClip;
 245
 246     /** Cursor interrupt mask set/clear register */
 247     InterruptReg clcdCrsrImsc;
 248
 249     /** Cursor interrupt clear register */
 250     InterruptReg clcdCrsrIcr;
 251
 252     /** Cursor raw interrupt status register - const */
 253     InterruptReg clcdCrsrRis;
 254
 255     /** Cursor masked interrupt status register - const */
 256     InterruptReg clcdCrsrMis;
 257
 258     /** Pixel clock */
 259     Tick pixelClock;
 260
 261     PixelConverter converter;
 262     FrameBuffer fb;
 263
 264     /** VNC server */
 265     VncInput *vnc;
 266
 267     /** Helper to write out bitmaps */
 268     Bitmap bmp;
 269
 270     /** Picture of what the current frame buffer looks like */
 271     std::ostream *pic;
 272
 273     /** Frame buffer width - pixels per line */
 274     uint16_t width;
 275
 276     /** Frame buffer height - lines per panel */
 277     uint16_t height;
 278
 279     /** Bytes per pixel */
 280     uint8_t bytesPerPixel;
 281
 282     /** CLCDC supports up to 1024x768 */
 283     uint8_t *dmaBuffer;
 284
 285     /** Start time for frame buffer dma read */
 286     Tick startTime;
 287
 288     /** Frame buffer base address */
 289     Addr startAddr;
 290
 291     /** Frame buffer max address */
 292     Addr maxAddr;
 293
 294     /** Frame buffer current address */
 295     Addr curAddr;
 296
 297     /** DMA FIFO watermark */
 298     uint32_t waterMark;
 299
 300     /** Number of pending dma reads */
 301     uint32_t dmaPendingNum;
 302
 303     PixelConverter pixelConverter() const;
 304
 305     /** Send updated parameters to the vnc server */
 306     void updateVideoParams();
 307
 308     /** DMA framebuffer read */
 309     void readFramebuffer();
 310
 311     /** Generate dma framebuffer read event */
 312     void generateReadEvent();
 313
 314     /** Function to generate interrupt */
 315     void generateInterrupt();
 316
 317     /** fillFIFO event */
 318     void fillFifo();
 319
 320     /** start the dmas off after power is enabled */
 321     void startDma();
 322
 323     /** DMA done event */
 324     void dmaDone();
 325
 326     /** DMA framebuffer read event */
 327     EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
 328
 329     /** Fill fifo */
 330     EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
 331
 332     /**@{*/
 333     /**
 334      * All pre-allocated DMA done events
 335      *
 336      * The PL111 model preallocates maxOutstandingDma number of
 337      * DmaDoneEvents to avoid having to heap allocate every single
 338      * event when it is needed. In order to keep track of which events
 339      * are in flight and which are ready to be used, we use two
 340      * different vectors. dmaDoneEventAll contains <i>all</i>
 341      * DmaDoneEvents that the object may use, while dmaDoneEventFree
 342      * contains a list of currently <i>unused</i> events. When an
 343      * event needs to be scheduled, the last element of the
 344      * dmaDoneEventFree is used and removed from the list. When an
 345      * event fires, it is added to the end of the
 346      * dmaEventFreeList. dmaDoneEventAll is never used except for in
 347      * initialization and serialization.
 348      */
 349     std::vector<DmaDoneEvent> dmaDoneEventAll;
 350
 351     /** Unused DMA done events that are ready to be scheduled */
 352     std::vector<DmaDoneEvent *> dmaDoneEventFree;
 353     /**@}*/
 354
 355     /** Wrapper to create an event out of the interrupt */
 356     EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
 357
 358     bool enableCapture;
 359
 360   public:
 361     typedef Pl111Params Params;
 362
 363     const Params *
 364     params() const
 365     {
 366         return dynamic_cast<const Params *>(_params);
 367     }
 368     Pl111(const Params *p);
 369     ~Pl111();
 370
 371     virtual Tick read(PacketPtr pkt);
 372     virtual Tick write(PacketPtr pkt);
 373
 374     virtual void serialize(std::ostream &os);
 375     virtual void unserialize(Checkpoint *cp, const std::string &section);
 376
 377     /**
 378      * Determine the address ranges that this device responds to.
 379      *
 380      * @return a list of non-overlapping address ranges
 381      */
 382     AddrRangeList getAddrRanges() const;
 383 };
 384
 385 #endif