2 * Copyright (c) 2010-2012 ARM Limited
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: William Wang
43 * Implementiation of a PL111 CLCD controller
46 #ifndef __DEV_ARM_PL111_HH__
47 #define __DEV_ARM_PL111_HH__
51 #include "dev/arm/amba_device.hh"
52 #include "params/Pl111.hh"
53 #include "sim/serialize.hh"
58 class Pl111: public AmbaDmaDevice
61 static const uint64_t AMBA_ID = ULL(0xb105f00d00141111);
62 /** ARM PL111 register map*/
63 static const int LcdTiming0 = 0x000;
64 static const int LcdTiming1 = 0x004;
65 static const int LcdTiming2 = 0x008;
66 static const int LcdTiming3 = 0x00C;
67 static const int LcdUpBase = 0x010;
68 static const int LcdLpBase = 0x014;
69 static const int LcdControl = 0x018;
70 static const int LcdImsc = 0x01C;
71 static const int LcdRis = 0x020;
72 static const int LcdMis = 0x024;
73 static const int LcdIcr = 0x028;
74 static const int LcdUpCurr = 0x02C;
75 static const int LcdLpCurr = 0x030;
76 static const int LcdPalette = 0x200;
77 static const int CrsrImage = 0x800;
78 static const int ClcdCrsrCtrl = 0xC00;
79 static const int ClcdCrsrConfig = 0xC04;
80 static const int ClcdCrsrPalette0 = 0xC08;
81 static const int ClcdCrsrPalette1 = 0xC0C;
82 static const int ClcdCrsrXY = 0xC10;
83 static const int ClcdCrsrClip = 0xC14;
84 static const int ClcdCrsrImsc = 0xC20;
85 static const int ClcdCrsrIcr = 0xC24;
86 static const int ClcdCrsrRis = 0xC28;
87 static const int ClcdCrsrMis = 0xC2C;
89 static const int LcdPaletteSize = 128;
90 static const int CrsrImageSize = 256;
92 static const int LcdMaxWidth = 1024; // pixels per line
93 static const int LcdMaxHeight = 768; // lines per panel
95 static const int dmaSize = 8; // 64 bits
96 static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits
98 static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
111 BitUnion8(InterruptReg)
112 Bitfield<1> underflow;
113 Bitfield<2> baseaddr;
115 Bitfield<4> ahbmaster;
116 EndBitUnion(InterruptReg)
118 BitUnion32(TimingReg0)
123 EndBitUnion(TimingReg0)
125 BitUnion32(TimingReg1)
130 EndBitUnion(TimingReg1)
132 BitUnion32(TimingReg2)
142 Bitfield<31,27> pcdhi;
143 EndBitUnion(TimingReg2)
145 BitUnion32(TimingReg3)
148 EndBitUnion(TimingReg3)
150 BitUnion32(ControlReg)
152 Bitfield<3,1> lcdbpp;
155 Bitfield<6> lcdmono8;
161 Bitfield<13,12> lcdvcomp;
162 Bitfield<16> watermark;
163 EndBitUnion(ControlReg)
166 * Event wrapper for dmaDone()
168 * This event calls pushes its this pointer onto the freeDoneEvent
169 * vector and calls dmaDone() when triggered.
171 class DmaDoneEvent : public Event
177 DmaDoneEvent(Pl111 *_obj)
178 : Event(), obj(*_obj) {}
181 obj.dmaDoneEventFree.push_back(this);
185 const std::string name() const {
186 return obj.name() + ".DmaDoneEvent";
190 /** Horizontal axis panel control register */
191 TimingReg0 lcdTiming0;
193 /** Vertical axis panel control register */
194 TimingReg1 lcdTiming1;
196 /** Clock and signal polarity control register */
197 TimingReg2 lcdTiming2;
199 /** Line end control register */
200 TimingReg3 lcdTiming3;
202 /** Upper panel frame base address register */
205 /** Lower panel frame base address register */
208 /** Control register */
209 ControlReg lcdControl;
211 /** Interrupt mask set/clear register */
212 InterruptReg lcdImsc;
214 /** Raw interrupt status register - const */
217 /** Masked interrupt status register */
220 /** 256x16-bit color palette registers
221 * 256 palette entries organized as 128 locations of two entries per word */
222 uint32_t lcdPalette[LcdPaletteSize];
224 /** Cursor image RAM register
225 * 256-word wide values defining images overlaid by the hw cursor mechanism */
226 uint32_t cursorImage[CrsrImageSize];
228 /** Cursor control register */
229 uint32_t clcdCrsrCtrl;
231 /** Cursor configuration register */
232 uint32_t clcdCrsrConfig;
234 /** Cursor palette registers */
235 uint32_t clcdCrsrPalette0;
236 uint32_t clcdCrsrPalette1;
238 /** Cursor XY position register */
241 /** Cursor clip position register */
242 uint32_t clcdCrsrClip;
244 /** Cursor interrupt mask set/clear register */
245 InterruptReg clcdCrsrImsc;
247 /** Cursor interrupt clear register */
248 InterruptReg clcdCrsrIcr;
250 /** Cursor raw interrupt status register - const */
251 InterruptReg clcdCrsrRis;
253 /** Cursor masked interrupt status register - const */
254 InterruptReg clcdCrsrMis;
262 /** Helper to write out bitmaps */
265 /** Picture of what the current frame buffer looks like */
268 /** Frame buffer width - pixels per line */
271 /** Frame buffer height - lines per panel */
274 /** Bytes per pixel */
275 uint8_t bytesPerPixel;
277 /** CLCDC supports up to 1024x768 */
280 /** Start time for frame buffer dma read */
283 /** Frame buffer base address */
286 /** Frame buffer max address */
289 /** Frame buffer current address */
292 /** DMA FIFO watermark */
295 /** Number of pending dma reads */
296 uint32_t dmaPendingNum;
298 /** Send updated parameters to the vnc server */
299 void updateVideoParams();
301 /** DMA framebuffer read */
302 void readFramebuffer();
304 /** Generate dma framebuffer read event */
305 void generateReadEvent();
307 /** Function to generate interrupt */
308 void generateInterrupt();
310 /** fillFIFO event */
313 /** start the dmas off after power is enabled */
316 /** DMA done event */
319 /** DMA framebuffer read event */
320 EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
323 EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
327 * All pre-allocated DMA done events
329 * The PL111 model preallocates maxOutstandingDma number of
330 * DmaDoneEvents to avoid having to heap allocate every single
331 * event when it is needed. In order to keep track of which events
332 * are in flight and which are ready to be used, we use two
333 * different vectors. dmaDoneEventAll contains <i>all</i>
334 * DmaDoneEvents that the object may use, while dmaDoneEventFree
335 * contains a list of currently <i>unused</i> events. When an
336 * event needs to be scheduled, the last element of the
337 * dmaDoneEventFree is used and removed from the list. When an
338 * event fires, it is added to the end of the
339 * dmaEventFreeList. dmaDoneEventAll is never used except for in
340 * initialization and serialization.
342 std::vector<DmaDoneEvent> dmaDoneEventAll;
344 /** Unused DMA done events that are ready to be scheduled */
345 std::vector<DmaDoneEvent *> dmaDoneEventFree;
348 /** Wrapper to create an event out of the interrupt */
349 EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
354 typedef Pl111Params Params;
359 return dynamic_cast<const Params *>(_params);
361 Pl111(const Params *p);
364 virtual Tick read(PacketPtr pkt);
365 virtual Tick write(PacketPtr pkt);
367 virtual void serialize(std::ostream &os);
368 virtual void unserialize(Checkpoint *cp, const std::string §ion);
371 * Determine the address ranges that this device responds to.
373 * @return a list of non-overlapping address ranges
375 AddrRangeList getAddrRanges() const;