src/mem/cache/base.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2015-2016 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Steve Reinhardt
  42  *          Ron Dreslinski
  43  */
  44
  45 /**
  46  * @file
  47  * Declares a basic cache interface BaseCache.
  48  */
  49
  50 #ifndef __MEM_CACHE_BASE_HH__
  51 #define __MEM_CACHE_BASE_HH__
  52
  53 #include <algorithm>
  54 #include <list>
  55 #include <string>
  56 #include <vector>
  57
  58 #include "base/misc.hh"
  59 #include "base/statistics.hh"
  60 #include "base/trace.hh"
  61 #include "base/types.hh"
  62 #include "debug/Cache.hh"
  63 #include "debug/CachePort.hh"
  64 #include "mem/cache/mshr_queue.hh"
  65 #include "mem/cache/write_queue.hh"
  66 #include "mem/mem_object.hh"
  67 #include "mem/packet.hh"
  68 #include "mem/qport.hh"
  69 #include "mem/request.hh"
  70 #include "params/BaseCache.hh"
  71 #include "sim/eventq.hh"
  72 #include "sim/full_system.hh"
  73 #include "sim/sim_exit.hh"
  74 #include "sim/system.hh"
  75
  76 /**
  77  * A basic cache interface. Implements some common functions for speed.
  78  */
  79 class BaseCache : public MemObject
  80 {
  81   protected:
  82     /**
  83      * Indexes to enumerate the MSHR queues.
  84      */
  85     enum MSHRQueueIndex {
  86         MSHRQueue_MSHRs,
  87         MSHRQueue_WriteBuffer
  88     };
  89
  90   public:
  91     /**
  92      * Reasons for caches to be blocked.
  93      */
  94     enum BlockedCause {
  95         Blocked_NoMSHRs = MSHRQueue_MSHRs,
  96         Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
  97         Blocked_NoTargets,
  98         NUM_BLOCKED_CAUSES
  99     };
 100
 101   protected:
 102
 103     /**
 104      * A cache master port is used for the memory-side port of the
 105      * cache, and in addition to the basic timing port that only sends
 106      * response packets through a transmit list, it also offers the
 107      * ability to schedule and send request packets (requests &
 108      * writebacks). The send event is scheduled through schedSendEvent,
 109      * and the sendDeferredPacket of the timing port is modified to
 110      * consider both the transmit list and the requests from the MSHR.
 111      */
 112     class CacheMasterPort : public QueuedMasterPort
 113     {
 114
 115       public:
 116
 117         /**
 118          * Schedule a send of a request packet (from the MSHR). Note
 119          * that we could already have a retry outstanding.
 120          */
 121         void schedSendEvent(Tick time)
 122         {
 123             DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
 124             reqQueue.schedSendEvent(time);
 125         }
 126
 127       protected:
 128
 129         CacheMasterPort(const std::string &_name, BaseCache *_cache,
 130                         ReqPacketQueue &_reqQueue,
 131                         SnoopRespPacketQueue &_snoopRespQueue) :
 132             QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
 133         { }
 134
 135         /**
 136          * Memory-side port always snoops.
 137          *
 138          * @return always true
 139          */
 140         virtual bool isSnooping() const { return true; }
 141     };
 142
 143     /**
 144      * A cache slave port is used for the CPU-side port of the cache,
 145      * and it is basically a simple timing port that uses a transmit
 146      * list for responses to the CPU (or connected master). In
 147      * addition, it has the functionality to block the port for
 148      * incoming requests. If blocked, the port will issue a retry once
 149      * unblocked.
 150      */
 151     class CacheSlavePort : public QueuedSlavePort
 152     {
 153
 154       public:
 155
 156         /** Do not accept any new requests. */
 157         void setBlocked();
 158
 159         /** Return to normal operation and accept new requests. */
 160         void clearBlocked();
 161
 162         bool isBlocked() const { return blocked; }
 163
 164       protected:
 165
 166         CacheSlavePort(const std::string &_name, BaseCache *_cache,
 167                        const std::string &_label);
 168
 169         /** A normal packet queue used to store responses. */
 170         RespPacketQueue queue;
 171
 172         bool blocked;
 173
 174         bool mustSendRetry;
 175
 176       private:
 177
 178         void processSendRetry();
 179
 180         EventFunctionWrapper sendRetryEvent;
 181
 182     };
 183
 184     CacheSlavePort *cpuSidePort;
 185     CacheMasterPort *memSidePort;
 186
 187   protected:
 188
 189     /** Miss status registers */
 190     MSHRQueue mshrQueue;
 191
 192     /** Write/writeback buffer */
 193     WriteQueue writeBuffer;
 194
 195     /**
 196      * Mark a request as in service (sent downstream in the memory
 197      * system), effectively making this MSHR the ordering point.
 198      */
 199     void markInService(MSHR *mshr, bool pending_modified_resp)
 200     {
 201         bool wasFull = mshrQueue.isFull();
 202         mshrQueue.markInService(mshr, pending_modified_resp);
 203
 204         if (wasFull && !mshrQueue.isFull()) {
 205             clearBlocked(Blocked_NoMSHRs);
 206         }
 207     }
 208
 209     void markInService(WriteQueueEntry *entry)
 210     {
 211         bool wasFull = writeBuffer.isFull();
 212         writeBuffer.markInService(entry);
 213
 214         if (wasFull && !writeBuffer.isFull()) {
 215             clearBlocked(Blocked_NoWBBuffers);
 216         }
 217     }
 218
 219     /**
 220      * Determine if we should allocate on a fill or not.
 221      *
 222      * @param cmd Packet command being added as an MSHR target
 223      *
 224      * @return Whether we should allocate on a fill or not
 225      */
 226     virtual bool allocOnFill(MemCmd cmd) const = 0;
 227
 228     /**
 229      * Write back dirty blocks in the cache using functional accesses.
 230      */
 231     virtual void memWriteback() override = 0;
 232     /**
 233      * Invalidates all blocks in the cache.
 234      *
 235      * @warn Dirty cache lines will not be written back to
 236      * memory. Make sure to call functionalWriteback() first if you
 237      * want the to write them to memory.
 238      */
 239     virtual void memInvalidate() override = 0;
 240     /**
 241      * Determine if there are any dirty blocks in the cache.
 242      *
 243      * \return true if at least one block is dirty, false otherwise.
 244      */
 245     virtual bool isDirty() const = 0;
 246
 247     /**
 248      * Determine if an address is in the ranges covered by this
 249      * cache. This is useful to filter snoops.
 250      *
 251      * @param addr Address to check against
 252      *
 253      * @return If the address in question is in range
 254      */
 255     bool inRange(Addr addr) const;
 256
 257     /** Block size of this cache */
 258     const unsigned blkSize;
 259
 260     /**
 261      * The latency of tag lookup of a cache. It occurs when there is
 262      * an access to the cache.
 263      */
 264     const Cycles lookupLatency;
 265
 266     /**
 267      * The latency of data access of a cache. It occurs when there is
 268      * an access to the cache.
 269      */
 270     const Cycles dataLatency;
 271
 272     /**
 273      * This is the forward latency of the cache. It occurs when there
 274      * is a cache miss and a request is forwarded downstream, in
 275      * particular an outbound miss.
 276      */
 277     const Cycles forwardLatency;
 278
 279     /** The latency to fill a cache block */
 280     const Cycles fillLatency;
 281
 282     /**
 283      * The latency of sending reponse to its upper level cache/core on
 284      * a linefill. The responseLatency parameter captures this
 285      * latency.
 286      */
 287     const Cycles responseLatency;
 288
 289     /** The number of targets for each MSHR. */
 290     const int numTarget;
 291
 292     /** Do we forward snoops from mem side port through to cpu side port? */
 293     bool forwardSnoops;
 294
 295     /**
 296      * Is this cache read only, for example the instruction cache, or
 297      * table-walker cache. A cache that is read only should never see
 298      * any writes, and should never get any dirty data (and hence
 299      * never have to do any writebacks).
 300      */
 301     const bool isReadOnly;
 302
 303     /**
 304      * Bit vector of the blocking reasons for the access path.
 305      * @sa #BlockedCause
 306      */
 307     uint8_t blocked;
 308
 309     /** Increasing order number assigned to each incoming request. */
 310     uint64_t order;
 311
 312     /** Stores time the cache blocked for statistics. */
 313     Cycles blockedCycle;
 314
 315     /** Pointer to the MSHR that has no targets. */
 316     MSHR *noTargetMSHR;
 317
 318     /** The number of misses to trigger an exit event. */
 319     Counter missCount;
 320
 321     /**
 322      * The address range to which the cache responds on the CPU side.
 323      * Normally this is all possible memory addresses. */
 324     const AddrRangeList addrRanges;
 325
 326   public:
 327     /** System we are currently operating in. */
 328     System *system;
 329
 330     // Statistics
 331     /**
 332      * @addtogroup CacheStatistics
 333      * @{
 334      */
 335
 336     /** Number of hits per thread for each type of command.
 337         @sa Packet::Command */
 338     Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
 339     /** Number of hits for demand accesses. */
 340     Stats::Formula demandHits;
 341     /** Number of hit for all accesses. */
 342     Stats::Formula overallHits;
 343
 344     /** Number of misses per thread for each type of command.
 345         @sa Packet::Command */
 346     Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
 347     /** Number of misses for demand accesses. */
 348     Stats::Formula demandMisses;
 349     /** Number of misses for all accesses. */
 350     Stats::Formula overallMisses;
 351
 352     /**
 353      * Total number of cycles per thread/command spent waiting for a miss.
 354      * Used to calculate the average miss latency.
 355      */
 356     Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
 357     /** Total number of cycles spent waiting for demand misses. */
 358     Stats::Formula demandMissLatency;
 359     /** Total number of cycles spent waiting for all misses. */
 360     Stats::Formula overallMissLatency;
 361
 362     /** The number of accesses per command and thread. */
 363     Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
 364     /** The number of demand accesses. */
 365     Stats::Formula demandAccesses;
 366     /** The number of overall accesses. */
 367     Stats::Formula overallAccesses;
 368
 369     /** The miss rate per command and thread. */
 370     Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
 371     /** The miss rate of all demand accesses. */
 372     Stats::Formula demandMissRate;
 373     /** The miss rate for all accesses. */
 374     Stats::Formula overallMissRate;
 375
 376     /** The average miss latency per command and thread. */
 377     Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
 378     /** The average miss latency for demand misses. */
 379     Stats::Formula demandAvgMissLatency;
 380     /** The average miss latency for all misses. */
 381     Stats::Formula overallAvgMissLatency;
 382
 383     /** The total number of cycles blocked for each blocked cause. */
 384     Stats::Vector blocked_cycles;
 385     /** The number of times this cache blocked for each blocked cause. */
 386     Stats::Vector blocked_causes;
 387
 388     /** The average number of cycles blocked for each blocked cause. */
 389     Stats::Formula avg_blocked;
 390
 391     /** The number of times a HW-prefetched block is evicted w/o reference. */
 392     Stats::Scalar unusedPrefetches;
 393
 394     /** Number of blocks written back per thread. */
 395     Stats::Vector writebacks;
 396
 397     /** Number of misses that hit in the MSHRs per command and thread. */
 398     Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
 399     /** Demand misses that hit in the MSHRs. */
 400     Stats::Formula demandMshrHits;
 401     /** Total number of misses that hit in the MSHRs. */
 402     Stats::Formula overallMshrHits;
 403
 404     /** Number of misses that miss in the MSHRs, per command and thread. */
 405     Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
 406     /** Demand misses that miss in the MSHRs. */
 407     Stats::Formula demandMshrMisses;
 408     /** Total number of misses that miss in the MSHRs. */
 409     Stats::Formula overallMshrMisses;
 410
 411     /** Number of misses that miss in the MSHRs, per command and thread. */
 412     Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
 413     /** Total number of misses that miss in the MSHRs. */
 414     Stats::Formula overallMshrUncacheable;
 415
 416     /** Total cycle latency of each MSHR miss, per command and thread. */
 417     Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
 418     /** Total cycle latency of demand MSHR misses. */
 419     Stats::Formula demandMshrMissLatency;
 420     /** Total cycle latency of overall MSHR misses. */
 421     Stats::Formula overallMshrMissLatency;
 422
 423     /** Total cycle latency of each MSHR miss, per command and thread. */
 424     Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
 425     /** Total cycle latency of overall MSHR misses. */
 426     Stats::Formula overallMshrUncacheableLatency;
 427
 428 #if 0
 429     /** The total number of MSHR accesses per command and thread. */
 430     Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
 431     /** The total number of demand MSHR accesses. */
 432     Stats::Formula demandMshrAccesses;
 433     /** The total number of MSHR accesses. */
 434     Stats::Formula overallMshrAccesses;
 435 #endif
 436
 437     /** The miss rate in the MSHRs pre command and thread. */
 438     Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
 439     /** The demand miss rate in the MSHRs. */
 440     Stats::Formula demandMshrMissRate;
 441     /** The overall miss rate in the MSHRs. */
 442     Stats::Formula overallMshrMissRate;
 443
 444     /** The average latency of an MSHR miss, per command and thread. */
 445     Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
 446     /** The average latency of a demand MSHR miss. */
 447     Stats::Formula demandAvgMshrMissLatency;
 448     /** The average overall latency of an MSHR miss. */
 449     Stats::Formula overallAvgMshrMissLatency;
 450
 451     /** The average latency of an MSHR miss, per command and thread. */
 452     Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
 453     /** The average overall latency of an MSHR miss. */
 454     Stats::Formula overallAvgMshrUncacheableLatency;
 455
 456     /**
 457      * @}
 458      */
 459
 460     /**
 461      * Register stats for this object.
 462      */
 463     virtual void regStats() override;
 464
 465   public:
 466     BaseCache(const BaseCacheParams *p, unsigned blk_size);
 467     ~BaseCache() {}
 468
 469     virtual void init() override;
 470
 471     virtual BaseMasterPort &getMasterPort(const std::string &if_name,
 472                                           PortID idx = InvalidPortID) override;
 473     virtual BaseSlavePort &getSlavePort(const std::string &if_name,
 474                                         PortID idx = InvalidPortID) override;
 475
 476     /**
 477      * Query block size of a cache.
 478      * @return  The block size
 479      */
 480     unsigned
 481     getBlockSize() const
 482     {
 483         return blkSize;
 484     }
 485
 486     const AddrRangeList &getAddrRanges() const { return addrRanges; }
 487
 488     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
 489     {
 490         MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
 491                                         pkt, time, order++,
 492                                         allocOnFill(pkt->cmd));
 493
 494         if (mshrQueue.isFull()) {
 495             setBlocked((BlockedCause)MSHRQueue_MSHRs);
 496         }
 497
 498         if (sched_send) {
 499             // schedule the send
 500             schedMemSideSendEvent(time);
 501         }
 502
 503         return mshr;
 504     }
 505
 506     void allocateWriteBuffer(PacketPtr pkt, Tick time)
 507     {
 508         // should only see writes or clean evicts here
 509         assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
 510
 511         Addr blk_addr = pkt->getBlockAddr(blkSize);
 512
 513         WriteQueueEntry *wq_entry =
 514             writeBuffer.findMatch(blk_addr, pkt->isSecure());
 515         if (wq_entry && !wq_entry->inService) {
 516             DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
 517         }
 518
 519         writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
 520
 521         if (writeBuffer.isFull()) {
 522             setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
 523         }
 524
 525         // schedule the send
 526         schedMemSideSendEvent(time);
 527     }
 528
 529     /**
 530      * Returns true if the cache is blocked for accesses.
 531      */
 532     bool isBlocked() const
 533     {
 534         return blocked != 0;
 535     }
 536
 537     /**
 538      * Marks the access path of the cache as blocked for the given cause. This
 539      * also sets the blocked flag in the slave interface.
 540      * @param cause The reason for the cache blocking.
 541      */
 542     void setBlocked(BlockedCause cause)
 543     {
 544         uint8_t flag = 1 << cause;
 545         if (blocked == 0) {
 546             blocked_causes[cause]++;
 547             blockedCycle = curCycle();
 548             cpuSidePort->setBlocked();
 549         }
 550         blocked |= flag;
 551         DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
 552     }
 553
 554     /**
 555      * Marks the cache as unblocked for the given cause. This also clears the
 556      * blocked flags in the appropriate interfaces.
 557      * @param cause The newly unblocked cause.
 558      * @warning Calling this function can cause a blocked request on the bus to
 559      * access the cache. The cache must be in a state to handle that request.
 560      */
 561     void clearBlocked(BlockedCause cause)
 562     {
 563         uint8_t flag = 1 << cause;
 564         blocked &= ~flag;
 565         DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
 566         if (blocked == 0) {
 567             blocked_cycles[cause] += curCycle() - blockedCycle;
 568             cpuSidePort->clearBlocked();
 569         }
 570     }
 571
 572     /**
 573      * Schedule a send event for the memory-side port. If already
 574      * scheduled, this may reschedule the event at an earlier
 575      * time. When the specified time is reached, the port is free to
 576      * send either a response, a request, or a prefetch request.
 577      *
 578      * @param time The time when to attempt sending a packet.
 579      */
 580     void schedMemSideSendEvent(Tick time)
 581     {
 582         memSidePort->schedSendEvent(time);
 583     }
 584
 585     virtual bool inCache(Addr addr, bool is_secure) const = 0;
 586
 587     virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
 588
 589     void incMissCount(PacketPtr pkt)
 590     {
 591         assert(pkt->req->masterId() < system->maxMasters());
 592         misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
 593         pkt->req->incAccessDepth();
 594         if (missCount) {
 595             --missCount;
 596             if (missCount == 0)
 597                 exitSimLoop("A cache reached the maximum miss count");
 598         }
 599     }
 600     void incHitCount(PacketPtr pkt)
 601     {
 602         assert(pkt->req->masterId() < system->maxMasters());
 603         hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
 604
 605     }
 606
 607 };
 608
 609 #endif //__MEM_CACHE_BASE_HH__