src/mem/ruby/system/Sequencer.hh

   1
   2 /*
   3  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
  32  *
  33  * Description:
  34  *
  35  */
  36
  37 #ifndef SEQUENCER_H
  38 #define SEQUENCER_H
  39
  40 #include "mem/ruby/common/Global.hh"
  41 #include "mem/ruby/common/Consumer.hh"
  42 #include "mem/protocol/CacheRequestType.hh"
  43 #include "mem/protocol/AccessModeType.hh"
  44 #include "mem/protocol/GenericMachineType.hh"
  45 #include "mem/protocol/PrefetchBit.hh"
  46 #include "mem/ruby/system/RubyPort.hh"
  47 #include "mem/gems_common/Map.hh"
  48 #include "mem/ruby/common/Address.hh"
  49
  50 class DataBlock;
  51 class CacheMsg;
  52 class MachineID;
  53 class CacheMemory;
  54 class AbstractController;
  55
  56 struct SequencerRequest {
  57   RubyRequest ruby_request;
  58   int64_t id;
  59   Time issue_time;
  60
  61   SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
  62     : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
  63   {}
  64 };
  65
  66 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
  67
  68 class Sequencer : public Consumer, public RubyPort {
  69 public:
  70   // Constructors
  71   Sequencer(const string & name);
  72   void init(const vector<string> & argv);
  73
  74   // Destructor
  75   ~Sequencer();
  76
  77   // Public Methods
  78   void wakeup(); // Used only for deadlock detection
  79
  80   void printConfig(ostream& out) const;
  81
  82   void printProgress(ostream& out) const;
  83
  84   void writeCallback(const Address& address, DataBlock& data);
  85   void readCallback(const Address& address, DataBlock& data);
  86
  87   // called by Tester or Simics
  88   int64_t makeRequest(const RubyRequest & request);
  89   int isReady(const RubyRequest& request);
  90   bool empty() const;
  91
  92   void print(ostream& out) const;
  93   void printStats(ostream & out) const;
  94   void checkCoherence(const Address& address);
  95
  96   //  bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
  97   //  bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
  98
  99   void removeRequest(SequencerRequest* request);
 100 private:
 101   // Private Methods
 102   bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
 103   void issueRequest(const RubyRequest& request);
 104
 105   void hitCallback(SequencerRequest* request, DataBlock& data);
 106   bool insertRequest(SequencerRequest* request);
 107
 108
 109   // Private copy constructor and assignment operator
 110   Sequencer(const Sequencer& obj);
 111   Sequencer& operator=(const Sequencer& obj);
 112
 113 private:
 114   int m_max_outstanding_requests;
 115   int m_deadlock_threshold;
 116
 117   AbstractController* m_controller;
 118   MessageBuffer* m_mandatory_q_ptr;
 119   CacheMemory* m_dataCache_ptr;
 120   CacheMemory* m_instCache_ptr;
 121
 122   // indicates what processor on the chip this sequencer is associated with
 123   int m_version;
 124   int m_controller_type;
 125
 126   Map<Address, SequencerRequest*> m_writeRequestTable;
 127   Map<Address, SequencerRequest*> m_readRequestTable;
 128   // Global outstanding request count, across all request tables
 129   int m_outstanding_count;
 130   bool m_deadlock_check_scheduled;
 131   int m_atomic_reads;
 132   int m_atomic_writes;
 133
 134   int m_store_waiting_on_load_cycles;
 135   int m_store_waiting_on_store_cycles;
 136   int m_load_waiting_on_store_cycles;
 137   int m_load_waiting_on_load_cycles;
 138 };
 139
 140 // Output operator declaration
 141 ostream& operator<<(ostream& out, const Sequencer& obj);
 142
 143 // ******************* Definitions *******************
 144
 145 // Output operator definition
 146 extern inline
 147 ostream& operator<<(ostream& out, const Sequencer& obj)
 148 {
 149   obj.print(out);
 150   out << flush;
 151   return out;
 152 }
 153
 154 #endif //SEQUENCER_H
 155