src/sim/pseudo_inst.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __SIM_PSEUDO_INST_HH__
  42 #define __SIM_PSEUDO_INST_HH__
  43
  44 #include <gem5/asm/generic/m5ops.h>
  45
  46 class ThreadContext;
  47
  48 #include "base/bitfield.hh"
  49 #include "base/logging.hh"
  50 #include "base/trace.hh"
  51 #include "base/types.hh" // For Tick and Addr data types.
  52 #include "cpu/thread_context.hh"
  53 #include "debug/PseudoInst.hh"
  54 #include "sim/guest_abi.hh"
  55
  56 namespace PseudoInst
  57 {
  58
  59 static inline void
  60 decodeAddrOffset(Addr offset, uint8_t &func)
  61 {
  62     func = bits(offset, 15, 8);
  63 }
  64
  65 void arm(ThreadContext *tc);
  66 void quiesce(ThreadContext *tc);
  67 void quiesceSkip(ThreadContext *tc);
  68 void quiesceNs(ThreadContext *tc, uint64_t ns);
  69 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
  70 uint64_t quiesceTime(ThreadContext *tc);
  71 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
  72     uint64_t offset);
  73 uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
  74     uint64_t offset, Addr filenameAddr);
  75 void loadsymbol(ThreadContext *xc);
  76 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
  77 uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
  78 uint64_t rpns(ThreadContext *tc);
  79 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
  80 void m5exit(ThreadContext *tc, Tick delay);
  81 void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
  82 uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c,
  83                                   uint64_t d, uint64_t e, uint64_t f);
  84 void resetstats(ThreadContext *tc, Tick delay, Tick period);
  85 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
  86 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
  87 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
  88 void debugbreak(ThreadContext *tc);
  89 void switchcpu(ThreadContext *tc);
  90 void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
  91 void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
  92 void m5Syscall(ThreadContext *tc);
  93 void togglesync(ThreadContext *tc);
  94 void triggerWorkloadEvent(ThreadContext *tc);
  95
  96 /**
  97  * Execute a decoded M5 pseudo instruction
  98  *
  99  * The ISA-specific code is responsible to decode the pseudo inst
 100  * function number and subfunction number. After that has been done,
 101  * the rest of the instruction can be implemented in an ISA-agnostic
 102  * manner using the ISA-specific getArguments functions.
 103  *
 104  * @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
 105  * @param result A reference to a uint64_t to store a result in.
 106  * @return Whether the pseudo instruction was recognized/handled.
 107  */
 108
 109 template <typename ABI, bool store_ret>
 110 bool
 111 pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
 112 {
 113     DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
 114
 115     result = 0;
 116
 117     switch (func) {
 118       case M5OP_ARM:
 119         invokeSimcall<ABI>(tc, arm);
 120         return true;
 121
 122       case M5OP_QUIESCE:
 123         invokeSimcall<ABI>(tc, quiesce);
 124         return true;
 125
 126       case M5OP_QUIESCE_NS:
 127         invokeSimcall<ABI>(tc, quiesceNs);
 128         return true;
 129
 130       case M5OP_QUIESCE_CYCLE:
 131         invokeSimcall<ABI>(tc, quiesceCycles);
 132         return true;
 133
 134       case M5OP_QUIESCE_TIME:
 135         result = invokeSimcall<ABI, store_ret>(tc, quiesceTime);
 136         return true;
 137
 138       case M5OP_RPNS:
 139         result = invokeSimcall<ABI, store_ret>(tc, rpns);
 140         return true;
 141
 142       case M5OP_WAKE_CPU:
 143         invokeSimcall<ABI>(tc, wakeCPU);
 144         return true;
 145
 146       case M5OP_EXIT:
 147         invokeSimcall<ABI>(tc, m5exit);
 148         return true;
 149
 150       case M5OP_FAIL:
 151         invokeSimcall<ABI>(tc, m5fail);
 152         return true;
 153
 154       // M5OP_SUM is for sanity checking the gem5 op interface.
 155       case M5OP_SUM:
 156         result = invokeSimcall<ABI, store_ret>(tc, m5sum);
 157         return true;
 158
 159       case M5OP_INIT_PARAM:
 160         result = invokeSimcall<ABI, store_ret>(tc, initParam);
 161         return true;
 162
 163       case M5OP_LOAD_SYMBOL:
 164         invokeSimcall<ABI>(tc, loadsymbol);
 165         return true;
 166
 167       case M5OP_RESET_STATS:
 168         invokeSimcall<ABI>(tc, resetstats);
 169         return true;
 170
 171       case M5OP_DUMP_STATS:
 172         invokeSimcall<ABI>(tc, dumpstats);
 173         return true;
 174
 175       case M5OP_DUMP_RESET_STATS:
 176         invokeSimcall<ABI>(tc, dumpresetstats);
 177         return true;
 178
 179       case M5OP_CHECKPOINT:
 180         invokeSimcall<ABI>(tc, m5checkpoint);
 181         return true;
 182
 183       case M5OP_WRITE_FILE:
 184         result = invokeSimcall<ABI, store_ret>(tc, writefile);
 185         return true;
 186
 187       case M5OP_READ_FILE:
 188         result = invokeSimcall<ABI, store_ret>(tc, readfile);
 189         return true;
 190
 191       case M5OP_DEBUG_BREAK:
 192         invokeSimcall<ABI>(tc, debugbreak);
 193         return true;
 194
 195       case M5OP_SWITCH_CPU:
 196         invokeSimcall<ABI>(tc, switchcpu);
 197         return true;
 198
 199       case M5OP_ADD_SYMBOL:
 200         invokeSimcall<ABI>(tc, addsymbol);
 201         return true;
 202
 203       case M5OP_PANIC:
 204         panic("M5 panic instruction called at %s\n", tc->pcState());
 205
 206       case M5OP_WORK_BEGIN:
 207         invokeSimcall<ABI>(tc, workbegin);
 208         return true;
 209
 210       case M5OP_WORK_END:
 211         invokeSimcall<ABI>(tc, workend);
 212         return true;
 213
 214       case M5OP_RESERVED1:
 215       case M5OP_RESERVED2:
 216       case M5OP_RESERVED3:
 217       case M5OP_RESERVED4:
 218       case M5OP_RESERVED5:
 219         warn("Unimplemented m5 op (%#x)\n", func);
 220         return false;
 221
 222       /* dist-gem5 functions */
 223       case M5OP_DIST_TOGGLE_SYNC:
 224         invokeSimcall<ABI>(tc, togglesync);
 225         return true;
 226
 227       case M5OP_WORKLOAD:
 228         invokeSimcall<ABI>(tc, triggerWorkloadEvent);
 229         return true;
 230
 231       default:
 232         warn("Unhandled m5 op: %#x\n", func);
 233         return false;
 234     }
 235 }
 236
 237 template <typename ABI, bool store_ret=false>
 238 bool
 239 pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
 240 {
 241     return pseudoInstWork<ABI, store_ret>(tc, func, result);
 242 }
 243
 244 template <typename ABI, bool store_ret=true>
 245 bool
 246 pseudoInst(ThreadContext *tc, uint8_t func)
 247 {
 248     uint64_t result;
 249     return pseudoInstWork<ABI, store_ret>(tc, func, result);
 250 }
 251
 252 } // namespace PseudoInst
 253
 254 #endif // __SIM_PSEUDO_INST_HH__