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erik and I made the the same modification... merged.
[gem5.git] / system / alpha / h / machine_defs.h
1 /*
2 * Copyright (C) 1998 by the Board of Trustees
3 * of Leland Stanford Junior University.
4 * Copyright (C) 1998 Digital Equipment Corporation
5 *
6 * This file is part of the SimOS distribution.
7 * See LICENSE file for terms of the license.
8 *
9 */
10
11 /***********************************************************************
12
13 machine_defs.h
14
15 ***********************************************************************/
16
17 /*************************************************************************
18 * *
19 * Copyright (C) 1993-1996 Stanford University *
20 * *
21 * These coded instructions, statements, and computer programs contain *
22 * unpublished proprietary information of Stanford University, and *
23 * are protected by Federal copyright law. They may not be disclosed *
24 * to third parties or copied or duplicated in any form, in whole or *
25 * in part, without the prior written consent of Stanford University. *
26 * *
27 *************************************************************************/
28
29 #ifndef __DPGCC__
30 #ifndef _HEADER_STACK_
31 #define _HEADER_STACK_
32 #endif
33 #endif
34
35 #ifndef _MACHINE_DEFS_H
36 #define _MACHINE_DEFS_H
37
38 /*
39 * Created by: Dan Teodosiu, 07/96
40 *
41 * This header file defines the OS view of the MAGIC service address space
42 * and of the device registers.
43 *
44 * The service address space addresses used by the OS are VIRTUAL addresses.
45 * Depending on whether we simulate a 32 bit or a 64 bit processor,
46 * the service address mappings will be different. MAGIC physical addresses
47 * are 40 bits wide, so in 32 bit mode (current SimOS) we had to squeeze
48 * the service address space into less address bits.
49 *
50 * There are two kinds of macros in this file:
51 *
52 * - MAGIC definitions, pertaining to the services offered by the
53 * MAGIC node controller. All these macros start with MAGIC_...,
54 * Those definitions are further subdivided into ones which do not
55 * depend on the address mappings (such as MAGIC register numbers,
56 * error codes, etc.), and ones which do (such as the macros that help
57 * construct MAGIC PPR addresses).
58 * The current simulated MAGIC only supports doubleword accesses.
59 *
60 * - devices register definitions, of the form DEV_... These defs
61 * describe the various device registers. Devices are accessed by
62 * performing uncached word (32bit) reads and writes to their registers.
63 *
64 * Notes:
65 * The macro SIMOS64BIT selects the 64 bit version of those definitions;
66 * by default, you get the 32 bit version. 64 bit is currently not
67 * implemented.
68 *
69 * Related documents:
70 * - FLASH: Physical Address Layout
71 * - FLASH: PP Software Services
72 * - SimOS to FLASH Physical Address Mapping
73 *
74 */
75
76
77 /***************************************************************************
78 MAGIC defs which do not depend on the virtual -> physical address mapping
79 ***************************************************************************/
80
81 /** zone numbering for service address space **/
82
83 #define MAGIC_ZONE_FRAM_ALIAS 0
84 #define MAGIC_ZONE_PPR_ALIAS 1
85 #define MAGIC_ZONE_PPC_ALIAS 2
86 #define MAGIC_ZONE_FIREWALL 3
87 #define MAGIC_ZONE_DMAMAP 4
88 #define MAGIC_ZONE_SWTLB 5
89 #define MAGIC_ZONE_MISSCNT 6
90 #define MAGIC_ZONE_NODEMAP 7
91 #define MAGIC_ZONE_PPR 8
92 #define MAGIC_ZONE_PPC 9
93 #define MAGIC_ZONE_MILO_ALIAS 10
94 #define MAGIC_ZONE_EV5_ALIAS 10
95 #define MAGIC_ZONE_NODECOMM 11 /* node communication zone */
96 /* do not def zone 12: see below why */
97 #define MAGIC_ZONE_BDOOR_DEV 14 /* backdoor area for devices */
98 #define MAGIC_ZONE_FPROM_ALIAS 15
99
100 #ifndef SIMOS64BIT
101 #undef MAGIC_ZONE_FPROM_ALIAS /* In 32bit Simos, 0xbfc00000 maps to... */
102 #define MAGIC_ZONE_FPROM_ALIAS 12 /* ... zone 12 */
103 #endif
104
105 /** PPR numbering **/
106
107 /* Individual MAGIC registers */
108
109 #define MAGIC_PPR_IECHIGH 0x0000 /* r */
110 #define MAGIC_PPR_ACKINTERNAL 0x0001 /* w */
111 #define MAGIC_PPR_IECENABLE 0x0002 /* r/w */
112 #define MAGIC_PPR_SENDIPI 0x0003 /* w */
113 #define MAGIC_PPR_OPSPACE 0x0004 /* r/w */
114 #define MAGIC_PPR_ASID 0x0005 /* r/w */
115 #define MAGIC_PPR_TLBINVAL 0x0006 /* w */
116 #define MAGIC_PPR_TLBINUSE 0x0007 /* r */
117 #define MAGIC_PPR_MSGTAG 0x0008 /* r/w */
118 #define MAGIC_PPR_STALLOSPC 0x0009 /* r/w */
119 #define MAGIC_PPR_CYCLECOUNT 0x000a /* r */
120 #define MAGIC_PPR_NETMSGTIME 0x000b /* r */
121 #define MAGIC_PPR_RESERVED_C 0x000c /* */
122 #define MAGIC_PPR_RESERVED_D 0x000d /* */
123 #define MAGIC_PPR_RESERVED_E 0x000e /* */
124 #define MAGIC_PPR_RESERVED_F 0x000f /* */
125
126 #define MAGIC_PPR_UNUSED10 0x0010 /* r */
127 #define MAGIC_PPR_PROTVERSION 0x0011 /* r */
128 #define MAGIC_PPR_HWVERSION 0x0012 /* r */
129 #define MAGIC_PPR_REMAPMASK 0x0013 /* r/w */
130 #define MAGIC_PPR_PROTCONTROL 0x0014 /* r/w */
131 #define MAGIC_PPR_RESERVED_15 0x0015 /* */
132 #define MAGIC_PPR_RESERVED_16 0x0016 /* */
133 #define MAGIC_PPR_RESERVED_17 0x0017 /* */
134 #define MAGIC_PPR_OUTOFRANGE 0x0018 /* r */
135 #define MAGIC_PPR_INTERVAL 0x0019 /* r/w */
136 #define MAGIC_PPR_SLOTMAP 0x001a /* r/w */
137 #define MAGIC_SLOTMAP_SLOT0_OFFS 0
138 #define MAGIC_SLOTMAP_SLOT0_MASK 0x00000000000000FFLL
139 #define MAGIC_SLOTMAP_SLOT1_OFFS 8
140 #define MAGIC_SLOTMAP_SLOT1_MASK 0x000000000000FF00LL
141 #define MAGIC_SLOTMAP_SLOT2_OFFS 16
142 #define MAGIC_SLOTMAP_SLOT2_MASK 0x0000000000FF0000LL
143 #define MAGIC_SLOTMAP_SLOT3_OFFS 24
144 #define MAGIC_SLOTMAP_SLOT3_MASK 0x00000000FF000000LL
145 #define MAGIC_PPR_FWSHIFT 0x001b /* r/w */
146 #define MAGIC_PPR_RECOVERYSYNC 0x001c /* r */
147 #define MAGIC_RECOVERYSYNC_PHASE_MASK 0xF000000000000000LL;
148 #define MAGIC_RECOVERYSYNC_PHASE_SHIFT 60
149 #define MAGIC_RECOVERYSYNC_PHASE_ZERO (0x0LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
150 #define MAGIC_RECOVERYSYNC_PHASE_ONE (0x1LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
151 #define MAGIC_RECOVERYSYNC_PHASE_TWO (0x2LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
152 #define MAGIC_RECOVERYSYNC_PHASE_THREE (0x3LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
153 #define MAGIC_RECOVERYSYNC_TIMESTAMP_MASK 0x0FFFFFFFFFFFFFFFLL
154 #define MAGIC_RECOVERYSYNC_TIMESTAMP_SHIFT 0
155 #define MAGIC_PPR_REPORT_DIAG_RESULT 0x001d /* w */
156 #define MAGIC_REPORT_PASS_DIAG 0 /* other values indicate fail */
157 #define MAGIC_PPR_RESERVED_1E 0x001e /* w */
158 #define MAGIC_PPR_DRAIN_POLL 0x001f /* r */
159
160 #define MAGIC_PPR_NODECONFIG 0x0020 /* r */
161 #define MAGIC_NODECONFIG_THISNODE_OFFS 0
162 #define MAGIC_NODECONFIG_THISNODE_MASK 0x0000000000000fffLL
163 #define MAGIC_NODECONFIG_FIRSTNODE_OFFS 12
164 #define MAGIC_NODECONFIG_FIRSTNODE_MASK 0x0000000000fff000LL
165 #define MAGIC_NODECONFIG_NODESINCELL_OFFS 24
166 #define MAGIC_NODECONFIG_NODESINCELL_MASK 0x0000000fff000000LL
167 #define MAGIC_NODECONFIG_THISCELL_OFFS 36
168 #define MAGIC_NODECONFIG_THISCELL_MASK 0x0000fff000000000LL
169 #define MAGIC_NODECONFIG_NCELLS_OFFS 48
170 #define MAGIC_NODECONFIG_NCELLS_MASK 0x0fff000000000000LL
171
172 #define MAGIC_NODECONFIG_THISNODE(val) \
173 (((val)&MAGIC_NODECONFIG_THISNODE_MASK)>>MAGIC_NODECONFIG_THISNODE_OFFS)
174 #define MAGIC_NODECONFIG_FIRSTNODE(val) \
175 (((val)&MAGIC_NODECONFIG_FIRSTNODE_MASK)>>MAGIC_NODECONFIG_FIRSTNODE_OFFS)
176 #define MAGIC_NODECONFIG_NODESINCELL(val) \
177 (((val)&MAGIC_NODECONFIG_NODESINCELL_MASK)>>MAGIC_NODECONFIG_NODESINCELL_OFFS)
178 #define MAGIC_NODECONFIG_THISCELL(val) \
179 (((val)&MAGIC_NODECONFIG_THISCELL_MASK)>>MAGIC_NODECONFIG_THISCELL_OFFS)
180 #define MAGIC_NODECONFIG_NCELLS(val) \
181 (((val)&MAGIC_NODECONFIG_NCELLS_MASK)>>MAGIC_NODECONFIG_NCELLS_OFFS)
182
183 #define MAGIC_PPR_ADDRCONFIG 0x0021 /* r */
184 #define MAGIC_ADDRCONFIG_PAGES_OFFS 0
185 #define MAGIC_ADDRCONFIG_PAGES_MASK 0x0000ffffffffLL
186 #define MAGIC_ADDRCONFIG_NNBITS_OFFS 32
187 #define MAGIC_ADDRCONFIG_NNBITS_MASK 0x00ff00000000LL
188 #define MAGIC_ADDRCONFIG_MASBITS_OFFS 40
189 #define MAGIC_ADDRCONFIG_MASBITS_MASK 0xff0000000000LL
190
191 #define MAGIC_ADDRCONFIG_PAGES(val) \
192 (((val)&MAGIC_ADDRCONFIG_PAGES_MASK)>>MAGIC_ADDRCONFIG_PAGES_OFFS)
193 #define MAGIC_ADDRCONFIG_NNBITS(val) \
194 (((val)&MAGIC_ADDRCONFIG_NNBITS_MASK)>>MAGIC_ADDRCONFIG_NNBITS_OFFS)
195 #define MAGIC_ADDRCONFIG_MASBITS(val) \
196 (((val)&MAGIC_ADDRCONFIG_MASBITS_MASK)>>MAGIC_ADDRCONFIG_MASBITS_OFFS)
197
198 /* OSPC mirror in uncached space (used by FPROM) */
199 #define MAGIC_PPR_OSPC 0x1000 /* r */
200
201
202 /** PPC error codes **/
203
204 #define MAGIC_PPC_NOT_SUCCESSFUL_BIT 0x8000000000000000LL /* set for error */
205 /* these return values should be ORed with the "not successful" bit */
206 #define MAGIC_PPC_RETRY_CODE 0x00 /* please retry request (default) */
207 #define MAGIC_PPC_BADGROUP 0x01 /* PPC group was invalid */
208 #define MAGIC_PPC_BADOPCODE 0x02 /* PPC opcode was invalid */
209 #define MAGIC_PPC_ARGOUTOFRANGE 0x03 /* some arg to the PPC was bad */
210 #define MAGIC_PPC_BUSY 0x04 /* operation needed some
211 * resource that was unavail */
212 /* these results indicate the request cannot be serviced, and it should
213 not be retried. The interpretation of these is protocol-dependent
214 One example is: the physical pages are remote. The application
215 can't know this, but the sequence was otherwise valid. If a protocol
216 can't handle remote pages, this is a possibility. So, e.g. fmemcpy
217 uses PROT_FAIL1 to indicate it can't handle the pages. See the
218 individual _interface files to describe the interpretation*/
219 #define MAGIC_PPC_PROT_FAIL1 0x11
220 #define MAGIC_PPC_PROT_FAIL2 0x12
221 #define MAGIC_PPC_PROT_FAIL3 0x13
222 #define MAGIC_PPC_RETRY (MAGIC_PPC_NOT_SUCCESSFUL_BIT|MAGIC_PPC_RETRY_CODE)
223
224 /** PPC groups **/
225
226 #define MAGIC_PPC_GROUP_KERNEL 0x000
227 #define MAGIC_PPC_GROUP_MSG 0x001
228
229 /** kernel group opcodes **/
230
231 #define MAGIC_PPC_OP_SIPSLO 0x000
232 #define MAGIC_PPC_OP_SIPSHI 0x001
233 #define MAGIC_PPC_OP_MEMCPY 0x002
234 #define MAGIC_PPC_OP_IBITWRITE 0x003
235 #define MAGIC_PPC_OP_IBITREAD 0x004
236 #define MAGIC_PPC_OP_DONATE 0x005
237 #define MAGIC_PPC_OP_RESETPOOL 0x006
238 #define MAGIC_PPC_OP_LOADSTATE 0x007
239 #define MAGIC_PPC_OP_STORESTATE 0x008
240 #define MAGIC_PPC_OP_MEMRESET 0x009
241 #define MAGIC_PPC_OP_VECTORPKT 0x00A
242 #define MAGIC_PPC_OP_BZERO 0x00B
243 /* HLL/Diag opcodes within kernel region */
244 #define MAGIC_PPC_OP_PRINTF1 0x00C
245 /* config info opcodes within kernel region */
246 /* note: result has same format as MAGIC_PPR_NODECONFIG and
247 * MAGIC_PPR_ADDRCONFIG PPR's.
248 */
249 #define MAGIC_PPC_OP_CELLNODECONFIG 0x010
250 #define MAGIC_PPC_OP_NODEADDRCONFIG 0x011
251 #define MAGIC_PPC_OP_STARTSLAVENODE 0x012
252
253 /** msg group opcodes **/
254 #define MAGIC_PPC_OP_MEMCPY_V 0x000
255 #define MAGIC_PPC_OP_SIPS_V 0x001
256 #define MAGIC_PPC_OP_BZERO_V 0x002
257
258
259 /** OSPC defs **/
260
261 /* OSPC opcodes.
262 *
263 * Note:
264 * In the future we will probably add more structure to the header dword...
265 * for example, in SIPS it would be nice to have the sender CPU from the
266 * message header there, which authenticates the sender at a lower level
267 * than the sender cell info in the SIPS header. Because this will happen
268 * eventually, these opcodes are not defined as 0x01LL.
269 */
270 #define MAGIC_OSPC_LO_NONE 0xff /* no OSPC pending */
271 #define MAGIC_OSPC_LO_SIPSREQ 0x01 /* lopri SIPS pending */
272 #define MAGIC_OSPC_LO_CACHECTR 0x02 /* ??? */
273
274 #define MAGIC_OSPC_HI_NONE 0xff /* no OSPC pending */
275 #define MAGIC_OSPC_HI_SIPSREPLY 0x81 /* hipri SIPS pending */
276 #define MAGIC_OSPC_HI_TLBMISS 0x82 /* ??? */
277
278 /* For vector packet payload retrieval... in the future we'll move to some
279 method other than OSPCs for this. */
280 #define MAGIC_OSPC_VEC_REQ_NONE 0xff
281 #define MAGIC_OSPC_VEC_REQ 0xd1
282 #define MAGIC_OSPC_VEC_REP_NONE 0xff
283 #define MAGIC_OSPC_VEC_REP 0xe1
284
285 /* OSPC offsets */
286 #define MAGIC_OSPC_SIZE 128 /* OSPC size == 1 cache line */
287
288 #define MAGIC_OSPC_LO_OFFS 0*MAGIC_OSPC_SIZE /* lopri SIPS */
289 #define MAGIC_OSPC_HI_OFFS 1*MAGIC_OSPC_SIZE /* hipri SIPS */
290 #define MAGIC_OSPC_VEC_REQ_OFFS 2*MAGIC_OSPC_SIZE /* VP request */
291 #define MAGIC_OSPC_VEC_REP_OFFS 3*MAGIC_OSPC_SIZE /* VP reply */
292
293 /***************************************************************************
294 MAGIC defs which reflect the virtual -> physical address mapping
295 ***************************************************************************/
296
297 /* auxiliary defs -- ONLY FOR INTERNAL USE IN THIS FILE */
298
299 #ifndef SIMOS64BIT /* 32 bit address space (current SimOS version) */
300
301 /* virtual addresses for start of FPROM and FRAM */
302 #define FPROM_BASE _SEXT(0xbfc00000)
303 #define FRAM_BASE _SEXT(0xa0000000)
304
305 #ifdef _KERNEL
306 #define __MAGIC_BASE COMPAT_K1BASE /* KSEG1 */
307 #define __MAGIC_BASE_32 COMPAT_K1BASE_32 /* KSEG1 */
308 #define __MAGIC_BASE_ACC COMPAT_K1BASE /* still KSEG1 */
309 #else
310 #define __MAGIC_BASE K1BASE /* KSEG1 */
311 #define __MAGIC_BASE_32 K1BASE_32 /* KSEG1 */
312 #define __MAGIC_BASE_ACC K1BASE /* still KSEG1 */
313 #endif
314 #define __MAGIC_OSPC_BASE (K0BASE+0x1000) /* OSPC right after remap */
315 #define __MAGIC_OSPC_END (K0BASE+0x2000) /* 1 page-alias for each node */
316
317 #define __MAGIC_NODE_BITS 5 /* max. 32 nodes */
318 #define __MAGIC_NODE_OFFS 24
319
320 #define __MAGIC_ZONE_BITS 4 /* 16 zones / node */
321 #define __MAGIC_ZONE_OFFS 20 /* 1MB / zone */
322
323 #define __MAGIC_REG_BITS 17
324 #define __MAGIC_REG_OFFS 3 /* registers are 64bit */
325
326 #define __MAGIC_PPC_SEQ_BITS 7 /* one cache line */
327 #define __MAGIC_PPC_SEQ_OFFS 0
328 #define __MAGIC_PPC_OPC_BITS 5 /* group corresponds to a 4K page */
329 #define __MAGIC_PPC_OPC_OFFS __MAGIC_PPC_SEQ_BITS
330 #define __MAGIC_PPC_GRP_BITS 8
331 #define __MAGIC_PPC_GRP_OFFS (__MAGIC_PPC_SEQ_BITS+__MAGIC_PPC_OPC_BITS)
332
333 #define __MAGIC_ZONE(node, nbits, zone) \
334 ( __MAGIC_BASE | ((node) << __MAGIC_NODE_OFFS) \
335 | ((zone) << __MAGIC_ZONE_OFFS) )
336 #define __MAGIC_ZONE_32(node, nbits, zone) \
337 ( __MAGIC_BASE_32 | ((node) << __MAGIC_NODE_OFFS) \
338 | ((zone) << __MAGIC_ZONE_OFFS) )
339 #define __MAGIC_ZONE_ACC(node, nbits, zone) \
340 ( __MAGIC_BASE_ACC | ((node) << __MAGIC_NODE_OFFS) \
341 | ((zone) << __MAGIC_ZONE_OFFS) )
342 #define __MAGIC_ZONE_ALIAS(zone) \
343 ( __MAGIC_BASE | ((zone) << __MAGIC_ZONE_OFFS) )
344 #define __MAGIC_ZONE_ALIAS_ACC(zone) \
345 ( __MAGIC_BASE_ACC | ((zone) << __MAGIC_ZONE_OFFS) )
346 #define __MAGIC_OSPC_RANGE(node, nbits) \
347 ( __MAGIC_OSPC_BASE )
348
349 #define MAGIC_MAX_REMAP_PAGES 1 /* max. sz of remap area (limited
350 * by OSPC in following page) */
351
352 /* offsets in bdoor zone of simulated devices (64KB each) */
353 #define __MAGIC_BDOOR_CLOCK_OFFS 0x00000000 /* CMOS rt clock */
354 #define __MAGIC_BDOOR_CNSLE_OFFS 0x00001000 /* console interface */
355 #define __MAGIC_BDOOR_ETHER_OFFS 0x00002000 /* ethernet controller */
356 #define __MAGIC_BDOOR_DISKS_OFFS 0x00010000 /* scsi disk controller */
357
358 #ifdef TORNADO
359 #define __MAGIC_BDOOR_GIZMO_OFFS \
360 ((__MAGIC_BDOOR_DISKS_OFFS + sizeof(DevDiskRegisters)*DEV_DISK_MAX_DISKS + \
361 0x1000 - 1) & ~(0x1000-1)) /* gizmo interface */
362 #endif
363
364 #else /* SIMOS64BIT */ /* 64 bit address space */
365 not yet implemented, will not compile;
366 #endif /* SIMOS64BIT */
367
368 #ifdef LANGUAGE_ASSEMBLY
369 #define MagicRegister int
370 #define MAGICREGP_CAST
371 #else
372 typedef uint64 MagicRegister;
373 #define MAGICREGP_CAST (MagicRegister *)
374 #endif
375
376 /* PPR access */
377 #define MAGIC_PPR(node, nbits, reg) \
378 ((MagicRegister*) \
379 (__MAGIC_ZONE(node,nbits,MAGIC_ZONE_PPR) | ((reg) << __MAGIC_REG_OFFS)))
380 #define MAGIC_PPR_ALIAS(reg) \
381 (MAGICREGP_CAST \
382 (__MAGIC_ZONE_ALIAS(MAGIC_ZONE_PPR_ALIAS) | ((reg) << __MAGIC_REG_OFFS)))
383 #define MAGIC_PPR_NODE(addr, nbits) \
384 ( ((addr) >> __MAGIC_NODE_OFFS) & ((1LL << (nbits)) - 1) )
385 #define MAGIC_PPR_ZONE(addr) \
386 ( ((addr) >> __MAGIC_ZONE_OFFS) & ((1LL << __MAGIC_ZONE_BITS) - 1) )
387 #define MAGIC_PPR_REG(addr) \
388 ( ((addr) >> __MAGIC_REG_OFFS) & ((1LL << __MAGIC_REG_BITS) - 1) )
389
390 /* PPC access */
391 #define MAGIC_PPC(node, nbits, grp, opc) \
392 ((MagicRegister*) \
393 ( __MAGIC_ZONE(node,nbits,MAGIC_ZONE_PPC) | \
394 ((grp) << __MAGIC_PPC_GRP_OFFS) | \
395 ((opc) << __MAGIC_PPC_OPC_OFFS) ))
396 #define MAGIC_PPC_ACC(node, nbits, grp, opc) \
397 ((MagicRegister*) \
398 ( __MAGIC_ZONE_ACC(node,nbits,MAGIC_ZONE_PPC) | \
399 ((grp) << __MAGIC_PPC_GRP_OFFS) | \
400 ((opc) << __MAGIC_PPC_OPC_OFFS) ))
401 #define MAGIC_PPC_ALIAS(grp, opc) \
402 (MAGICREGP_CAST \
403 ( __MAGIC_ZONE_ALIAS(MAGIC_ZONE_PPC_ALIAS) \
404 | ((grp) << __MAGIC_PPC_GRP_OFFS) \
405 | ((opc) << __MAGIC_PPC_OPC_OFFS) ))
406 #define MAGIC_PPC_ALIAS_ACC(grp, opc) \
407 ((MagicRegister*) \
408 ( __MAGIC_ZONE_ALIAS_ACC(MAGIC_ZONE_PPC_ALIAS) \
409 | ((grp) << __MAGIC_PPC_GRP_OFFS) \
410 | ((opc) << __MAGIC_PPC_OPC_OFFS) ))
411
412 #define MAGIC_PPC_NODE(addr,nbits) \
413 ( ((addr) >> __MAGIC_NODE_OFFS) & ((1LL << (nbits)) - 1) )
414 #define MAGIC_PPC_ZONE(addr) \
415 ( ((addr) >> __MAGIC_ZONE_OFFS) & ((1LL << __MAGIC_ZONE_BITS) - 1) )
416 #define MAGIC_PPC_GRP(addr) \
417 ( ((addr) >> __MAGIC_PPC_GRP_OFFS) & ((1LL << __MAGIC_PPC_GRP_BITS) - 1) )
418 #define MAGIC_PPC_OPC(addr) \
419 ( ((addr) >> __MAGIC_PPC_OPC_OFFS) & ((1LL << __MAGIC_PPC_OPC_BITS) - 1) )
420
421 /* Nodemap access */
422 #define MAGIC_NODEMAP(node, nbits, reg) \
423 ((MagicRegister*) \
424 (__MAGIC_ZONE(node,nbits,MAGIC_ZONE_NODEMAP) | ((reg) << __MAGIC_REG_OFFS)))
425
426 /* Nodecomm access */
427 #define MAGIC_NODECOMM(node, nbits, n) \
428 ((MagicRegister*) \
429 (__MAGIC_ZONE(node,nbits,MAGIC_ZONE_NODECOMM) | ((n) << __MAGIC_REG_OFFS)))
430
431 /* OSPC access */
432 #define MAGIC_OSPC(node, nbits, ospc) \
433 ( (MagicRegister*)(__MAGIC_OSPC_RANGE(node, nbits) + (ospc)) )
434
435 #define MAGIC_UNCACHED_OSPC(node, nbits, offs) \
436 MAGIC_PPR(node, nbits, MAGIC_PPR_OSPC + ((offs) >> __MAGIC_REG_OFFS))
437
438 #define MAGIC_UNCACHED_OSPC_ALIAS(offs) \
439 MAGIC_PPR_ALIAS(MAGIC_PPR_OSPC + ((offs) >> __MAGIC_REG_OFFS))
440
441 #define MAGIC_OSPC_OPCODE(val) ((int)((val) & ((MagicRegister)0xff)))
442
443 /* firewall access */
444 #define MAGIC_FW_RANGE(node, nbits) \
445 ((MagicRegister*) __MAGIC_ZONE(node,nbits,MAGIC_ZONE_FIREWALL))
446
447
448 /***************************************************************************
449 definitions of the simulated devices and of various parameters
450 which depend on the simulator.
451 ***************************************************************************/
452
453 #define MAGIC_MAX_CPUS 32 /* max no of nodes in a simulation */
454 #define MAGIC_MAX_CELLS 32 /* max no of cells in a simulation */
455
456
457 /* needed so assembly files can include machine_defs */
458 #ifndef LANGUAGE_ASSEMBLY
459
460
461 typedef unsigned int DevRegister;
462
463 /* disk device:
464 * there is currently one controller per cell. The controller
465 * can be accessed through the backdoor zone of the first node
466 * in the cell.
467 */
468
469 #define DEV_DISK_CMD_SIZE 12
470 #define DEV_DISK_MAX_DMA_LENGTH 1024 /* max no of pages for one request */
471 #define DEV_DISK_MAX_DISKS 128 /* max disks per controller (cell) */
472
473 typedef struct DevDiskRegisters {
474 DevRegister intr_pending; /* r:int posted for this disk / w:ack int */
475 DevRegister errnoVal; /* status of last i/o */
476 DevRegister bytesTransferred; /* bytes transferred during last i/o */
477
478 DevRegister interruptNode; /* node to interrupt upon completion */
479 DevRegister k0Addr[DEV_DISK_MAX_DMA_LENGTH]; /* page addresses */
480 DevRegister offset; /* page offset for first page */
481 DevRegister command[DEV_DISK_CMD_SIZE]; /* i/o command */
482
483 DevRegister startIO; /* write here causes i/o initiation */
484 DevRegister doneIO; /* tells when i/o complete */
485
486 DevRegister filler[16]; /* filler: resize when you add new regs */
487 } DevDiskRegisters;
488
489 #define DEV_DISK_REGISTERS(node, nbits, disk) \
490 ( ((volatile DevDiskRegisters*) \
491 (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
492 __MAGIC_BDOOR_DISKS_OFFS)) + \
493 (disk) )
494
495
496 /* console device:
497 * there is currently one console per cell. The console registers
498 * can be accessed through the backdoor zone of the first node
499 * in the cell. The console always interrupts this node.
500 */
501
502 #define DEV_CNSLE_TX_INTR 0x01 /* intr enable / state bits */
503 #define DEV_CNSLE_RX_INTR 0x02
504
505 typedef struct DevConsoleRegisters {
506 DevRegister intr_status; /* r: intr state / w: intr enable */
507 DevRegister data; /* r: current char / w: send char */
508 } DevConsoleRegisters;
509
510 #define DEV_CONSOLE_REGISTERS(node, nbits) \
511 ( ((volatile DevConsoleRegisters*) \
512 (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
513 __MAGIC_BDOOR_CNSLE_OFFS)) )
514
515
516 /* ethernet device:
517 * there is currently one ether interface per cell. The ether registers
518 * can be accessed through the backdoor zone of the first node
519 * in the cell. The ether interface always interrupts this node.
520 */
521
522 #define DEV_ETHER_MAX_RCV_ENTRIES 64
523 #define DEV_ETHER_MAX_SND_ENTRIES 64
524 #define DEV_ETHER_MAX_SND_CHUNKS 128
525
526 #define DEV_ETHER_MAX_TRANSFER_SIZE 1800
527
528 typedef struct DevEtherRegisters {
529 DevRegister etheraddr[6]; /* controller tells OS its ethernet addr */
530 DevRegister numRcvEntries; /* read by OS, indicates how many receive
531 * ring buffer entries will be used. OS must
532 * allocate a receive buffer for each of
533 * these entries */
534 DevRegister numSndEntries; /* read by OS, indicates how many send ring
535 * buffer entries will be used so it knows
536 * when to wrap its index pointer */
537 DevRegister numSndChunks; /* same as numSndEntries */
538
539 struct {
540 DevRegister pAddr;
541 DevRegister maxLen;
542 DevRegister len;
543 DevRegister flag;
544 } rcvEntries[ DEV_ETHER_MAX_RCV_ENTRIES ];
545
546 struct {
547 DevRegister firstChunk;
548 DevRegister lastChunk;
549 DevRegister flag; /* triggers send */
550 } sndEntries[ DEV_ETHER_MAX_SND_ENTRIES ];
551
552 struct {
553 DevRegister pAddr;
554 DevRegister len;
555 } sndChunks[ DEV_ETHER_MAX_SND_CHUNKS ];
556
557 /* note: sndChunks is last because we might extend the number of
558 * send chunks in the future and don't want to break OS compatibility when
559 * we do it */
560 } DevEtherRegisters;
561
562 /* values for flag field */
563 #define DEV_ETHER_OS_OWNED (DevRegister)1
564 #define DEV_ETHER_CONTROLLER_OWNED (DevRegister)2
565
566 #define DEV_ETHER_REGISTERS(node, nbits) \
567 ( ((volatile DevEtherRegisters*) \
568 (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
569 __MAGIC_BDOOR_ETHER_OFFS)) )
570
571
572 /* CMOS RT clock device:
573 * This simulates a very primitive CMOS clock. This device only
574 * has one register that contains the time since January 1, 1970
575 * (same as the Unix gettimeofday() result).
576 */
577
578 typedef struct DevClockRegisters {
579 DevRegister ctime; /* current time */
580 } DevClockRegisters;
581
582 #define DEV_CLOCK_REGISTERS(node, nbits) \
583 ( ((volatile DevClockRegisters*) \
584 (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
585 __MAGIC_BDOOR_CLOCK_OFFS)) )
586
587
588 #endif /* LANGUAGE_ASSEMBLY */
589
590
591 /* Interrupt bit assignments:
592 *
593 * There are 64 external interrupt lines coming into MAGIC. The
594 * following defines show to what interrupt line each device is
595 * connected.
596 *
597 * NOTE: when MAGIC posts an interrupt, the IEChigh register will
598 * contain the bit number of the highest level interrupt pending,
599 * so the bit numbers are also IEC's (Interrupt Exception Codes).
600 */
601
602 #define DEV_IEC_SCSI 0x08 /* scsi disk controller */
603 #define DEV_IEC_ETHER 0x09 /* ether controller */
604 #define DEV_IEC_OSPC_LO 0x0a /* low-priority SIPS */
605 #define DEV_IEC_VEC_REQ 0x0b /* vector packet request */
606 #define DEV_IEC_KEYBDMOUSE 0x10 /* console */
607 #define DEV_IEC_DUART 0x11 /* serial line on FLASH board */
608 #define DEV_IEC_OSPC_HI 0x12 /* high-priority SIPS */
609 #define DEV_IEC_RECOVERY 0x13 /* recov int (posted by MAGIC) */
610 #define DEV_IEC_VEC_REPLY 0x14 /* vector packet reply */
611 #define DEV_IEC_CLOCK 0x18 /* clock */
612 #define DEV_IEC_IPI 0x20 /* inter-processor interrupt */
613 #define DEV_IEC_DEBUG 0x21 /* ??? */
614 #define DEV_IEC_PROFTIM 0x28 /* prof timer (currently unused) */
615 #define DEV_IEC_MAGICWARN 0x29 /* ??? */
616 #define DEV_IEC_MAGICERR 0x31 /* ??? */
617 #define DEV_IEC_POWERFAIL 0x38 /* ??? */
618
619 #define DEV_IEC_MAX 0x3f /* 64 bits */
620
621
622 /* PCI slot assignments:
623 *
624 * NOTE:
625 * On the real system these slot assignments wouldn't be fixed (you
626 * could plug a card into any slot on the I/O bus) but this isn't
627 * particularly interesting to model.
628 */
629
630 #define DEV_PCI_DISK_SLOT 0
631 #define DEV_PCI_ETHER_SLOT 1
632 #define DEV_PCI_CONSOLE_SLOT 2
633
634
635 #endif /* _MACHINE_DEFS_H */