system/alpha/h/tga.h

   1 /*
   2  * @DEC_COPYRIGHT@
   3  */
   4 /*
   5  * HISTORY
   6  * $Log: tga.h,v $
   7  * Revision 1.1.1.1  1997/10/30 23:27:18  verghese
   8  * current 10/29/97
   9  *
  10  * Revision 1.1.9.2  1995/04/24  23:34:47  Jeff_Colburn
  11  *      Add support for shared interrupts, ISR's now have a return value
  12  *      of INTR_SERVICED or INTR_NOT_SERVICED. Changed return type from "void"
  13  *      to "int" for interrupt return type in "tga_info_t".
  14  *      [1995/04/24  23:24:12  Jeff_Colburn]
  15  *
  16  * Revision 1.1.7.2  1994/11/07  23:31:23  Jeff_Colburn
  17  *      Added defines for putting TGA in Copy mode to support console scrolling fix.
  18  *      [1994/10/26  22:32:00  Jeff_Colburn]
  19  *
  20  * Revision 1.1.5.5  1994/05/16  19:29:08  Monty_Brandenberg
  21  *      Add dma_map_info_t to the info struct.
  22  *      [1994/05/12  05:31:19  Monty_Brandenberg]
  23  *
  24  * Revision 1.1.5.4  1994/04/19  21:59:33  Stuart_Hollander
  25  *      merge agoshw2 bl5 to gold bl10
  26  *      Revision 1.1.2.4  1994/04/14  20:17:15  Monty_Brandenberg
  27  *      T32-88 Framebuffer offset was incorrect causing obscure z buffering
  28  *      problems in pex.
  29  *      [1994/04/14  19:17:10  Monty_Brandenberg]
  30  *
  31  * Revision 1.1.5.3  1994/04/11  12:58:27  Stuart_Hollander
  32  *      Revision 1.1.2.3  1994/02/28  16:53:52  Monty_Brandenberg
  33  *      Removed a few magic numbers from the code and made symbolics out of
  34  *      them.
  35  *      [1994/02/23  21:09:10  Monty_Brandenberg]
  36  *
  37  *      Add header files we need to define structures.  Added two new ioctls
  38  *      to extract direct dma mapping info.  SFB+ and TGA ioctl structures
  39  *      are now incompatible.  Fixed truecolor index and private ioctl code.
  40  *      [1994/02/04  21:10:07  Monty_Brandenberg]
  41  *
  42  *      Removed two interrupt sources as per spec.  Fixed the RAMDAC access
  43  *      macros to actually work.  Imagine.
  44  *      [1994/02/02  23:16:55  Monty_Brandenberg]
  45  *
  46  *      Converted to use io_handles.  Needs work on DMA
  47  *      [1994/01/07  21:14:33  Monty_Brandenberg]
  48  *
  49  *      Added support for 24-plane option using BT463 and custom cursor chip.
  50  *      Converted to fully prototyped functions.  Started conversion to
  51  *      io_handle structure.
  52  *      [1994/01/06  21:15:14  Monty_Brandenberg]
  53  *
  54  * Revision 1.1.5.2  1994/01/23  21:16:19  Stuart_Hollander
  55  *      merge from hw2 to goldbl8
  56  *      [1993/12/29  12:57:23  Stuart_Hollander]
  57  *
  58  * Revision 1.1.2.2  1993/12/21  13:42:28  Monty_Brandenberg
  59  *      Initial version of the TGA device driver.
  60  *      [1993/12/14  00:22:06  Monty_Brandenberg]
  61  *
  62  * $EndLog$
  63  */
  64 /*
  65  * @(#)$RCSfile: tga.h,v $ $Revision: 1.1.1.1 $ (DEC) $Date: 1997/10/30 23:27:18 $
  66  */
  67
  68 /************************************************************************
  69  *                                                                      *
  70  *                      Copyright (c) 1993 by                           *
  71  *              Digital Equipment Corporation, Maynard, MA              *
  72  *                      All rights reserved.                            *
  73  *                                                                      *
  74  *   This software is furnished under a license and may be used and     *
  75  *   copied  only  in accordance with the terms of such license and     *
  76  *   with the  inclusion  of  the  above  copyright  notice.   This     *
  77  *   software  or  any  other copies thereof may not be provided or     *
  78  *   otherwise made available to any other person.  No title to and     *
  79  *   ownership of the software is hereby transferred.                   *
  80  *                                                                      *
  81  *   The information in this software is subject to change  without     *
  82  *   notice  and should not be construed as a commitment by Digital     *
  83  *   Equipment Corporation.                                             *
  84  *                                                                      *
  85  *   Digital assumes no responsibility for the use  or  reliability     *
  86  *   of its software on equipment which is not supplied by Digital.     *
  87  *                                                                      *
  88  ************************************************************************/
  89
  90 /*
  91  * RAMDAC is a trademark of Brooktree Corporation
  92  */
  93
  94 #ifndef TGA_DEFINED
  95 #define TGA_DEFINED
  96
  97 /*
  98  * Header files
  99  */
 100 #if 0
 101 #include <sys/types.h>
 102 #include <sys/ioctl.h>
 103 #include <sys/workstation.h>
 104 #include <sys/inputdevice.h>
 105 #include <sys/wsdevice.h>
 106 #include <io/common/devdriver.h>
 107 #endif                                  /* 0 */
 108
 109 /*
 110  * Special offsets within the PCI configuration header
 111  */
 112 #define TGA_CONFIG_PVRR_OFFSET          0x00000040
 113 #define TGA_CONFIG_PAER_OFFSET          0x00000044
 114
 115 /*
 116  * PAER values
 117  */
 118 #define TGA_CONFIG_PAER_32MB            0x00000000
 119 #define TGA_CONFIG_PAER_64MB            0x00010000
 120 #define TGA_CONFIG_PAER_128MB           0x00030000
 121
 122 /*
 123  * Offsets within Memory Space
 124  */
 125 #define TGA_ROM_OFFSET                  0x000000
 126 #define TGA_ASIC_OFFSET                 0x100000
 127 #define TGA_RAMDAC_SETUP_OFFSET         0x1000c0
 128 #define TGA_RAMDAC_DATA_OFFSET          0x1001f0
 129 #define TGA_XY_REG_OFFSET               0x100074
 130 #define TGA_VALID_REG_OFFSET            0x100070
 131
 132 #define TGA_0_0_FB_OFFSET               0x00200000
 133 #define TGA_0_0_FB_SIZE                 0x00200000
 134 #define TGA_0_1_FB_OFFSET               0x00400000
 135 #define TGA_0_1_FB_SIZE                 0x00400000
 136 #define TGA_0_3_FB_OFFSET               0x00800000
 137 #define TGA_0_3_FB_SIZE                 0x00800000
 138 #define TGA_1_3_FB_OFFSET               0x00800000
 139 #define TGA_1_3_FB_SIZE                 0x00800000
 140 #define TGA_1_7_FB_OFFSET               0x01000000
 141 #define TGA_1_7_FB_SIZE                 0x01000000
 142 #define TGA_INVALID_FB_OFFSET           0
 143 #define TGA_INVALID_FB_SIZE             0
 144
 145 /*
 146  * TGA card types
 147  */
 148 #define TGA_TYPE_T801                   0
 149 #define TGA_TYPE_T802                   1
 150 #define TGA_TYPE_T822                   2
 151 #define TGA_TYPE_T844                   3
 152 #define TGA_TYPE_T3204                  4
 153 #define TGA_TYPE_T3208                  5
 154 #define TGA_TYPE_T3288                  6
 155 #define TGA_TYPE_INVALID                7
 156 #define TGA_TYPE_NUM                    8
 157
 158 #ifndef NDEPTHS
 159 #define NDEPTHS 1                       /* all current hardware just has one */
 160 #define NVISUALS 1
 161 #endif                                  /* NDEPTHS */
 162
 163 typedef unsigned char tga_pix8_t;
 164 typedef unsigned int tga_pix32_t;
 165 typedef unsigned int tga_reg_t;
 166
 167 /*
 168  * Window tags definitions
 169  */
 170 #define TGA_TRUECOLOR_WID_INDEX         0xc
 171 #define TGA_TRUECOLOR_WID_MASK          0xc0000000
 172
 173 #if 0
 174 /*
 175  * Device-private ioctls
 176  */
 177 #define TGA_IOCTL_PRIVATE               _IOWR('w', (0|IOC_S), tga_ioc_t)
 178 #define TGA_IOC_LOAD_WINDOW_TAGS        0
 179 #define TGA_IOC_ENABLE_DMA_OPS          1
 180 #define TGA_IOC_SET_STEREO_MODE         2
 181 #define TGA_IOC_GET_STEREO_MODE         3
 182 #define TGA_IOC_GET_DIRECT_DMA_COUNT    4
 183 #define TGA_IOC_GET_DIRECT_DMA_INFO     5
 184
 185 typedef struct {
 186     char windex;
 187     unsigned char low;
 188     unsigned char mid;
 189     unsigned char high;
 190 } tga_window_tag_cell_t;
 191
 192 typedef struct {
 193     short ncells;
 194     short start;
 195     tga_window_tag_cell_t *p_cells;
 196 } tga_ioc_window_tag_t;
 197
 198 typedef struct {
 199     vm_offset_t phys_base;
 200     vm_offset_t bus_base;
 201     vm_size_t map_size;
 202 } tga_dma_map_t;
 203
 204 typedef struct {
 205     int alloc_map_num;                  /* input */
 206     int actual_map_num;                 /* output */
 207     tga_dma_map_t *maps;                /* input & output */
 208 } tga_ioc_dma_info_t;
 209
 210 typedef struct {
 211     short screen;
 212     short cmd;
 213     union {
 214         tga_ioc_window_tag_t window_tag;
 215         unsigned int stereo_mode;
 216 #define TGA_IOC_STEREO_NONE             0
 217 #define TGA_IOC_STEREO_24               1
 218
 219 int direct_dma_count;
 220         tga_ioc_dma_info_t direct_dma_info;
 221     } data;
 222 } tga_ioc_t;
 223 #endif                                  /* 0 */
 224
 225 typedef struct {
 226     unsigned deep : 1;
 227     unsigned mbz0 : 1;
 228     unsigned mask : 3;
 229     unsigned block : 4;
 230     unsigned col_size : 1;
 231     unsigned sam_size : 1;
 232     unsigned parity : 1;
 233     unsigned write_en : 1;
 234     unsigned ready : 1;
 235     unsigned slow_dac : 1;
 236     unsigned dma_size : 1;
 237     unsigned sync_type : 1;
 238     unsigned mbz1 : 15;
 239 } tga_deep_reg_t;
 240
 241 #define TGA_DEEP_DEEP_8PLANE            0
 242 #define TGA_DEEP_DEEP_32PLANE           1
 243
 244 #define TGA_DEEP_MASK_4MB               0x00
 245 #define TGA_DEEP_MASK_8MB               0x01
 246 #define TGA_DEEP_MASK_16MB              0x03
 247 #define TGA_DEEP_MASK_32MB              0x07
 248
 249 #define TGA_DEEP_PARITY_ODD             0
 250 #define TGA_DEEP_PARITY_EVEN            1
 251
 252 #define TGA_DEEP_READY_ON_8             0
 253 #define TGA_DEEP_READY_ON_2             1
 254
 255 #define TGA_DEEP_DMA_64                 0
 256 #define TGA_DEEP_DMA_128                1
 257
 258 typedef struct {
 259     unsigned s_wr_mask : 8;
 260     unsigned s_rd_mask : 8;
 261     unsigned s_test : 3;
 262     unsigned s_fail : 3;
 263     unsigned d_fail : 3;
 264     unsigned d_pass : 3;
 265     unsigned z_test : 3;
 266     unsigned z : 1;
 267 } tga_stencil_mode_reg_t;
 268
 269 #define TGA_SM_TEST_GEQ                 0x00
 270 #define TGA_SM_TEST_TRUE                0x01
 271 #define TGA_SM_TEST_FALSE               0x02
 272 #define TGA_SM_TEST_LS                  0x03
 273 #define TGA_SM_TEST_EQ                  0x04
 274 #define TGA_SM_TEST_LEQ                 0x05
 275 #define TGA_SM_TEST_GT                  0x06
 276 #define TGA_SM_TEST_NEQ                 0x07
 277
 278 #define TGA_SM_RESULT_KEEP              0x00
 279 #define TGA_SM_RESULT_ZERO              0x01
 280 #define TGA_SM_RESULT_REPLACE           0x02
 281 #define TGA_SM_RESULT_INCR              0x03
 282 #define TGA_SM_RESULT_DECR              0x04
 283 #define TGA_SM_RESULT_INV               0x05
 284
 285 #define TGA_SM_Z_REPLACE                0
 286 #define TGA_SM_Z_KEEP                   1
 287
 288 typedef struct {
 289     unsigned mode : 8;
 290     unsigned visual : 3;
 291     unsigned rotate : 2;
 292     unsigned line : 1;
 293     unsigned z16 : 1;
 294     unsigned cap_ends : 1;
 295     unsigned mbz : 16;
 296 } tga_mode_reg_t;
 297
 298 #define TGA_MODE_MODE_SIMPLE                    0x00
 299 #define TGA_MODE_MODE_Z_SIMPLE                  0x10
 300 #define TGA_MODE_MODE_OPA_STIP                  0x01
 301 #define TGA_MODE_MODE_OPA_FILL                  0x21
 302 #define TGA_MODE_MODE_TRA_STIP                  0x05
 303 #define TGA_MODE_MODE_TRA_FILL                  0x25
 304 #define TGA_MODE_MODE_TRA_BLK_STIP              0x0d
 305 #define TGA_MODE_MODE_TRA_BLK_FILL              0x2d
 306 #define TGA_MODE_MODE_OPA_LINE                  0x02
 307 #define TGA_MODE_MODE_TRA_LINE                  0x06
 308 #define TGA_MODE_MODE_CINT_TRA_LINE             0x0e
 309 #define TGA_MODE_MODE_CINT_TRA_DITH_LINE        0x2e
 310 #define TGA_MODE_MODE_Z_OPA_LINE                0x12
 311 #define TGA_MODE_MODE_Z_TRA_LINE                0x16
 312 #define TGA_MODE_MODE_Z_CINT_OPA_LINE           0x1a
 313 #define TGA_MODE_MODE_Z_SINT_OPA                0x5a
 314 #define TGA_MODE_MODE_Z_CINT_OPA_DITH_LINE      0x3a
 315 #define TGA_MODE_MODE_Z_CINT_TRA_LINE           0x1e
 316 #define TGA_MODE_MODE_Z_SINT_TRA                0x5e
 317 #define TGA_MODE_MODE_Z_CINT_TRA_DITH_LINE      0x3e
 318 #define TGA_MODE_MODE_COPY                      0x07
 319 #define TGA_MODE_MODE_COPY24                    0x307
 320 #define TGA_MODE_MODE_DMA_READ                  0x17
 321 #define TGA_MODE_MODE_DMA_READ_DITH             0x37
 322 #define TGA_MODE_MODE_DMA_WRITE                 0x1f
 323
 324 #define TGA_MODE_VISUAL_8_PACKED                0x00
 325 #define TGA_MODE_VISUAL_8_UNPACKED              0x01
 326 #define TGA_MODE_VISUAL_12_LOW                  0x02
 327 #define TGA_MODE_VISUAL_12_HIGH                 0x06
 328 #define TGA_MODE_VISUAL_24                      0x03
 329
 330 #define TGA_MODE_PM_IS_PERS                     0x00800000
 331 #define TGA_MODE_ADDR_IS_NEW                    0x00400000
 332 #define TGA_MODE_BRES3_IS_NEW                   0x00200000
 333 #define TGA_MODE_COPY_WILL_DRAIN                0x00100000
 334
 335 typedef struct {
 336     unsigned opcode : 4;
 337     unsigned mbz : 4;
 338     unsigned visual : 2;
 339     unsigned rotate : 2;
 340 } tga_raster_op_t;
 341
 342 #define TGA_ROP_OP_CLEAR                        0
 343 #define TGA_ROP_OP_AND                          1
 344 #define TGA_ROP_OP_AND_REVERSE                  2
 345 #define TGA_ROP_OP_COPY                         3
 346 #define TGA_ROP_OP_COPY24                       0x303
 347 #define TGA_ROP_OP_AND_INVERTED                 4
 348 #define TGA_ROP_OP_NOOP                         5
 349 #define TGA_ROP_OP_XOR                          6
 350 #define TGA_ROP_OP_OR                           7
 351 #define TGA_ROP_OP_NOR                          8
 352 #define TGA_ROP_OP_EQUIV                        9
 353 #define TGA_ROP_OP_INVERT                       10
 354 #define TGA_ROP_OP_OR_REVERSE                   11
 355 #define TGA_ROP_OP_COPY_INVERTED                12
 356 #define TGA_ROP_OP_OR_INVERTED                  13
 357 #define TGA_ROP_OP_NAND                         14
 358 #define TGA_ROP_OP_SET                          15
 359
 360 #define TGA_ROP_VISUAL_8_PACKED                 0x00
 361 #define TGA_ROP_VISUAL_8_UNPACKED               0x01
 362 #define TGA_ROP_VISUAL_12                       0x02
 363 #define TGA_ROP_VISUAL_24                       0x03
 364
 365 #define TGA_INTR_VSYNC                          0x00000001
 366 #define TGA_INTR_SHIFT_ADDR                     0x00000002
 367 #define TGA_INTR_TIMER                          0x00000010
 368 #define TGA_INTR_ALL                            0x00000013
 369 #define TGA_INTR_ENABLE_SHIFT                   16
 370
 371 #define TGA_RAMDAC_INTERF_WRITE_SHIFT           0
 372 #define TGA_RAMDAC_INTERF_READ0_SHIFT           16
 373 #define TGA_RAMDAC_INTERF_READ1_SHIFT           24
 374
 375 #define TGA_RAMDAC_485_READ                     0x01
 376 #define TGA_RAMDAC_485_WRITE                    0x00
 377
 378 #define TGA_RAMDAC_485_ADDR_PAL_WRITE           0x00
 379 #define TGA_RAMDAC_485_DATA_PAL                 0x02
 380 #define TGA_RAMDAC_485_PIXEL_MASK               0x04
 381 #define TGA_RAMDAC_485_ADDR_PAL_READ            0x06
 382 #define TGA_RAMDAC_485_ADDR_CUR_WRITE           0x08
 383 #define TGA_RAMDAC_485_DATA_CUR                 0x0a
 384 #define TGA_RAMDAC_485_CMD_0                    0x0c
 385 #define TGA_RAMDAC_485_ADDR_CUR_READ            0x0e
 386 #define TGA_RAMDAC_485_CMD_1                    0x10
 387 #define TGA_RAMDAC_485_CMD_2                    0x12
 388 #define TGA_RAMDAC_485_STATUS                   0x14
 389 #define TGA_RAMDAC_485_CMD_3                    0x14
 390 #define TGA_RAMDAC_485_CUR_RAM                  0x16
 391 #define TGA_RAMDAC_485_CUR_LOW_X                0x18
 392 #define TGA_RAMDAC_485_CUR_HIGH_X               0x1a
 393 #define TGA_RAMDAC_485_CUR_LOW_Y                0x1c
 394 #define TGA_RAMDAC_485_CUR_HIGH_Y               0x1e
 395
 396 #define TGA_RAMDAC_485_ADDR_EPSR_SHIFT          0
 397 #define TGA_RAMDAC_485_ADDR_EPDR_SHIFT          8
 398
 399 #define TGA_RAMDAC_463_HEAD_MASK                0x01
 400 #define TGA_RAMDAC_463_READ                     0x02
 401 #define TGA_RAMDAC_463_WRITE                    0x00
 402 #define TGA_RAMDAC_463_ADDR_LOW                 0x00
 403 #define TGA_RAMDAC_463_ADDR_HIGH                0x04
 404 #define TGA_RAMDAC_463_CMD_CURS                 0x08
 405 #define TGA_RAMDAC_463_CMD_CMAP                 0x0c
 406
 407 #define TGA_RAMDAC_463_ADDR_EPSR_SHIFT          0
 408 #define TGA_RAMDAC_463_ADDR_EPDR_SHIFT          8
 409
 410 #define TGA_RAMDAC_463_CURSOR_COLOR0            0x0100
 411 #define TGA_RAMDAC_463_CURSOR_COLOR1            0x0101
 412 #define TGA_RAMDAC_463_COMMAND_REG_0            0x0201
 413 #define TGA_RAMDAC_463_COMMAND_REG_1            0x0202
 414 #define TGA_RAMDAC_463_COMMAND_REG_2            0x0203
 415 #define TGA_RAMDAC_463_READ_MASK                0x0205
 416 #define TGA_RAMDAC_463_BLINK_MASK               0x0209
 417 #define TGA_RAMDAC_463_WINDOW_TYPE_TABLE        0x0300
 418
 419 typedef union {
 420     struct {
 421         unsigned int pixels : 9;
 422         unsigned int front_porch : 5;
 423         unsigned int sync : 7;
 424         unsigned int back_porch : 7;
 425         unsigned int ignore : 3;
 426         unsigned int odd : 1;
 427     } horizontal_setup;
 428     unsigned int h_setup;
 429 } tga_horizontal_setup_t;
 430
 431 typedef union {
 432     struct {
 433         unsigned int scan_lines : 11;
 434         unsigned int front_porch : 5;
 435         unsigned int sync : 6;
 436         unsigned int back_porch : 6;
 437     } vertical_setup;
 438     unsigned int v_setup;
 439 } tga_vertical_setup_t;
 440
 441 typedef volatile struct {
 442   tga_reg_t buffer[8];
 443
 444 tga_reg_t foreground;
 445 tga_reg_t background;
 446 tga_reg_t planemask;
 447 tga_reg_t pixelmask;
 448 tga_reg_t mode;
 449 tga_reg_t rop;
 450 tga_reg_t shift;
 451 tga_reg_t address;
 452
 453 tga_reg_t bres1;
 454 tga_reg_t bres2;
 455 tga_reg_t bres3;
 456 tga_reg_t brescont;
 457 tga_reg_t deep;
 458 tga_reg_t start;
 459 tga_reg_t stencil_mode;
 460 tga_reg_t pers_pixelmask;
 461
 462 tga_reg_t cursor_base_address;
 463 tga_reg_t horizontal_setup;
 464 tga_reg_t vertical_setup;
 465
 466 #define TGA_VERT_STEREO_EN              0x80000000
 467 tga_reg_t base_address;
 468 tga_reg_t video_valid;
 469
 470 #define TGA_VIDEO_VALID_SCANNING        0x00000001
 471 #define TGA_VIDEO_VALID_BLANK           0x00000002
 472 #define TGA_VIDEO_VALID_CURSOR_ENABLE   0x00000004
 473 tga_reg_t cursor_xy;
 474 tga_reg_t video_shift_addr;
 475 tga_reg_t intr_status;
 476
 477 tga_reg_t pixel_data;
 478 tga_reg_t red_incr;
 479 tga_reg_t green_incr;
 480 tga_reg_t blue_incr;
 481 tga_reg_t z_incr_low;
 482 tga_reg_t z_incr_high;
 483 tga_reg_t dma_address;
 484 tga_reg_t bres_width;
 485
 486 tga_reg_t z_value_low;
 487 tga_reg_t z_value_high;
 488 tga_reg_t z_base_address;
 489 tga_reg_t address2;
 490 tga_reg_t red_value;
 491 tga_reg_t green_value;
 492 tga_reg_t blue_value;
 493 tga_reg_t _jnk12;
 494
 495 tga_reg_t ramdac_setup;
 496 struct {
 497     tga_reg_t junk;
 498 } _junk[8 * 2 - 1];
 499
 500 struct {
 501     tga_reg_t data;
 502 } slope_no_go[8];
 503
 504 struct {
 505     tga_reg_t data;
 506 } slope[8];
 507
 508 tga_reg_t bm_color_0;
 509 tga_reg_t bm_color_1;
 510 tga_reg_t bm_color_2;
 511 tga_reg_t bm_color_3;
 512 tga_reg_t bm_color_4;
 513 tga_reg_t bm_color_5;
 514 tga_reg_t bm_color_6;
 515 tga_reg_t bm_color_7;
 516
 517 tga_reg_t c64_src;
 518 tga_reg_t c64_dst;
 519 tga_reg_t c64_src2;
 520 tga_reg_t c64_dst2;
 521 tga_reg_t _jnk45;
 522 tga_reg_t _jnk46;
 523 tga_reg_t _jnk47;
 524 tga_reg_t _jnk48;
 525
 526 struct {
 527     tga_reg_t junk;
 528 } _junk2[8 * 3];
 529
 530 tga_reg_t eprom_write;
 531 tga_reg_t _res0;
 532 tga_reg_t clock;
 533 tga_reg_t _res1;
 534 tga_reg_t ramdac;
 535 tga_reg_t _res2;
 536 tga_reg_t command_status;
 537 tga_reg_t command_status2;
 538
 539 }
 540  tga_rec_t, *tga_ptr_t;
 541
 542 #if 0
 543 typedef struct {
 544     ws_screen_descriptor screen;        /* MUST be first!!! */
 545     ws_depth_descriptor depth[NDEPTHS];
 546     ws_visual_descriptor visual[NVISUALS];
 547     ws_cursor_functions cf;
 548     ws_color_map_functions cmf;
 549     ws_screen_functions sf;
 550     int (*attach)();
 551     int (*bootmsg)();
 552     int (*map)();
 553     int (*interrupt)();
 554     int (*setup)();
 555     vm_offset_t base;
 556     tga_ptr_t asic;
 557     vm_offset_t fb;
 558     size_t fb_size;
 559     unsigned int bt485_present;
 560     unsigned int bits_per_pixel;
 561     unsigned int core_size;
 562     unsigned int paer_value;
 563     tga_reg_t deep;
 564     tga_reg_t head_mask;
 565     tga_reg_t refresh_count;
 566     tga_reg_t horizontal_setup;
 567     tga_reg_t vertical_setup;
 568     tga_reg_t base_address;
 569     caddr_t info_area;
 570     vm_offset_t virtual_dma_buffer;
 571     vm_offset_t physical_dma_buffer;
 572     int wt_min_dirty;
 573     int wt_max_dirty;
 574     int wt_dirty;
 575     tga_window_tag_cell_t wt_cell[16];  /* magic number */
 576     unsigned int stereo_mode;
 577     io_handle_t io_handle;
 578     dma_map_info_t p_map_info;
 579 } tga_info_t;
 580
 581 #define TGA_USER_MAPPING_COUNT          4
 582
 583 typedef struct {
 584     vm_offset_t fb_alias_increment;
 585     vm_offset_t option_base;
 586     unsigned int planemask;
 587     vm_offset_t virtual_dma_buffer;
 588     vm_offset_t physical_dma_buffer;
 589 } tga_server_info_t;
 590 #endif                                  /* 0 */
 591
 592 typedef struct {
 593     unsigned char dirty_cell;
 594     unsigned char red;                  /* only need 8 bits */
 595     unsigned char green;
 596     unsigned char blue;
 597 } tga_bt485_color_cell_t;
 598
 599 typedef struct {
 600     volatile unsigned int *setup;
 601     volatile unsigned int *data;
 602     unsigned int head_mask;
 603     short fb_xoffset;
 604     short fb_yoffset;
 605     short min_dirty;
 606     short max_dirty;
 607     caddr_t reset;
 608     u_int mask;
 609 } tga_bt485_type_t;
 610
 611 #if 0
 612 typedef struct {
 613     volatile unsigned int *setup;
 614     volatile unsigned int *data;
 615     unsigned int head_mask;
 616     short fb_xoffset;
 617     short fb_yoffset;
 618     short min_dirty;
 619     short max_dirty;
 620     caddr_t reset;
 621     u_int mask;
 622
 623     /*************************************************************** fields
 624      * above this line MUST match struct bt485type
 625      * exactly!***************************************************************/
 626     u_int unit;
 627     char screen_on;
 628     char on_off;
 629     char dirty_cursor;
 630     char dirty_colormap;
 631     short x_hot;
 632     short y_hot;
 633     ws_color_cell cursor_fg;
 634     ws_color_cell cursor_bg;
 635     void (*enable_interrupt)();
 636     u_long bits[256];
 637     tga_bt485_color_cell_t cells[256];
 638 } tga_bt485_info_t;
 639 #endif                                  /* 0 */
 640
 641 #define TGA_RAMDAC_463_WINDOW_TAG_COUNT 16
 642 #define TGA_RAMDAC_463_CMAP_ENTRY_COUNT 528
 643
 644 typedef struct {
 645     unsigned char dirty_cell;
 646     unsigned char red;
 647     unsigned char green;
 648     unsigned char blue;
 649 } tga_bt463_color_cell_t;
 650
 651 typedef struct {
 652     unsigned char low_byte;
 653     unsigned char middle_byte;
 654     unsigned char high_byte;
 655     unsigned char unused;
 656 } tga_bt463_wid_cell_t;
 657
 658 typedef struct {
 659     volatile unsigned int *setup;
 660     volatile unsigned int *data;
 661     unsigned int head_mask;
 662     short fb_xoffset;
 663     short fb_yoffset;
 664 } tga_bt463_type_t;
 665
 666 #if 0
 667 typedef struct {
 668     volatile unsigned int *setup;
 669     volatile unsigned int *data;
 670     unsigned int head_mask;
 671     short fb_xoffset;
 672     short fb_yoffset;
 673     char type;
 674     char screen_on;
 675     char dirty_colormap;
 676     char dirty_cursormap;
 677     int unit;
 678     void (*enable_interrupt)();
 679     caddr_t cursor_closure;
 680     ws_color_cell cursor_fg;
 681     ws_color_cell cursor_bg;
 682     short min_dirty;
 683     short max_dirty;
 684     tga_bt463_color_cell_t cells[TGA_RAMDAC_463_CMAP_ENTRY_COUNT];
 685 } tga_bt463_info_t;
 686 #endif                                  /* 0 */
 687
 688 typedef struct {
 689     volatile unsigned int *xy_reg;
 690     volatile unsigned int *valid;
 691     short fb_xoffset;
 692     short fb_yoffset;
 693 } tga_curs_type_t;
 694
 695 #if 0
 696 typedef struct {
 697     volatile unsigned int *xy_reg;
 698     volatile unsigned int *valid;
 699     short fb_xoffset;
 700     short fb_yoffset;
 701     u_int unit;
 702     char on_off;
 703     char dirty_cursor;
 704     char dirty_cursormap;
 705     short x_hot;
 706     short y_hot;
 707     short last_row;
 708     ws_color_cell cursor_fg;
 709     ws_color_cell cursor_bg;
 710     void (*enable_interrupt)();
 711     unsigned int bits[256];
 712 } tga_curs_info_t;
 713 #endif                                  /* 0 */
 714
 715 #endif                                  /* TGA_DEFINED */
 716