2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.270577 # Number of seconds simulated
4 sim_ticks 270576960000 # Number of ticks simulated
5 final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1675606 # Simulator instruction rate (inst/s)
8 host_tick_rate 2343719954 # Simulator tick rate (ticks/s)
9 host_mem_usage 218792 # Number of bytes of host memory used
10 host_seconds 115.45 # Real time elapsed on the host
11 sim_insts 193444769 # Number of instructions simulated
12 system.physmem.bytes_read 331072 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 5173 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 1223578 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 850804 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 1223578 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.workload.num_syscalls 401 # Number of system calls
22 system.cpu.numCycles 541153920 # number of cpu cycles simulated
23 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
24 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
25 system.cpu.num_insts 193444769 # Number of instructions executed
26 system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
27 system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
28 system.cpu.num_func_calls 1957920 # number of times a function call or return occured
29 system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls
30 system.cpu.num_int_insts 167974818 # number of integer instructions
31 system.cpu.num_fp_insts 1970372 # number of float instructions
32 system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read
33 system.cpu.num_int_register_writes 163060136 # number of times the integer registers were written
34 system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
35 system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
36 system.cpu.num_mem_refs 76733959 # number of memory refs
37 system.cpu.num_load_insts 57735092 # Number of load instructions
38 system.cpu.num_store_insts 18998867 # Number of store instructions
39 system.cpu.num_idle_cycles 0 # Number of idle cycles
40 system.cpu.num_busy_cycles 541153920 # Number of busy cycles
41 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
42 system.cpu.idle_fraction 0 # Percentage of idle cycles
43 system.cpu.icache.replacements 10362 # number of replacements
44 system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use
45 system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks.
46 system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
47 system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks.
48 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
49 system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context
50 system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy
51 system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits
52 system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits
53 system.cpu.icache.overall_hits 193433261 # number of overall hits
54 system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses
55 system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses
56 system.cpu.icache.overall_misses 12288 # number of overall misses
57 system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles
58 system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles
59 system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles
60 system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses)
61 system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses
62 system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses
63 system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses
64 system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses
65 system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses
66 system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
67 system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency
68 system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
69 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
70 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
71 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
72 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
73 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
74 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
75 system.cpu.icache.fast_writes 0 # number of fast writes performed
76 system.cpu.icache.cache_copies 0 # number of cache copies performed
77 system.cpu.icache.writebacks 0 # number of writebacks
78 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
79 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
80 system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses
81 system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses
82 system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses
83 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
84 system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles
85 system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles
86 system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles
87 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
88 system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
89 system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
90 system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
91 system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
92 system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
93 system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
94 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
95 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
96 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
97 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
98 system.cpu.dcache.replacements 2 # number of replacements
99 system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use
100 system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
101 system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
102 system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
103 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
104 system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context
105 system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy
106 system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits
107 system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits
108 system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits
109 system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits
110 system.cpu.dcache.overall_hits 76709933 # number of overall hits
111 system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
112 system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses
113 system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses
114 system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses
115 system.cpu.dcache.overall_misses 1575 # number of overall misses
116 system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles
117 system.cpu.dcache.WriteReq_miss_latency 60312000 # number of WriteReq miss cycles
118 system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles
119 system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles
120 system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles
121 system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
122 system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
123 system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
124 system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
125 system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
126 system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
127 system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses
128 system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses
129 system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
130 system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
131 system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
132 system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
133 system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
134 system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
135 system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
136 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
137 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
138 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
139 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
140 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
141 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
142 system.cpu.dcache.fast_writes 0 # number of fast writes performed
143 system.cpu.dcache.cache_copies 0 # number of cache copies performed
144 system.cpu.dcache.writebacks 2 # number of writebacks
145 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
146 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
147 system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
148 system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses
149 system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
150 system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses
151 system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses
152 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
153 system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles
154 system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles
155 system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles
156 system.cpu.dcache.demand_mshr_miss_latency 83475000 # number of demand (read+write) MSHR miss cycles
157 system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles
158 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
159 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
160 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses
161 system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses
162 system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
163 system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
164 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
165 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
166 system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
167 system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
168 system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
169 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
170 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
171 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
172 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
173 system.cpu.l2cache.replacements 0 # number of replacements
174 system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use
175 system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
176 system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks.
177 system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks.
178 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
179 system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context
180 system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context
181 system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy
182 system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy
183 system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits
184 system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
185 system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits
186 system.cpu.l2cache.overall_hits 8691 # number of overall hits
187 system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses
188 system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses
189 system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses
190 system.cpu.l2cache.overall_misses 5173 # number of overall misses
191 system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles
192 system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles
193 system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles
194 system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles
195 system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses)
196 system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
197 system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses)
198 system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses
199 system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
200 system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses
201 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
202 system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses
203 system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses
204 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
205 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
206 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
207 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
208 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
209 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
210 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
211 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
212 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
213 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
214 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
215 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
216 system.cpu.l2cache.writebacks 0 # number of writebacks
217 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
218 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
219 system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
220 system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses
221 system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses
222 system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses
223 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
224 system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
225 system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles
226 system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles
227 system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles
228 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
229 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
230 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
231 system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses
232 system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses
233 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
234 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
235 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
236 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
237 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
238 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
239 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
240 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
242 ---------- End Simulation Statistics ----------
projects / gem5.git / blob