tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu0]
 114 type=MinorCPU
 115 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=system.cpu0.branchPred
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 decodeCycleInput=true
 121 decodeInputBufferSize=3
 122 decodeInputWidth=2
 123 decodeToExecuteForwardDelay=1
 124 default_p_state=UNDEFINED
 125 do_checkpoint_insts=true
 126 do_quiesce=true
 127 do_statistics_insts=true
 128 dstage2_mmu=system.cpu0.dstage2_mmu
 129 dtb=system.cpu0.dtb
 130 enableIdling=true
 131 eventq_index=0
 132 executeAllowEarlyMemoryIssue=true
 133 executeBranchDelay=1
 134 executeCommitLimit=2
 135 executeCycleInput=true
 136 executeFuncUnits=system.cpu0.executeFuncUnits
 137 executeInputBufferSize=7
 138 executeInputWidth=2
 139 executeIssueLimit=2
 140 executeLSQMaxStoreBufferStoresPerCycle=2
 141 executeLSQRequestsQueueSize=1
 142 executeLSQStoreBufferSize=5
 143 executeLSQTransfersQueueSize=2
 144 executeMaxAccessesInMemory=2
 145 executeMemoryCommitLimit=1
 146 executeMemoryIssueLimit=1
 147 executeMemoryWidth=0
 148 executeSetTraceTimeOnCommit=true
 149 executeSetTraceTimeOnIssue=false
 150 fetch1FetchLimit=1
 151 fetch1LineSnapWidth=0
 152 fetch1LineWidth=0
 153 fetch1ToFetch2BackwardDelay=1
 154 fetch1ToFetch2ForwardDelay=1
 155 fetch2CycleInput=true
 156 fetch2InputBufferSize=2
 157 fetch2ToDecodeForwardDelay=1
 158 function_trace=false
 159 function_trace_start=0
 160 interrupts=system.cpu0.interrupts
 161 isa=system.cpu0.isa
 162 istage2_mmu=system.cpu0.istage2_mmu
 163 itb=system.cpu0.itb
 164 max_insts_all_threads=0
 165 max_insts_any_thread=0
 166 max_loads_all_threads=0
 167 max_loads_any_thread=0
 168 numThreads=1
 169 p_state_clk_gate_bins=20
 170 p_state_clk_gate_max=1000000000000
 171 p_state_clk_gate_min=1000
 172 power_model=Null
 173 profile=0
 174 progress_interval=0
 175 simpoint_start_insts=
 176 socket_id=0
 177 switched_out=false
 178 syscallRetryLatency=10000
 179 system=system
 180 threadPolicy=RoundRobin
 181 tracer=system.cpu0.tracer
 182 workload=
 183 dcache_port=system.cpu0.dcache.cpu_side
 184 icache_port=system.cpu0.icache.cpu_side
 185
 186 [system.cpu0.branchPred]
 187 type=TournamentBP
 188 BTBEntries=4096
 189 BTBTagSize=16
 190 RASSize=16
 191 choiceCtrBits=2
 192 choicePredictorSize=8192
 193 eventq_index=0
 194 globalCtrBits=2
 195 globalPredictorSize=8192
 196 indirectHashGHR=true
 197 indirectHashTargets=true
 198 indirectPathLength=3
 199 indirectSets=256
 200 indirectTagSize=16
 201 indirectWays=2
 202 instShiftAmt=2
 203 localCtrBits=2
 204 localHistoryTableSize=2048
 205 localPredictorSize=2048
 206 numThreads=1
 207 useIndirect=true
 208
 209 [system.cpu0.dcache]
 210 type=Cache
 211 children=tags
 212 addr_ranges=0:18446744073709551615:0:0:0:0
 213 assoc=2
 214 clk_domain=system.cpu_clk_domain
 215 clusivity=mostly_incl
 216 data_latency=2
 217 default_p_state=UNDEFINED
 218 demand_mshr_reserve=1
 219 eventq_index=0
 220 is_read_only=false
 221 max_miss_count=0
 222 mshrs=6
 223 p_state_clk_gate_bins=20
 224 p_state_clk_gate_max=1000000000000
 225 p_state_clk_gate_min=1000
 226 power_model=Null
 227 prefetch_on_access=false
 228 prefetcher=Null
 229 response_latency=2
 230 sequential_access=false
 231 size=32768
 232 system=system
 233 tag_latency=2
 234 tags=system.cpu0.dcache.tags
 235 tgts_per_mshr=8
 236 write_buffers=16
 237 writeback_clean=true
 238 cpu_side=system.cpu0.dcache_port
 239 mem_side=system.cpu0.toL2Bus.slave[1]
 240
 241 [system.cpu0.dcache.tags]
 242 type=LRU
 243 assoc=2
 244 block_size=64
 245 clk_domain=system.cpu_clk_domain
 246 data_latency=2
 247 default_p_state=UNDEFINED
 248 eventq_index=0
 249 p_state_clk_gate_bins=20
 250 p_state_clk_gate_max=1000000000000
 251 p_state_clk_gate_min=1000
 252 power_model=Null
 253 sequential_access=false
 254 size=32768
 255 tag_latency=2
 256
 257 [system.cpu0.dstage2_mmu]
 258 type=ArmStage2MMU
 259 children=stage2_tlb
 260 eventq_index=0
 261 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 262 sys=system
 263 tlb=system.cpu0.dtb
 264
 265 [system.cpu0.dstage2_mmu.stage2_tlb]
 266 type=ArmTLB
 267 children=walker
 268 eventq_index=0
 269 is_stage2=true
 270 size=32
 271 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 272
 273 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 274 type=ArmTableWalker
 275 clk_domain=system.cpu_clk_domain
 276 default_p_state=UNDEFINED
 277 eventq_index=0
 278 is_stage2=true
 279 num_squash_per_cycle=2
 280 p_state_clk_gate_bins=20
 281 p_state_clk_gate_max=1000000000000
 282 p_state_clk_gate_min=1000
 283 power_model=Null
 284 sys=system
 285
 286 [system.cpu0.dtb]
 287 type=ArmTLB
 288 children=walker
 289 eventq_index=0
 290 is_stage2=false
 291 size=64
 292 walker=system.cpu0.dtb.walker
 293
 294 [system.cpu0.dtb.walker]
 295 type=ArmTableWalker
 296 clk_domain=system.cpu_clk_domain
 297 default_p_state=UNDEFINED
 298 eventq_index=0
 299 is_stage2=false
 300 num_squash_per_cycle=2
 301 p_state_clk_gate_bins=20
 302 p_state_clk_gate_max=1000000000000
 303 p_state_clk_gate_min=1000
 304 power_model=Null
 305 sys=system
 306 port=system.cpu0.toL2Bus.slave[3]
 307
 308 [system.cpu0.executeFuncUnits]
 309 type=MinorFUPool
 310 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 311 eventq_index=0
 312 funcUnits=system.cpu0.executeFuncUnits.funcUnits0 system.cpu0.executeFuncUnits.funcUnits1 system.cpu0.executeFuncUnits.funcUnits2 system.cpu0.executeFuncUnits.funcUnits3 system.cpu0.executeFuncUnits.funcUnits4 system.cpu0.executeFuncUnits.funcUnits5 system.cpu0.executeFuncUnits.funcUnits6
 313
 314 [system.cpu0.executeFuncUnits.funcUnits0]
 315 type=MinorFU
 316 children=opClasses timings
 317 cantForwardFromFUIndices=
 318 eventq_index=0
 319 issueLat=1
 320 opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses
 321 opLat=3
 322 timings=system.cpu0.executeFuncUnits.funcUnits0.timings
 323
 324 [system.cpu0.executeFuncUnits.funcUnits0.opClasses]
 325 type=MinorOpClassSet
 326 children=opClasses
 327 eventq_index=0
 328 opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses
 329
 330 [system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses]
 331 type=MinorOpClass
 332 eventq_index=0
 333 opClass=IntAlu
 334
 335 [system.cpu0.executeFuncUnits.funcUnits0.timings]
 336 type=MinorFUTiming
 337 children=opClasses
 338 description=Int
 339 eventq_index=0
 340 extraAssumedLat=0
 341 extraCommitLat=0
 342 extraCommitLatExpr=Null
 343 mask=0
 344 match=0
 345 opClasses=system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses
 346 srcRegsRelativeLats=2
 347 suppress=false
 348
 349 [system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses]
 350 type=MinorOpClassSet
 351 eventq_index=0
 352 opClasses=
 353
 354 [system.cpu0.executeFuncUnits.funcUnits1]
 355 type=MinorFU
 356 children=opClasses timings
 357 cantForwardFromFUIndices=
 358 eventq_index=0
 359 issueLat=1
 360 opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses
 361 opLat=3
 362 timings=system.cpu0.executeFuncUnits.funcUnits1.timings
 363
 364 [system.cpu0.executeFuncUnits.funcUnits1.opClasses]
 365 type=MinorOpClassSet
 366 children=opClasses
 367 eventq_index=0
 368 opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses
 369
 370 [system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses]
 371 type=MinorOpClass
 372 eventq_index=0
 373 opClass=IntAlu
 374
 375 [system.cpu0.executeFuncUnits.funcUnits1.timings]
 376 type=MinorFUTiming
 377 children=opClasses
 378 description=Int
 379 eventq_index=0
 380 extraAssumedLat=0
 381 extraCommitLat=0
 382 extraCommitLatExpr=Null
 383 mask=0
 384 match=0
 385 opClasses=system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses
 386 srcRegsRelativeLats=2
 387 suppress=false
 388
 389 [system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses]
 390 type=MinorOpClassSet
 391 eventq_index=0
 392 opClasses=
 393
 394 [system.cpu0.executeFuncUnits.funcUnits2]
 395 type=MinorFU
 396 children=opClasses timings
 397 cantForwardFromFUIndices=
 398 eventq_index=0
 399 issueLat=1
 400 opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses
 401 opLat=3
 402 timings=system.cpu0.executeFuncUnits.funcUnits2.timings
 403
 404 [system.cpu0.executeFuncUnits.funcUnits2.opClasses]
 405 type=MinorOpClassSet
 406 children=opClasses
 407 eventq_index=0
 408 opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses
 409
 410 [system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses]
 411 type=MinorOpClass
 412 eventq_index=0
 413 opClass=IntMult
 414
 415 [system.cpu0.executeFuncUnits.funcUnits2.timings]
 416 type=MinorFUTiming
 417 children=opClasses
 418 description=Mul
 419 eventq_index=0
 420 extraAssumedLat=0
 421 extraCommitLat=0
 422 extraCommitLatExpr=Null
 423 mask=0
 424 match=0
 425 opClasses=system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses
 426 srcRegsRelativeLats=0
 427 suppress=false
 428
 429 [system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses]
 430 type=MinorOpClassSet
 431 eventq_index=0
 432 opClasses=
 433
 434 [system.cpu0.executeFuncUnits.funcUnits3]
 435 type=MinorFU
 436 children=opClasses
 437 cantForwardFromFUIndices=
 438 eventq_index=0
 439 issueLat=9
 440 opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses
 441 opLat=9
 442 timings=
 443
 444 [system.cpu0.executeFuncUnits.funcUnits3.opClasses]
 445 type=MinorOpClassSet
 446 children=opClasses
 447 eventq_index=0
 448 opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses
 449
 450 [system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses]
 451 type=MinorOpClass
 452 eventq_index=0
 453 opClass=IntDiv
 454
 455 [system.cpu0.executeFuncUnits.funcUnits4]
 456 type=MinorFU
 457 children=opClasses timings
 458 cantForwardFromFUIndices=
 459 eventq_index=0
 460 issueLat=1
 461 opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses
 462 opLat=6
 463 timings=system.cpu0.executeFuncUnits.funcUnits4.timings
 464
 465 [system.cpu0.executeFuncUnits.funcUnits4.opClasses]
 466 type=MinorOpClassSet
 467 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
 468 eventq_index=0
 469 opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses27
 470
 471 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 472 type=MinorOpClass
 473 eventq_index=0
 474 opClass=FloatAdd
 475
 476 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 477 type=MinorOpClass
 478 eventq_index=0
 479 opClass=FloatCmp
 480
 481 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 482 type=MinorOpClass
 483 eventq_index=0
 484 opClass=FloatCvt
 485
 486 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 487 type=MinorOpClass
 488 eventq_index=0
 489 opClass=FloatMisc
 490
 491 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 492 type=MinorOpClass
 493 eventq_index=0
 494 opClass=FloatMult
 495
 496 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 497 type=MinorOpClass
 498 eventq_index=0
 499 opClass=FloatMultAcc
 500
 501 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 502 type=MinorOpClass
 503 eventq_index=0
 504 opClass=FloatDiv
 505
 506 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 507 type=MinorOpClass
 508 eventq_index=0
 509 opClass=FloatSqrt
 510
 511 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 512 type=MinorOpClass
 513 eventq_index=0
 514 opClass=SimdAdd
 515
 516 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 517 type=MinorOpClass
 518 eventq_index=0
 519 opClass=SimdAddAcc
 520
 521 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 522 type=MinorOpClass
 523 eventq_index=0
 524 opClass=SimdAlu
 525
 526 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 527 type=MinorOpClass
 528 eventq_index=0
 529 opClass=SimdCmp
 530
 531 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 532 type=MinorOpClass
 533 eventq_index=0
 534 opClass=SimdCvt
 535
 536 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 537 type=MinorOpClass
 538 eventq_index=0
 539 opClass=SimdMisc
 540
 541 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 542 type=MinorOpClass
 543 eventq_index=0
 544 opClass=SimdMult
 545
 546 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 547 type=MinorOpClass
 548 eventq_index=0
 549 opClass=SimdMultAcc
 550
 551 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 552 type=MinorOpClass
 553 eventq_index=0
 554 opClass=SimdShift
 555
 556 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 557 type=MinorOpClass
 558 eventq_index=0
 559 opClass=SimdShiftAcc
 560
 561 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 562 type=MinorOpClass
 563 eventq_index=0
 564 opClass=SimdSqrt
 565
 566 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 567 type=MinorOpClass
 568 eventq_index=0
 569 opClass=SimdFloatAdd
 570
 571 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 572 type=MinorOpClass
 573 eventq_index=0
 574 opClass=SimdFloatAlu
 575
 576 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 577 type=MinorOpClass
 578 eventq_index=0
 579 opClass=SimdFloatCmp
 580
 581 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 582 type=MinorOpClass
 583 eventq_index=0
 584 opClass=SimdFloatCvt
 585
 586 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 587 type=MinorOpClass
 588 eventq_index=0
 589 opClass=SimdFloatDiv
 590
 591 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 592 type=MinorOpClass
 593 eventq_index=0
 594 opClass=SimdFloatMisc
 595
 596 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 597 type=MinorOpClass
 598 eventq_index=0
 599 opClass=SimdFloatMult
 600
 601 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses26]
 602 type=MinorOpClass
 603 eventq_index=0
 604 opClass=SimdFloatMultAcc
 605
 606 [system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses27]
 607 type=MinorOpClass
 608 eventq_index=0
 609 opClass=SimdFloatSqrt
 610
 611 [system.cpu0.executeFuncUnits.funcUnits4.timings]
 612 type=MinorFUTiming
 613 children=opClasses
 614 description=FloatSimd
 615 eventq_index=0
 616 extraAssumedLat=0
 617 extraCommitLat=0
 618 extraCommitLatExpr=Null
 619 mask=0
 620 match=0
 621 opClasses=system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses
 622 srcRegsRelativeLats=2
 623 suppress=false
 624
 625 [system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses]
 626 type=MinorOpClassSet
 627 eventq_index=0
 628 opClasses=
 629
 630 [system.cpu0.executeFuncUnits.funcUnits5]
 631 type=MinorFU
 632 children=opClasses timings
 633 cantForwardFromFUIndices=
 634 eventq_index=0
 635 issueLat=1
 636 opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses
 637 opLat=1
 638 timings=system.cpu0.executeFuncUnits.funcUnits5.timings
 639
 640 [system.cpu0.executeFuncUnits.funcUnits5.opClasses]
 641 type=MinorOpClassSet
 642 children=opClasses0 opClasses1 opClasses2 opClasses3
 643 eventq_index=0
 644 opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3
 645
 646 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 647 type=MinorOpClass
 648 eventq_index=0
 649 opClass=MemRead
 650
 651 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 652 type=MinorOpClass
 653 eventq_index=0
 654 opClass=MemWrite
 655
 656 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2]
 657 type=MinorOpClass
 658 eventq_index=0
 659 opClass=FloatMemRead
 660
 661 [system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3]
 662 type=MinorOpClass
 663 eventq_index=0
 664 opClass=FloatMemWrite
 665
 666 [system.cpu0.executeFuncUnits.funcUnits5.timings]
 667 type=MinorFUTiming
 668 children=opClasses
 669 description=Mem
 670 eventq_index=0
 671 extraAssumedLat=2
 672 extraCommitLat=0
 673 extraCommitLatExpr=Null
 674 mask=0
 675 match=0
 676 opClasses=system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses
 677 srcRegsRelativeLats=1
 678 suppress=false
 679
 680 [system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses]
 681 type=MinorOpClassSet
 682 eventq_index=0
 683 opClasses=
 684
 685 [system.cpu0.executeFuncUnits.funcUnits6]
 686 type=MinorFU
 687 children=opClasses
 688 cantForwardFromFUIndices=
 689 eventq_index=0
 690 issueLat=1
 691 opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses
 692 opLat=1
 693 timings=
 694
 695 [system.cpu0.executeFuncUnits.funcUnits6.opClasses]
 696 type=MinorOpClassSet
 697 children=opClasses0 opClasses1
 698 eventq_index=0
 699 opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1
 700
 701 [system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 702 type=MinorOpClass
 703 eventq_index=0
 704 opClass=IprAccess
 705
 706 [system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 707 type=MinorOpClass
 708 eventq_index=0
 709 opClass=InstPrefetch
 710
 711 [system.cpu0.icache]
 712 type=Cache
 713 children=tags
 714 addr_ranges=0:18446744073709551615:0:0:0:0
 715 assoc=2
 716 clk_domain=system.cpu_clk_domain
 717 clusivity=mostly_incl
 718 data_latency=1
 719 default_p_state=UNDEFINED
 720 demand_mshr_reserve=1
 721 eventq_index=0
 722 is_read_only=true
 723 max_miss_count=0
 724 mshrs=2
 725 p_state_clk_gate_bins=20
 726 p_state_clk_gate_max=1000000000000
 727 p_state_clk_gate_min=1000
 728 power_model=Null
 729 prefetch_on_access=false
 730 prefetcher=Null
 731 response_latency=1
 732 sequential_access=false
 733 size=32768
 734 system=system
 735 tag_latency=1
 736 tags=system.cpu0.icache.tags
 737 tgts_per_mshr=8
 738 write_buffers=8
 739 writeback_clean=true
 740 cpu_side=system.cpu0.icache_port
 741 mem_side=system.cpu0.toL2Bus.slave[0]
 742
 743 [system.cpu0.icache.tags]
 744 type=LRU
 745 assoc=2
 746 block_size=64
 747 clk_domain=system.cpu_clk_domain
 748 data_latency=1
 749 default_p_state=UNDEFINED
 750 eventq_index=0
 751 p_state_clk_gate_bins=20
 752 p_state_clk_gate_max=1000000000000
 753 p_state_clk_gate_min=1000
 754 power_model=Null
 755 sequential_access=false
 756 size=32768
 757 tag_latency=1
 758
 759 [system.cpu0.interrupts]
 760 type=ArmInterrupts
 761 eventq_index=0
 762
 763 [system.cpu0.isa]
 764 type=ArmISA
 765 decoderFlavour=Generic
 766 eventq_index=0
 767 fpsid=1090793632
 768 id_aa64afr0_el1=0
 769 id_aa64afr1_el1=0
 770 id_aa64dfr0_el1=1052678
 771 id_aa64dfr1_el1=0
 772 id_aa64isar0_el1=0
 773 id_aa64isar1_el1=0
 774 id_aa64mmfr0_el1=15728642
 775 id_aa64mmfr1_el1=0
 776 id_isar0=34607377
 777 id_isar1=34677009
 778 id_isar2=555950401
 779 id_isar3=17899825
 780 id_isar4=268501314
 781 id_isar5=0
 782 id_mmfr0=270536963
 783 id_mmfr1=0
 784 id_mmfr2=19070976
 785 id_mmfr3=34611729
 786 midr=1091551472
 787 pmu=Null
 788 system=system
 789
 790 [system.cpu0.istage2_mmu]
 791 type=ArmStage2MMU
 792 children=stage2_tlb
 793 eventq_index=0
 794 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 795 sys=system
 796 tlb=system.cpu0.itb
 797
 798 [system.cpu0.istage2_mmu.stage2_tlb]
 799 type=ArmTLB
 800 children=walker
 801 eventq_index=0
 802 is_stage2=true
 803 size=32
 804 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 805
 806 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 807 type=ArmTableWalker
 808 clk_domain=system.cpu_clk_domain
 809 default_p_state=UNDEFINED
 810 eventq_index=0
 811 is_stage2=true
 812 num_squash_per_cycle=2
 813 p_state_clk_gate_bins=20
 814 p_state_clk_gate_max=1000000000000
 815 p_state_clk_gate_min=1000
 816 power_model=Null
 817 sys=system
 818
 819 [system.cpu0.itb]
 820 type=ArmTLB
 821 children=walker
 822 eventq_index=0
 823 is_stage2=false
 824 size=64
 825 walker=system.cpu0.itb.walker
 826
 827 [system.cpu0.itb.walker]
 828 type=ArmTableWalker
 829 clk_domain=system.cpu_clk_domain
 830 default_p_state=UNDEFINED
 831 eventq_index=0
 832 is_stage2=false
 833 num_squash_per_cycle=2
 834 p_state_clk_gate_bins=20
 835 p_state_clk_gate_max=1000000000000
 836 p_state_clk_gate_min=1000
 837 power_model=Null
 838 sys=system
 839 port=system.cpu0.toL2Bus.slave[2]
 840
 841 [system.cpu0.l2cache]
 842 type=Cache
 843 children=prefetcher tags
 844 addr_ranges=0:18446744073709551615:0:0:0:0
 845 assoc=16
 846 clk_domain=system.cpu_clk_domain
 847 clusivity=mostly_excl
 848 data_latency=12
 849 default_p_state=UNDEFINED
 850 demand_mshr_reserve=1
 851 eventq_index=0
 852 is_read_only=false
 853 max_miss_count=0
 854 mshrs=16
 855 p_state_clk_gate_bins=20
 856 p_state_clk_gate_max=1000000000000
 857 p_state_clk_gate_min=1000
 858 power_model=Null
 859 prefetch_on_access=true
 860 prefetcher=system.cpu0.l2cache.prefetcher
 861 response_latency=12
 862 sequential_access=false
 863 size=1048576
 864 system=system
 865 tag_latency=12
 866 tags=system.cpu0.l2cache.tags
 867 tgts_per_mshr=8
 868 write_buffers=8
 869 writeback_clean=false
 870 cpu_side=system.cpu0.toL2Bus.master[0]
 871 mem_side=system.toL2Bus.slave[0]
 872
 873 [system.cpu0.l2cache.prefetcher]
 874 type=StridePrefetcher
 875 cache_snoop=false
 876 clk_domain=system.cpu_clk_domain
 877 default_p_state=UNDEFINED
 878 degree=8
 879 eventq_index=0
 880 latency=1
 881 max_conf=7
 882 min_conf=0
 883 on_data=true
 884 on_inst=true
 885 on_miss=false
 886 on_read=true
 887 on_write=true
 888 p_state_clk_gate_bins=20
 889 p_state_clk_gate_max=1000000000000
 890 p_state_clk_gate_min=1000
 891 power_model=Null
 892 queue_filter=true
 893 queue_size=32
 894 queue_squash=true
 895 start_conf=4
 896 sys=system
 897 table_assoc=4
 898 table_sets=16
 899 tag_prefetch=true
 900 thresh_conf=4
 901 use_master_id=true
 902
 903 [system.cpu0.l2cache.tags]
 904 type=RandomRepl
 905 assoc=16
 906 block_size=64
 907 clk_domain=system.cpu_clk_domain
 908 data_latency=12
 909 default_p_state=UNDEFINED
 910 eventq_index=0
 911 p_state_clk_gate_bins=20
 912 p_state_clk_gate_max=1000000000000
 913 p_state_clk_gate_min=1000
 914 power_model=Null
 915 sequential_access=false
 916 size=1048576
 917 tag_latency=12
 918
 919 [system.cpu0.toL2Bus]
 920 type=CoherentXBar
 921 children=snoop_filter
 922 clk_domain=system.cpu_clk_domain
 923 default_p_state=UNDEFINED
 924 eventq_index=0
 925 forward_latency=0
 926 frontend_latency=1
 927 p_state_clk_gate_bins=20
 928 p_state_clk_gate_max=1000000000000
 929 p_state_clk_gate_min=1000
 930 point_of_coherency=false
 931 power_model=Null
 932 response_latency=1
 933 snoop_filter=system.cpu0.toL2Bus.snoop_filter
 934 snoop_response_latency=1
 935 system=system
 936 use_default_range=false
 937 width=32
 938 master=system.cpu0.l2cache.cpu_side
 939 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 940
 941 [system.cpu0.toL2Bus.snoop_filter]
 942 type=SnoopFilter
 943 eventq_index=0
 944 lookup_latency=0
 945 max_capacity=8388608
 946 system=system
 947
 948 [system.cpu0.tracer]
 949 type=ExeTracer
 950 eventq_index=0
 951
 952 [system.cpu1]
 953 type=MinorCPU
 954 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 955 branchPred=system.cpu1.branchPred
 956 checker=Null
 957 clk_domain=system.cpu_clk_domain
 958 cpu_id=1
 959 decodeCycleInput=true
 960 decodeInputBufferSize=3
 961 decodeInputWidth=2
 962 decodeToExecuteForwardDelay=1
 963 default_p_state=UNDEFINED
 964 do_checkpoint_insts=true
 965 do_quiesce=true
 966 do_statistics_insts=true
 967 dstage2_mmu=system.cpu1.dstage2_mmu
 968 dtb=system.cpu1.dtb
 969 enableIdling=true
 970 eventq_index=0
 971 executeAllowEarlyMemoryIssue=true
 972 executeBranchDelay=1
 973 executeCommitLimit=2
 974 executeCycleInput=true
 975 executeFuncUnits=system.cpu1.executeFuncUnits
 976 executeInputBufferSize=7
 977 executeInputWidth=2
 978 executeIssueLimit=2
 979 executeLSQMaxStoreBufferStoresPerCycle=2
 980 executeLSQRequestsQueueSize=1
 981 executeLSQStoreBufferSize=5
 982 executeLSQTransfersQueueSize=2
 983 executeMaxAccessesInMemory=2
 984 executeMemoryCommitLimit=1
 985 executeMemoryIssueLimit=1
 986 executeMemoryWidth=0
 987 executeSetTraceTimeOnCommit=true
 988 executeSetTraceTimeOnIssue=false
 989 fetch1FetchLimit=1
 990 fetch1LineSnapWidth=0
 991 fetch1LineWidth=0
 992 fetch1ToFetch2BackwardDelay=1
 993 fetch1ToFetch2ForwardDelay=1
 994 fetch2CycleInput=true
 995 fetch2InputBufferSize=2
 996 fetch2ToDecodeForwardDelay=1
 997 function_trace=false
 998 function_trace_start=0
 999 interrupts=system.cpu1.interrupts
1000 isa=system.cpu1.isa
1001 istage2_mmu=system.cpu1.istage2_mmu
1002 itb=system.cpu1.itb
1003 max_insts_all_threads=0
1004 max_insts_any_thread=0
1005 max_loads_all_threads=0
1006 max_loads_any_thread=0
1007 numThreads=1
1008 p_state_clk_gate_bins=20
1009 p_state_clk_gate_max=1000000000000
1010 p_state_clk_gate_min=1000
1011 power_model=Null
1012 profile=0
1013 progress_interval=0
1014 simpoint_start_insts=
1015 socket_id=0
1016 switched_out=false
1017 syscallRetryLatency=10000
1018 system=system
1019 threadPolicy=RoundRobin
1020 tracer=system.cpu1.tracer
1021 workload=
1022 dcache_port=system.cpu1.dcache.cpu_side
1023 icache_port=system.cpu1.icache.cpu_side
1024
1025 [system.cpu1.branchPred]
1026 type=TournamentBP
1027 BTBEntries=4096
1028 BTBTagSize=16
1029 RASSize=16
1030 choiceCtrBits=2
1031 choicePredictorSize=8192
1032 eventq_index=0
1033 globalCtrBits=2
1034 globalPredictorSize=8192
1035 indirectHashGHR=true
1036 indirectHashTargets=true
1037 indirectPathLength=3
1038 indirectSets=256
1039 indirectTagSize=16
1040 indirectWays=2
1041 instShiftAmt=2
1042 localCtrBits=2
1043 localHistoryTableSize=2048
1044 localPredictorSize=2048
1045 numThreads=1
1046 useIndirect=true
1047
1048 [system.cpu1.dcache]
1049 type=Cache
1050 children=tags
1051 addr_ranges=0:18446744073709551615:0:0:0:0
1052 assoc=2
1053 clk_domain=system.cpu_clk_domain
1054 clusivity=mostly_incl
1055 data_latency=2
1056 default_p_state=UNDEFINED
1057 demand_mshr_reserve=1
1058 eventq_index=0
1059 is_read_only=false
1060 max_miss_count=0
1061 mshrs=6
1062 p_state_clk_gate_bins=20
1063 p_state_clk_gate_max=1000000000000
1064 p_state_clk_gate_min=1000
1065 power_model=Null
1066 prefetch_on_access=false
1067 prefetcher=Null
1068 response_latency=2
1069 sequential_access=false
1070 size=32768
1071 system=system
1072 tag_latency=2
1073 tags=system.cpu1.dcache.tags
1074 tgts_per_mshr=8
1075 write_buffers=16
1076 writeback_clean=true
1077 cpu_side=system.cpu1.dcache_port
1078 mem_side=system.cpu1.toL2Bus.slave[1]
1079
1080 [system.cpu1.dcache.tags]
1081 type=LRU
1082 assoc=2
1083 block_size=64
1084 clk_domain=system.cpu_clk_domain
1085 data_latency=2
1086 default_p_state=UNDEFINED
1087 eventq_index=0
1088 p_state_clk_gate_bins=20
1089 p_state_clk_gate_max=1000000000000
1090 p_state_clk_gate_min=1000
1091 power_model=Null
1092 sequential_access=false
1093 size=32768
1094 tag_latency=2
1095
1096 [system.cpu1.dstage2_mmu]
1097 type=ArmStage2MMU
1098 children=stage2_tlb
1099 eventq_index=0
1100 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
1101 sys=system
1102 tlb=system.cpu1.dtb
1103
1104 [system.cpu1.dstage2_mmu.stage2_tlb]
1105 type=ArmTLB
1106 children=walker
1107 eventq_index=0
1108 is_stage2=true
1109 size=32
1110 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
1111
1112 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
1113 type=ArmTableWalker
1114 clk_domain=system.cpu_clk_domain
1115 default_p_state=UNDEFINED
1116 eventq_index=0
1117 is_stage2=true
1118 num_squash_per_cycle=2
1119 p_state_clk_gate_bins=20
1120 p_state_clk_gate_max=1000000000000
1121 p_state_clk_gate_min=1000
1122 power_model=Null
1123 sys=system
1124
1125 [system.cpu1.dtb]
1126 type=ArmTLB
1127 children=walker
1128 eventq_index=0
1129 is_stage2=false
1130 size=64
1131 walker=system.cpu1.dtb.walker
1132
1133 [system.cpu1.dtb.walker]
1134 type=ArmTableWalker
1135 clk_domain=system.cpu_clk_domain
1136 default_p_state=UNDEFINED
1137 eventq_index=0
1138 is_stage2=false
1139 num_squash_per_cycle=2
1140 p_state_clk_gate_bins=20
1141 p_state_clk_gate_max=1000000000000
1142 p_state_clk_gate_min=1000
1143 power_model=Null
1144 sys=system
1145 port=system.cpu1.toL2Bus.slave[3]
1146
1147 [system.cpu1.executeFuncUnits]
1148 type=MinorFUPool
1149 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
1150 eventq_index=0
1151 funcUnits=system.cpu1.executeFuncUnits.funcUnits0 system.cpu1.executeFuncUnits.funcUnits1 system.cpu1.executeFuncUnits.funcUnits2 system.cpu1.executeFuncUnits.funcUnits3 system.cpu1.executeFuncUnits.funcUnits4 system.cpu1.executeFuncUnits.funcUnits5 system.cpu1.executeFuncUnits.funcUnits6
1152
1153 [system.cpu1.executeFuncUnits.funcUnits0]
1154 type=MinorFU
1155 children=opClasses timings
1156 cantForwardFromFUIndices=
1157 eventq_index=0
1158 issueLat=1
1159 opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses
1160 opLat=3
1161 timings=system.cpu1.executeFuncUnits.funcUnits0.timings
1162
1163 [system.cpu1.executeFuncUnits.funcUnits0.opClasses]
1164 type=MinorOpClassSet
1165 children=opClasses
1166 eventq_index=0
1167 opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses
1168
1169 [system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses]
1170 type=MinorOpClass
1171 eventq_index=0
1172 opClass=IntAlu
1173
1174 [system.cpu1.executeFuncUnits.funcUnits0.timings]
1175 type=MinorFUTiming
1176 children=opClasses
1177 description=Int
1178 eventq_index=0
1179 extraAssumedLat=0
1180 extraCommitLat=0
1181 extraCommitLatExpr=Null
1182 mask=0
1183 match=0
1184 opClasses=system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses
1185 srcRegsRelativeLats=2
1186 suppress=false
1187
1188 [system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses]
1189 type=MinorOpClassSet
1190 eventq_index=0
1191 opClasses=
1192
1193 [system.cpu1.executeFuncUnits.funcUnits1]
1194 type=MinorFU
1195 children=opClasses timings
1196 cantForwardFromFUIndices=
1197 eventq_index=0
1198 issueLat=1
1199 opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses
1200 opLat=3
1201 timings=system.cpu1.executeFuncUnits.funcUnits1.timings
1202
1203 [system.cpu1.executeFuncUnits.funcUnits1.opClasses]
1204 type=MinorOpClassSet
1205 children=opClasses
1206 eventq_index=0
1207 opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses
1208
1209 [system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses]
1210 type=MinorOpClass
1211 eventq_index=0
1212 opClass=IntAlu
1213
1214 [system.cpu1.executeFuncUnits.funcUnits1.timings]
1215 type=MinorFUTiming
1216 children=opClasses
1217 description=Int
1218 eventq_index=0
1219 extraAssumedLat=0
1220 extraCommitLat=0
1221 extraCommitLatExpr=Null
1222 mask=0
1223 match=0
1224 opClasses=system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses
1225 srcRegsRelativeLats=2
1226 suppress=false
1227
1228 [system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses]
1229 type=MinorOpClassSet
1230 eventq_index=0
1231 opClasses=
1232
1233 [system.cpu1.executeFuncUnits.funcUnits2]
1234 type=MinorFU
1235 children=opClasses timings
1236 cantForwardFromFUIndices=
1237 eventq_index=0
1238 issueLat=1
1239 opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses
1240 opLat=3
1241 timings=system.cpu1.executeFuncUnits.funcUnits2.timings
1242
1243 [system.cpu1.executeFuncUnits.funcUnits2.opClasses]
1244 type=MinorOpClassSet
1245 children=opClasses
1246 eventq_index=0
1247 opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses
1248
1249 [system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses]
1250 type=MinorOpClass
1251 eventq_index=0
1252 opClass=IntMult
1253
1254 [system.cpu1.executeFuncUnits.funcUnits2.timings]
1255 type=MinorFUTiming
1256 children=opClasses
1257 description=Mul
1258 eventq_index=0
1259 extraAssumedLat=0
1260 extraCommitLat=0
1261 extraCommitLatExpr=Null
1262 mask=0
1263 match=0
1264 opClasses=system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses
1265 srcRegsRelativeLats=0
1266 suppress=false
1267
1268 [system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses]
1269 type=MinorOpClassSet
1270 eventq_index=0
1271 opClasses=
1272
1273 [system.cpu1.executeFuncUnits.funcUnits3]
1274 type=MinorFU
1275 children=opClasses
1276 cantForwardFromFUIndices=
1277 eventq_index=0
1278 issueLat=9
1279 opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses
1280 opLat=9
1281 timings=
1282
1283 [system.cpu1.executeFuncUnits.funcUnits3.opClasses]
1284 type=MinorOpClassSet
1285 children=opClasses
1286 eventq_index=0
1287 opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses
1288
1289 [system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses]
1290 type=MinorOpClass
1291 eventq_index=0
1292 opClass=IntDiv
1293
1294 [system.cpu1.executeFuncUnits.funcUnits4]
1295 type=MinorFU
1296 children=opClasses timings
1297 cantForwardFromFUIndices=
1298 eventq_index=0
1299 issueLat=1
1300 opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses
1301 opLat=6
1302 timings=system.cpu1.executeFuncUnits.funcUnits4.timings
1303
1304 [system.cpu1.executeFuncUnits.funcUnits4.opClasses]
1305 type=MinorOpClassSet
1306 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
1307 eventq_index=0
1308 opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27
1309
1310 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00]
1311 type=MinorOpClass
1312 eventq_index=0
1313 opClass=FloatAdd
1314
1315 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01]
1316 type=MinorOpClass
1317 eventq_index=0
1318 opClass=FloatCmp
1319
1320 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02]
1321 type=MinorOpClass
1322 eventq_index=0
1323 opClass=FloatCvt
1324
1325 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03]
1326 type=MinorOpClass
1327 eventq_index=0
1328 opClass=FloatMisc
1329
1330 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04]
1331 type=MinorOpClass
1332 eventq_index=0
1333 opClass=FloatMult
1334
1335 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05]
1336 type=MinorOpClass
1337 eventq_index=0
1338 opClass=FloatMultAcc
1339
1340 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06]
1341 type=MinorOpClass
1342 eventq_index=0
1343 opClass=FloatDiv
1344
1345 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07]
1346 type=MinorOpClass
1347 eventq_index=0
1348 opClass=FloatSqrt
1349
1350 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08]
1351 type=MinorOpClass
1352 eventq_index=0
1353 opClass=SimdAdd
1354
1355 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09]
1356 type=MinorOpClass
1357 eventq_index=0
1358 opClass=SimdAddAcc
1359
1360 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10]
1361 type=MinorOpClass
1362 eventq_index=0
1363 opClass=SimdAlu
1364
1365 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11]
1366 type=MinorOpClass
1367 eventq_index=0
1368 opClass=SimdCmp
1369
1370 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12]
1371 type=MinorOpClass
1372 eventq_index=0
1373 opClass=SimdCvt
1374
1375 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13]
1376 type=MinorOpClass
1377 eventq_index=0
1378 opClass=SimdMisc
1379
1380 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14]
1381 type=MinorOpClass
1382 eventq_index=0
1383 opClass=SimdMult
1384
1385 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15]
1386 type=MinorOpClass
1387 eventq_index=0
1388 opClass=SimdMultAcc
1389
1390 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16]
1391 type=MinorOpClass
1392 eventq_index=0
1393 opClass=SimdShift
1394
1395 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17]
1396 type=MinorOpClass
1397 eventq_index=0
1398 opClass=SimdShiftAcc
1399
1400 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18]
1401 type=MinorOpClass
1402 eventq_index=0
1403 opClass=SimdSqrt
1404
1405 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19]
1406 type=MinorOpClass
1407 eventq_index=0
1408 opClass=SimdFloatAdd
1409
1410 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20]
1411 type=MinorOpClass
1412 eventq_index=0
1413 opClass=SimdFloatAlu
1414
1415 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21]
1416 type=MinorOpClass
1417 eventq_index=0
1418 opClass=SimdFloatCmp
1419
1420 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22]
1421 type=MinorOpClass
1422 eventq_index=0
1423 opClass=SimdFloatCvt
1424
1425 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23]
1426 type=MinorOpClass
1427 eventq_index=0
1428 opClass=SimdFloatDiv
1429
1430 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24]
1431 type=MinorOpClass
1432 eventq_index=0
1433 opClass=SimdFloatMisc
1434
1435 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25]
1436 type=MinorOpClass
1437 eventq_index=0
1438 opClass=SimdFloatMult
1439
1440 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26]
1441 type=MinorOpClass
1442 eventq_index=0
1443 opClass=SimdFloatMultAcc
1444
1445 [system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27]
1446 type=MinorOpClass
1447 eventq_index=0
1448 opClass=SimdFloatSqrt
1449
1450 [system.cpu1.executeFuncUnits.funcUnits4.timings]
1451 type=MinorFUTiming
1452 children=opClasses
1453 description=FloatSimd
1454 eventq_index=0
1455 extraAssumedLat=0
1456 extraCommitLat=0
1457 extraCommitLatExpr=Null
1458 mask=0
1459 match=0
1460 opClasses=system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses
1461 srcRegsRelativeLats=2
1462 suppress=false
1463
1464 [system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses]
1465 type=MinorOpClassSet
1466 eventq_index=0
1467 opClasses=
1468
1469 [system.cpu1.executeFuncUnits.funcUnits5]
1470 type=MinorFU
1471 children=opClasses timings
1472 cantForwardFromFUIndices=
1473 eventq_index=0
1474 issueLat=1
1475 opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses
1476 opLat=1
1477 timings=system.cpu1.executeFuncUnits.funcUnits5.timings
1478
1479 [system.cpu1.executeFuncUnits.funcUnits5.opClasses]
1480 type=MinorOpClassSet
1481 children=opClasses0 opClasses1 opClasses2 opClasses3
1482 eventq_index=0
1483 opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3
1484
1485 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0]
1486 type=MinorOpClass
1487 eventq_index=0
1488 opClass=MemRead
1489
1490 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1]
1491 type=MinorOpClass
1492 eventq_index=0
1493 opClass=MemWrite
1494
1495 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2]
1496 type=MinorOpClass
1497 eventq_index=0
1498 opClass=FloatMemRead
1499
1500 [system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3]
1501 type=MinorOpClass
1502 eventq_index=0
1503 opClass=FloatMemWrite
1504
1505 [system.cpu1.executeFuncUnits.funcUnits5.timings]
1506 type=MinorFUTiming
1507 children=opClasses
1508 description=Mem
1509 eventq_index=0
1510 extraAssumedLat=2
1511 extraCommitLat=0
1512 extraCommitLatExpr=Null
1513 mask=0
1514 match=0
1515 opClasses=system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses
1516 srcRegsRelativeLats=1
1517 suppress=false
1518
1519 [system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses]
1520 type=MinorOpClassSet
1521 eventq_index=0
1522 opClasses=
1523
1524 [system.cpu1.executeFuncUnits.funcUnits6]
1525 type=MinorFU
1526 children=opClasses
1527 cantForwardFromFUIndices=
1528 eventq_index=0
1529 issueLat=1
1530 opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses
1531 opLat=1
1532 timings=
1533
1534 [system.cpu1.executeFuncUnits.funcUnits6.opClasses]
1535 type=MinorOpClassSet
1536 children=opClasses0 opClasses1
1537 eventq_index=0
1538 opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1
1539
1540 [system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0]
1541 type=MinorOpClass
1542 eventq_index=0
1543 opClass=IprAccess
1544
1545 [system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1]
1546 type=MinorOpClass
1547 eventq_index=0
1548 opClass=InstPrefetch
1549
1550 [system.cpu1.icache]
1551 type=Cache
1552 children=tags
1553 addr_ranges=0:18446744073709551615:0:0:0:0
1554 assoc=2
1555 clk_domain=system.cpu_clk_domain
1556 clusivity=mostly_incl
1557 data_latency=1
1558 default_p_state=UNDEFINED
1559 demand_mshr_reserve=1
1560 eventq_index=0
1561 is_read_only=true
1562 max_miss_count=0
1563 mshrs=2
1564 p_state_clk_gate_bins=20
1565 p_state_clk_gate_max=1000000000000
1566 p_state_clk_gate_min=1000
1567 power_model=Null
1568 prefetch_on_access=false
1569 prefetcher=Null
1570 response_latency=1
1571 sequential_access=false
1572 size=32768
1573 system=system
1574 tag_latency=1
1575 tags=system.cpu1.icache.tags
1576 tgts_per_mshr=8
1577 write_buffers=8
1578 writeback_clean=true
1579 cpu_side=system.cpu1.icache_port
1580 mem_side=system.cpu1.toL2Bus.slave[0]
1581
1582 [system.cpu1.icache.tags]
1583 type=LRU
1584 assoc=2
1585 block_size=64
1586 clk_domain=system.cpu_clk_domain
1587 data_latency=1
1588 default_p_state=UNDEFINED
1589 eventq_index=0
1590 p_state_clk_gate_bins=20
1591 p_state_clk_gate_max=1000000000000
1592 p_state_clk_gate_min=1000
1593 power_model=Null
1594 sequential_access=false
1595 size=32768
1596 tag_latency=1
1597
1598 [system.cpu1.interrupts]
1599 type=ArmInterrupts
1600 eventq_index=0
1601
1602 [system.cpu1.isa]
1603 type=ArmISA
1604 decoderFlavour=Generic
1605 eventq_index=0
1606 fpsid=1090793632
1607 id_aa64afr0_el1=0
1608 id_aa64afr1_el1=0
1609 id_aa64dfr0_el1=1052678
1610 id_aa64dfr1_el1=0
1611 id_aa64isar0_el1=0
1612 id_aa64isar1_el1=0
1613 id_aa64mmfr0_el1=15728642
1614 id_aa64mmfr1_el1=0
1615 id_isar0=34607377
1616 id_isar1=34677009
1617 id_isar2=555950401
1618 id_isar3=17899825
1619 id_isar4=268501314
1620 id_isar5=0
1621 id_mmfr0=270536963
1622 id_mmfr1=0
1623 id_mmfr2=19070976
1624 id_mmfr3=34611729
1625 midr=1091551472
1626 pmu=Null
1627 system=system
1628
1629 [system.cpu1.istage2_mmu]
1630 type=ArmStage2MMU
1631 children=stage2_tlb
1632 eventq_index=0
1633 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1634 sys=system
1635 tlb=system.cpu1.itb
1636
1637 [system.cpu1.istage2_mmu.stage2_tlb]
1638 type=ArmTLB
1639 children=walker
1640 eventq_index=0
1641 is_stage2=true
1642 size=32
1643 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1644
1645 [system.cpu1.istage2_mmu.stage2_tlb.walker]
1646 type=ArmTableWalker
1647 clk_domain=system.cpu_clk_domain
1648 default_p_state=UNDEFINED
1649 eventq_index=0
1650 is_stage2=true
1651 num_squash_per_cycle=2
1652 p_state_clk_gate_bins=20
1653 p_state_clk_gate_max=1000000000000
1654 p_state_clk_gate_min=1000
1655 power_model=Null
1656 sys=system
1657
1658 [system.cpu1.itb]
1659 type=ArmTLB
1660 children=walker
1661 eventq_index=0
1662 is_stage2=false
1663 size=64
1664 walker=system.cpu1.itb.walker
1665
1666 [system.cpu1.itb.walker]
1667 type=ArmTableWalker
1668 clk_domain=system.cpu_clk_domain
1669 default_p_state=UNDEFINED
1670 eventq_index=0
1671 is_stage2=false
1672 num_squash_per_cycle=2
1673 p_state_clk_gate_bins=20
1674 p_state_clk_gate_max=1000000000000
1675 p_state_clk_gate_min=1000
1676 power_model=Null
1677 sys=system
1678 port=system.cpu1.toL2Bus.slave[2]
1679
1680 [system.cpu1.l2cache]
1681 type=Cache
1682 children=prefetcher tags
1683 addr_ranges=0:18446744073709551615:0:0:0:0
1684 assoc=16
1685 clk_domain=system.cpu_clk_domain
1686 clusivity=mostly_excl
1687 data_latency=12
1688 default_p_state=UNDEFINED
1689 demand_mshr_reserve=1
1690 eventq_index=0
1691 is_read_only=false
1692 max_miss_count=0
1693 mshrs=16
1694 p_state_clk_gate_bins=20
1695 p_state_clk_gate_max=1000000000000
1696 p_state_clk_gate_min=1000
1697 power_model=Null
1698 prefetch_on_access=true
1699 prefetcher=system.cpu1.l2cache.prefetcher
1700 response_latency=12
1701 sequential_access=false
1702 size=1048576
1703 system=system
1704 tag_latency=12
1705 tags=system.cpu1.l2cache.tags
1706 tgts_per_mshr=8
1707 write_buffers=8
1708 writeback_clean=false
1709 cpu_side=system.cpu1.toL2Bus.master[0]
1710 mem_side=system.toL2Bus.slave[1]
1711
1712 [system.cpu1.l2cache.prefetcher]
1713 type=StridePrefetcher
1714 cache_snoop=false
1715 clk_domain=system.cpu_clk_domain
1716 default_p_state=UNDEFINED
1717 degree=8
1718 eventq_index=0
1719 latency=1
1720 max_conf=7
1721 min_conf=0
1722 on_data=true
1723 on_inst=true
1724 on_miss=false
1725 on_read=true
1726 on_write=true
1727 p_state_clk_gate_bins=20
1728 p_state_clk_gate_max=1000000000000
1729 p_state_clk_gate_min=1000
1730 power_model=Null
1731 queue_filter=true
1732 queue_size=32
1733 queue_squash=true
1734 start_conf=4
1735 sys=system
1736 table_assoc=4
1737 table_sets=16
1738 tag_prefetch=true
1739 thresh_conf=4
1740 use_master_id=true
1741
1742 [system.cpu1.l2cache.tags]
1743 type=RandomRepl
1744 assoc=16
1745 block_size=64
1746 clk_domain=system.cpu_clk_domain
1747 data_latency=12
1748 default_p_state=UNDEFINED
1749 eventq_index=0
1750 p_state_clk_gate_bins=20
1751 p_state_clk_gate_max=1000000000000
1752 p_state_clk_gate_min=1000
1753 power_model=Null
1754 sequential_access=false
1755 size=1048576
1756 tag_latency=12
1757
1758 [system.cpu1.toL2Bus]
1759 type=CoherentXBar
1760 children=snoop_filter
1761 clk_domain=system.cpu_clk_domain
1762 default_p_state=UNDEFINED
1763 eventq_index=0
1764 forward_latency=0
1765 frontend_latency=1
1766 p_state_clk_gate_bins=20
1767 p_state_clk_gate_max=1000000000000
1768 p_state_clk_gate_min=1000
1769 point_of_coherency=false
1770 power_model=Null
1771 response_latency=1
1772 snoop_filter=system.cpu1.toL2Bus.snoop_filter
1773 snoop_response_latency=1
1774 system=system
1775 use_default_range=false
1776 width=32
1777 master=system.cpu1.l2cache.cpu_side
1778 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1779
1780 [system.cpu1.toL2Bus.snoop_filter]
1781 type=SnoopFilter
1782 eventq_index=0
1783 lookup_latency=0
1784 max_capacity=8388608
1785 system=system
1786
1787 [system.cpu1.tracer]
1788 type=ExeTracer
1789 eventq_index=0
1790
1791 [system.cpu_clk_domain]
1792 type=SrcClockDomain
1793 clock=500
1794 domain_id=-1
1795 eventq_index=0
1796 init_perf_level=0
1797 voltage_domain=system.voltage_domain
1798
1799 [system.dvfs_handler]
1800 type=DVFSHandler
1801 domains=
1802 enable=false
1803 eventq_index=0
1804 sys_clk_domain=system.clk_domain
1805 transition_latency=100000000
1806
1807 [system.intrctrl]
1808 type=IntrControl
1809 eventq_index=0
1810 sys=system
1811
1812 [system.iobus]
1813 type=NoncoherentXBar
1814 clk_domain=system.clk_domain
1815 default_p_state=UNDEFINED
1816 eventq_index=0
1817 forward_latency=1
1818 frontend_latency=2
1819 p_state_clk_gate_bins=20
1820 p_state_clk_gate_max=1000000000000
1821 p_state_clk_gate_min=1000
1822 power_model=Null
1823 response_latency=2
1824 use_default_range=false
1825 width=16
1826 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
1827 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
1828
1829 [system.iocache]
1830 type=Cache
1831 children=tags
1832 addr_ranges=2147483648:2415919103:0:0:0:0
1833 assoc=8
1834 clk_domain=system.clk_domain
1835 clusivity=mostly_incl
1836 data_latency=50
1837 default_p_state=UNDEFINED
1838 demand_mshr_reserve=1
1839 eventq_index=0
1840 is_read_only=false
1841 max_miss_count=0
1842 mshrs=20
1843 p_state_clk_gate_bins=20
1844 p_state_clk_gate_max=1000000000000
1845 p_state_clk_gate_min=1000
1846 power_model=Null
1847 prefetch_on_access=false
1848 prefetcher=Null
1849 response_latency=50
1850 sequential_access=false
1851 size=1024
1852 system=system
1853 tag_latency=50
1854 tags=system.iocache.tags
1855 tgts_per_mshr=12
1856 write_buffers=8
1857 writeback_clean=false
1858 cpu_side=system.iobus.master[25]
1859 mem_side=system.membus.slave[3]
1860
1861 [system.iocache.tags]
1862 type=LRU
1863 assoc=8
1864 block_size=64
1865 clk_domain=system.clk_domain
1866 data_latency=50
1867 default_p_state=UNDEFINED
1868 eventq_index=0
1869 p_state_clk_gate_bins=20
1870 p_state_clk_gate_max=1000000000000
1871 p_state_clk_gate_min=1000
1872 power_model=Null
1873 sequential_access=false
1874 size=1024
1875 tag_latency=50
1876
1877 [system.l2c]
1878 type=Cache
1879 children=tags
1880 addr_ranges=0:18446744073709551615:0:0:0:0
1881 assoc=8
1882 clk_domain=system.cpu_clk_domain
1883 clusivity=mostly_incl
1884 data_latency=20
1885 default_p_state=UNDEFINED
1886 demand_mshr_reserve=1
1887 eventq_index=0
1888 is_read_only=false
1889 max_miss_count=0
1890 mshrs=20
1891 p_state_clk_gate_bins=20
1892 p_state_clk_gate_max=1000000000000
1893 p_state_clk_gate_min=1000
1894 power_model=Null
1895 prefetch_on_access=false
1896 prefetcher=Null
1897 response_latency=20
1898 sequential_access=false
1899 size=4194304
1900 system=system
1901 tag_latency=20
1902 tags=system.l2c.tags
1903 tgts_per_mshr=12
1904 write_buffers=8
1905 writeback_clean=false
1906 cpu_side=system.toL2Bus.master[0]
1907 mem_side=system.membus.slave[2]
1908
1909 [system.l2c.tags]
1910 type=LRU
1911 assoc=8
1912 block_size=64
1913 clk_domain=system.cpu_clk_domain
1914 data_latency=20
1915 default_p_state=UNDEFINED
1916 eventq_index=0
1917 p_state_clk_gate_bins=20
1918 p_state_clk_gate_max=1000000000000
1919 p_state_clk_gate_min=1000
1920 power_model=Null
1921 sequential_access=false
1922 size=4194304
1923 tag_latency=20
1924
1925 [system.membus]
1926 type=CoherentXBar
1927 children=badaddr_responder snoop_filter
1928 clk_domain=system.clk_domain
1929 default_p_state=UNDEFINED
1930 eventq_index=0
1931 forward_latency=4
1932 frontend_latency=3
1933 p_state_clk_gate_bins=20
1934 p_state_clk_gate_max=1000000000000
1935 p_state_clk_gate_min=1000
1936 point_of_coherency=true
1937 power_model=Null
1938 response_latency=2
1939 snoop_filter=system.membus.snoop_filter
1940 snoop_response_latency=4
1941 system=system
1942 use_default_range=false
1943 width=16
1944 default=system.membus.badaddr_responder.pio
1945 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1946 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1947
1948 [system.membus.badaddr_responder]
1949 type=IsaFake
1950 clk_domain=system.clk_domain
1951 default_p_state=UNDEFINED
1952 eventq_index=0
1953 fake_mem=false
1954 p_state_clk_gate_bins=20
1955 p_state_clk_gate_max=1000000000000
1956 p_state_clk_gate_min=1000
1957 pio_addr=0
1958 pio_latency=100000
1959 pio_size=8
1960 power_model=Null
1961 ret_bad_addr=true
1962 ret_data16=65535
1963 ret_data32=4294967295
1964 ret_data64=18446744073709551615
1965 ret_data8=255
1966 system=system
1967 update_data=false
1968 warn_access=warn
1969 pio=system.membus.default
1970
1971 [system.membus.snoop_filter]
1972 type=SnoopFilter
1973 eventq_index=0
1974 lookup_latency=1
1975 max_capacity=8388608
1976 system=system
1977
1978 [system.physmem]
1979 type=DRAMCtrl
1980 IDD0=0.055000
1981 IDD02=0.000000
1982 IDD2N=0.032000
1983 IDD2N2=0.000000
1984 IDD2P0=0.000000
1985 IDD2P02=0.000000
1986 IDD2P1=0.032000
1987 IDD2P12=0.000000
1988 IDD3N=0.038000
1989 IDD3N2=0.000000
1990 IDD3P0=0.000000
1991 IDD3P02=0.000000
1992 IDD3P1=0.038000
1993 IDD3P12=0.000000
1994 IDD4R=0.157000
1995 IDD4R2=0.000000
1996 IDD4W=0.125000
1997 IDD4W2=0.000000
1998 IDD5=0.235000
1999 IDD52=0.000000
2000 IDD6=0.020000
2001 IDD62=0.000000
2002 VDD=1.500000
2003 VDD2=0.000000
2004 activation_limit=4
2005 addr_mapping=RoRaBaCoCh
2006 bank_groups_per_rank=0
2007 banks_per_rank=8
2008 burst_length=8
2009 channels=1
2010 clk_domain=system.clk_domain
2011 conf_table_reported=true
2012 default_p_state=UNDEFINED
2013 device_bus_width=8
2014 device_rowbuffer_size=1024
2015 device_size=536870912
2016 devices_per_rank=8
2017 dll=true
2018 eventq_index=0
2019 in_addr_map=true
2020 kvm_map=true
2021 max_accesses_per_row=16
2022 mem_sched_policy=frfcfs
2023 min_writes_per_switch=16
2024 null=false
2025 p_state_clk_gate_bins=20
2026 p_state_clk_gate_max=1000000000000
2027 p_state_clk_gate_min=1000
2028 page_policy=open_adaptive
2029 power_model=Null
2030 range=2147483648:2415919103:0:0:0:0
2031 ranks_per_channel=2
2032 read_buffer_size=32
2033 static_backend_latency=10000
2034 static_frontend_latency=10000
2035 tBURST=5000
2036 tCCD_L=0
2037 tCK=1250
2038 tCL=13750
2039 tCS=2500
2040 tRAS=35000
2041 tRCD=13750
2042 tREFI=7800000
2043 tRFC=260000
2044 tRP=13750
2045 tRRD=6000
2046 tRRD_L=0
2047 tRTP=7500
2048 tRTW=2500
2049 tWR=15000
2050 tWTR=7500
2051 tXAW=30000
2052 tXP=6000
2053 tXPDLL=0
2054 tXS=270000
2055 tXSDLL=0
2056 write_buffer_size=64
2057 write_high_thresh_perc=85
2058 write_low_thresh_perc=50
2059 port=system.membus.master[5]
2060
2061 [system.realview]
2062 type=RealView
2063 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
2064 eventq_index=0
2065 intrctrl=system.intrctrl
2066 system=system
2067
2068 [system.realview.aaci_fake]
2069 type=AmbaFake
2070 amba_id=0
2071 clk_domain=system.clk_domain
2072 default_p_state=UNDEFINED
2073 eventq_index=0
2074 ignore_access=false
2075 p_state_clk_gate_bins=20
2076 p_state_clk_gate_max=1000000000000
2077 p_state_clk_gate_min=1000
2078 pio_addr=470024192
2079 pio_latency=100000
2080 power_model=Null
2081 system=system
2082 pio=system.iobus.master[18]
2083
2084 [system.realview.cf_ctrl]
2085 type=IdeController
2086 BAR0=471465984
2087 BAR0LegacyIO=true
2088 BAR0Size=256
2089 BAR1=471466240
2090 BAR1LegacyIO=true
2091 BAR1Size=4096
2092 BAR2=1
2093 BAR2LegacyIO=false
2094 BAR2Size=8
2095 BAR3=1
2096 BAR3LegacyIO=false
2097 BAR3Size=4
2098 BAR4=1
2099 BAR4LegacyIO=false
2100 BAR4Size=16
2101 BAR5=1
2102 BAR5LegacyIO=false
2103 BAR5Size=0
2104 BIST=0
2105 CacheLineSize=0
2106 CapabilityPtr=0
2107 CardbusCIS=0
2108 ClassCode=1
2109 Command=1
2110 DeviceID=28945
2111 ExpansionROM=0
2112 HeaderType=0
2113 InterruptLine=31
2114 InterruptPin=1
2115 LatencyTimer=0
2116 LegacyIOBase=0
2117 MSICAPBaseOffset=0
2118 MSICAPCapId=0
2119 MSICAPMaskBits=0
2120 MSICAPMsgAddr=0
2121 MSICAPMsgCtrl=0
2122 MSICAPMsgData=0
2123 MSICAPMsgUpperAddr=0
2124 MSICAPNextCapability=0
2125 MSICAPPendingBits=0
2126 MSIXCAPBaseOffset=0
2127 MSIXCAPCapId=0
2128 MSIXCAPNextCapability=0
2129 MSIXMsgCtrl=0
2130 MSIXPbaOffset=0
2131 MSIXTableOffset=0
2132 MaximumLatency=0
2133 MinimumGrant=0
2134 PMCAPBaseOffset=0
2135 PMCAPCapId=0
2136 PMCAPCapabilities=0
2137 PMCAPCtrlStatus=0
2138 PMCAPNextCapability=0
2139 PXCAPBaseOffset=0
2140 PXCAPCapId=0
2141 PXCAPCapabilities=0
2142 PXCAPDevCap2=0
2143 PXCAPDevCapabilities=0
2144 PXCAPDevCtrl=0
2145 PXCAPDevCtrl2=0
2146 PXCAPDevStatus=0
2147 PXCAPLinkCap=0
2148 PXCAPLinkCtrl=0
2149 PXCAPLinkStatus=0
2150 PXCAPNextCapability=0
2151 ProgIF=133
2152 Revision=0
2153 Status=640
2154 SubClassCode=1
2155 SubsystemID=0
2156 SubsystemVendorID=0
2157 VendorID=32902
2158 clk_domain=system.clk_domain
2159 config_latency=20000
2160 ctrl_offset=2
2161 default_p_state=UNDEFINED
2162 disks=
2163 eventq_index=0
2164 host=system.realview.pci_host
2165 io_shift=2
2166 p_state_clk_gate_bins=20
2167 p_state_clk_gate_max=1000000000000
2168 p_state_clk_gate_min=1000
2169 pci_bus=2
2170 pci_dev=0
2171 pci_func=0
2172 pio_latency=30000
2173 power_model=Null
2174 system=system
2175 dma=system.iobus.slave[2]
2176 pio=system.iobus.master[9]
2177
2178 [system.realview.clcd]
2179 type=Pl111
2180 amba_id=1315089
2181 clk_domain=system.clk_domain
2182 default_p_state=UNDEFINED
2183 enable_capture=true
2184 eventq_index=0
2185 gic=system.realview.gic
2186 int_num=46
2187 p_state_clk_gate_bins=20
2188 p_state_clk_gate_max=1000000000000
2189 p_state_clk_gate_min=1000
2190 pio_addr=471793664
2191 pio_latency=10000
2192 pixel_clock=41667
2193 power_model=Null
2194 system=system
2195 vnc=system.vncserver
2196 dma=system.iobus.slave[1]
2197 pio=system.iobus.master[5]
2198
2199 [system.realview.dcc]
2200 type=SubSystem
2201 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
2202 eventq_index=0
2203 thermal_domain=Null
2204
2205 [system.realview.dcc.osc_cpu]
2206 type=RealViewOsc
2207 dcc=0
2208 device=0
2209 eventq_index=0
2210 freq=16667
2211 parent=system.realview.realview_io
2212 position=0
2213 site=1
2214 voltage_domain=system.voltage_domain
2215
2216 [system.realview.dcc.osc_ddr]
2217 type=RealViewOsc
2218 dcc=0
2219 device=8
2220 eventq_index=0
2221 freq=25000
2222 parent=system.realview.realview_io
2223 position=0
2224 site=1
2225 voltage_domain=system.voltage_domain
2226
2227 [system.realview.dcc.osc_hsbm]
2228 type=RealViewOsc
2229 dcc=0
2230 device=4
2231 eventq_index=0
2232 freq=25000
2233 parent=system.realview.realview_io
2234 position=0
2235 site=1
2236 voltage_domain=system.voltage_domain
2237
2238 [system.realview.dcc.osc_pxl]
2239 type=RealViewOsc
2240 dcc=0
2241 device=5
2242 eventq_index=0
2243 freq=42105
2244 parent=system.realview.realview_io
2245 position=0
2246 site=1
2247 voltage_domain=system.voltage_domain
2248
2249 [system.realview.dcc.osc_smb]
2250 type=RealViewOsc
2251 dcc=0
2252 device=6
2253 eventq_index=0
2254 freq=20000
2255 parent=system.realview.realview_io
2256 position=0
2257 site=1
2258 voltage_domain=system.voltage_domain
2259
2260 [system.realview.dcc.osc_sys]
2261 type=RealViewOsc
2262 dcc=0
2263 device=7
2264 eventq_index=0
2265 freq=16667
2266 parent=system.realview.realview_io
2267 position=0
2268 site=1
2269 voltage_domain=system.voltage_domain
2270
2271 [system.realview.energy_ctrl]
2272 type=EnergyCtrl
2273 clk_domain=system.clk_domain
2274 default_p_state=UNDEFINED
2275 dvfs_handler=system.dvfs_handler
2276 eventq_index=0
2277 p_state_clk_gate_bins=20
2278 p_state_clk_gate_max=1000000000000
2279 p_state_clk_gate_min=1000
2280 pio_addr=470286336
2281 pio_latency=100000
2282 power_model=Null
2283 system=system
2284 pio=system.iobus.master[22]
2285
2286 [system.realview.ethernet]
2287 type=IGbE
2288 BAR0=0
2289 BAR0LegacyIO=false
2290 BAR0Size=131072
2291 BAR1=0
2292 BAR1LegacyIO=false
2293 BAR1Size=0
2294 BAR2=0
2295 BAR2LegacyIO=false
2296 BAR2Size=0
2297 BAR3=0
2298 BAR3LegacyIO=false
2299 BAR3Size=0
2300 BAR4=0
2301 BAR4LegacyIO=false
2302 BAR4Size=0
2303 BAR5=0
2304 BAR5LegacyIO=false
2305 BAR5Size=0
2306 BIST=0
2307 CacheLineSize=0
2308 CapabilityPtr=0
2309 CardbusCIS=0
2310 ClassCode=2
2311 Command=0
2312 DeviceID=4213
2313 ExpansionROM=0
2314 HeaderType=0
2315 InterruptLine=1
2316 InterruptPin=1
2317 LatencyTimer=0
2318 LegacyIOBase=0
2319 MSICAPBaseOffset=0
2320 MSICAPCapId=0
2321 MSICAPMaskBits=0
2322 MSICAPMsgAddr=0
2323 MSICAPMsgCtrl=0
2324 MSICAPMsgData=0
2325 MSICAPMsgUpperAddr=0
2326 MSICAPNextCapability=0
2327 MSICAPPendingBits=0
2328 MSIXCAPBaseOffset=0
2329 MSIXCAPCapId=0
2330 MSIXCAPNextCapability=0
2331 MSIXMsgCtrl=0
2332 MSIXPbaOffset=0
2333 MSIXTableOffset=0
2334 MaximumLatency=0
2335 MinimumGrant=255
2336 PMCAPBaseOffset=0
2337 PMCAPCapId=0
2338 PMCAPCapabilities=0
2339 PMCAPCtrlStatus=0
2340 PMCAPNextCapability=0
2341 PXCAPBaseOffset=0
2342 PXCAPCapId=0
2343 PXCAPCapabilities=0
2344 PXCAPDevCap2=0
2345 PXCAPDevCapabilities=0
2346 PXCAPDevCtrl=0
2347 PXCAPDevCtrl2=0
2348 PXCAPDevStatus=0
2349 PXCAPLinkCap=0
2350 PXCAPLinkCtrl=0
2351 PXCAPLinkStatus=0
2352 PXCAPNextCapability=0
2353 ProgIF=0
2354 Revision=0
2355 Status=0
2356 SubClassCode=0
2357 SubsystemID=4104
2358 SubsystemVendorID=32902
2359 VendorID=32902
2360 clk_domain=system.clk_domain
2361 config_latency=20000
2362 default_p_state=UNDEFINED
2363 eventq_index=0
2364 fetch_comp_delay=10000
2365 fetch_delay=10000
2366 hardware_address=00:90:00:00:00:01
2367 host=system.realview.pci_host
2368 p_state_clk_gate_bins=20
2369 p_state_clk_gate_max=1000000000000
2370 p_state_clk_gate_min=1000
2371 pci_bus=0
2372 pci_dev=0
2373 pci_func=0
2374 phy_epid=896
2375 phy_pid=680
2376 pio_latency=30000
2377 power_model=Null
2378 rx_desc_cache_size=64
2379 rx_fifo_size=393216
2380 rx_write_delay=0
2381 system=system
2382 tx_desc_cache_size=64
2383 tx_fifo_size=393216
2384 tx_read_delay=0
2385 wb_comp_delay=10000
2386 wb_delay=10000
2387 dma=system.iobus.slave[4]
2388 pio=system.iobus.master[24]
2389
2390 [system.realview.generic_timer]
2391 type=GenericTimer
2392 eventq_index=0
2393 gic=system.realview.gic
2394 int_phys=29
2395 int_virt=27
2396 system=system
2397
2398 [system.realview.gic]
2399 type=Pl390
2400 clk_domain=system.clk_domain
2401 cpu_addr=738205696
2402 cpu_pio_delay=10000
2403 default_p_state=UNDEFINED
2404 dist_addr=738201600
2405 dist_pio_delay=10000
2406 eventq_index=0
2407 gem5_extensions=false
2408 int_latency=10000
2409 it_lines=128
2410 p_state_clk_gate_bins=20
2411 p_state_clk_gate_max=1000000000000
2412 p_state_clk_gate_min=1000
2413 platform=system.realview
2414 power_model=Null
2415 system=system
2416 pio=system.membus.master[2]
2417
2418 [system.realview.hdlcd]
2419 type=HDLcd
2420 amba_id=1314816
2421 clk_domain=system.clk_domain
2422 default_p_state=UNDEFINED
2423 enable_capture=true
2424 eventq_index=0
2425 gic=system.realview.gic
2426 int_num=117
2427 p_state_clk_gate_bins=20
2428 p_state_clk_gate_max=1000000000000
2429 p_state_clk_gate_min=1000
2430 pio_addr=721420288
2431 pio_latency=10000
2432 pixel_buffer_size=2048
2433 pixel_chunk=32
2434 power_model=Null
2435 pxl_clk=system.realview.dcc.osc_pxl
2436 system=system
2437 vnc=system.vncserver
2438 workaround_dma_line_count=true
2439 workaround_swap_rb=true
2440 dma=system.membus.slave[0]
2441 pio=system.iobus.master[6]
2442
2443 [system.realview.ide]
2444 type=IdeController
2445 BAR0=1
2446 BAR0LegacyIO=false
2447 BAR0Size=8
2448 BAR1=1
2449 BAR1LegacyIO=false
2450 BAR1Size=4
2451 BAR2=1
2452 BAR2LegacyIO=false
2453 BAR2Size=8
2454 BAR3=1
2455 BAR3LegacyIO=false
2456 BAR3Size=4
2457 BAR4=1
2458 BAR4LegacyIO=false
2459 BAR4Size=16
2460 BAR5=1
2461 BAR5LegacyIO=false
2462 BAR5Size=0
2463 BIST=0
2464 CacheLineSize=0
2465 CapabilityPtr=0
2466 CardbusCIS=0
2467 ClassCode=1
2468 Command=0
2469 DeviceID=28945
2470 ExpansionROM=0
2471 HeaderType=0
2472 InterruptLine=2
2473 InterruptPin=2
2474 LatencyTimer=0
2475 LegacyIOBase=0
2476 MSICAPBaseOffset=0
2477 MSICAPCapId=0
2478 MSICAPMaskBits=0
2479 MSICAPMsgAddr=0
2480 MSICAPMsgCtrl=0
2481 MSICAPMsgData=0
2482 MSICAPMsgUpperAddr=0
2483 MSICAPNextCapability=0
2484 MSICAPPendingBits=0
2485 MSIXCAPBaseOffset=0
2486 MSIXCAPCapId=0
2487 MSIXCAPNextCapability=0
2488 MSIXMsgCtrl=0
2489 MSIXPbaOffset=0
2490 MSIXTableOffset=0
2491 MaximumLatency=0
2492 MinimumGrant=0
2493 PMCAPBaseOffset=0
2494 PMCAPCapId=0
2495 PMCAPCapabilities=0
2496 PMCAPCtrlStatus=0
2497 PMCAPNextCapability=0
2498 PXCAPBaseOffset=0
2499 PXCAPCapId=0
2500 PXCAPCapabilities=0
2501 PXCAPDevCap2=0
2502 PXCAPDevCapabilities=0
2503 PXCAPDevCtrl=0
2504 PXCAPDevCtrl2=0
2505 PXCAPDevStatus=0
2506 PXCAPLinkCap=0
2507 PXCAPLinkCtrl=0
2508 PXCAPLinkStatus=0
2509 PXCAPNextCapability=0
2510 ProgIF=133
2511 Revision=0
2512 Status=640
2513 SubClassCode=1
2514 SubsystemID=0
2515 SubsystemVendorID=0
2516 VendorID=32902
2517 clk_domain=system.clk_domain
2518 config_latency=20000
2519 ctrl_offset=0
2520 default_p_state=UNDEFINED
2521 disks=system.cf0
2522 eventq_index=0
2523 host=system.realview.pci_host
2524 io_shift=0
2525 p_state_clk_gate_bins=20
2526 p_state_clk_gate_max=1000000000000
2527 p_state_clk_gate_min=1000
2528 pci_bus=0
2529 pci_dev=1
2530 pci_func=0
2531 pio_latency=30000
2532 power_model=Null
2533 system=system
2534 dma=system.iobus.slave[3]
2535 pio=system.iobus.master[23]
2536
2537 [system.realview.kmi0]
2538 type=Pl050
2539 amba_id=1314896
2540 clk_domain=system.clk_domain
2541 default_p_state=UNDEFINED
2542 eventq_index=0
2543 gic=system.realview.gic
2544 int_delay=1000000
2545 int_num=44
2546 is_mouse=false
2547 p_state_clk_gate_bins=20
2548 p_state_clk_gate_max=1000000000000
2549 p_state_clk_gate_min=1000
2550 pio_addr=470155264
2551 pio_latency=100000
2552 power_model=Null
2553 system=system
2554 vnc=system.vncserver
2555 pio=system.iobus.master[7]
2556
2557 [system.realview.kmi1]
2558 type=Pl050
2559 amba_id=1314896
2560 clk_domain=system.clk_domain
2561 default_p_state=UNDEFINED
2562 eventq_index=0
2563 gic=system.realview.gic
2564 int_delay=1000000
2565 int_num=45
2566 is_mouse=true
2567 p_state_clk_gate_bins=20
2568 p_state_clk_gate_max=1000000000000
2569 p_state_clk_gate_min=1000
2570 pio_addr=470220800
2571 pio_latency=100000
2572 power_model=Null
2573 system=system
2574 vnc=system.vncserver
2575 pio=system.iobus.master[8]
2576
2577 [system.realview.l2x0_fake]
2578 type=IsaFake
2579 clk_domain=system.clk_domain
2580 default_p_state=UNDEFINED
2581 eventq_index=0
2582 fake_mem=false
2583 p_state_clk_gate_bins=20
2584 p_state_clk_gate_max=1000000000000
2585 p_state_clk_gate_min=1000
2586 pio_addr=739246080
2587 pio_latency=100000
2588 pio_size=4095
2589 power_model=Null
2590 ret_bad_addr=false
2591 ret_data16=65535
2592 ret_data32=4294967295
2593 ret_data64=18446744073709551615
2594 ret_data8=255
2595 system=system
2596 update_data=false
2597 warn_access=
2598 pio=system.iobus.master[12]
2599
2600 [system.realview.lan_fake]
2601 type=IsaFake
2602 clk_domain=system.clk_domain
2603 default_p_state=UNDEFINED
2604 eventq_index=0
2605 fake_mem=false
2606 p_state_clk_gate_bins=20
2607 p_state_clk_gate_max=1000000000000
2608 p_state_clk_gate_min=1000
2609 pio_addr=436207616
2610 pio_latency=100000
2611 pio_size=65535
2612 power_model=Null
2613 ret_bad_addr=false
2614 ret_data16=65535
2615 ret_data32=4294967295
2616 ret_data64=18446744073709551615
2617 ret_data8=255
2618 system=system
2619 update_data=false
2620 warn_access=
2621 pio=system.iobus.master[19]
2622
2623 [system.realview.local_cpu_timer]
2624 type=CpuLocalTimer
2625 clk_domain=system.clk_domain
2626 default_p_state=UNDEFINED
2627 eventq_index=0
2628 gic=system.realview.gic
2629 int_num_timer=29
2630 int_num_watchdog=30
2631 p_state_clk_gate_bins=20
2632 p_state_clk_gate_max=1000000000000
2633 p_state_clk_gate_min=1000
2634 pio_addr=738721792
2635 pio_latency=100000
2636 power_model=Null
2637 system=system
2638 pio=system.membus.master[4]
2639
2640 [system.realview.mcc]
2641 type=SubSystem
2642 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
2643 eventq_index=0
2644 thermal_domain=Null
2645
2646 [system.realview.mcc.osc_clcd]
2647 type=RealViewOsc
2648 dcc=0
2649 device=1
2650 eventq_index=0
2651 freq=42105
2652 parent=system.realview.realview_io
2653 position=0
2654 site=0
2655 voltage_domain=system.voltage_domain
2656
2657 [system.realview.mcc.osc_mcc]
2658 type=RealViewOsc
2659 dcc=0
2660 device=0
2661 eventq_index=0
2662 freq=20000
2663 parent=system.realview.realview_io
2664 position=0
2665 site=0
2666 voltage_domain=system.voltage_domain
2667
2668 [system.realview.mcc.osc_peripheral]
2669 type=RealViewOsc
2670 dcc=0
2671 device=2
2672 eventq_index=0
2673 freq=41667
2674 parent=system.realview.realview_io
2675 position=0
2676 site=0
2677 voltage_domain=system.voltage_domain
2678
2679 [system.realview.mcc.osc_system_bus]
2680 type=RealViewOsc
2681 dcc=0
2682 device=4
2683 eventq_index=0
2684 freq=41667
2685 parent=system.realview.realview_io
2686 position=0
2687 site=0
2688 voltage_domain=system.voltage_domain
2689
2690 [system.realview.mcc.temp_crtl]
2691 type=RealViewTemperatureSensor
2692 dcc=0
2693 device=0
2694 eventq_index=0
2695 parent=system.realview.realview_io
2696 position=0
2697 site=0
2698 system=system
2699
2700 [system.realview.mmc_fake]
2701 type=AmbaFake
2702 amba_id=0
2703 clk_domain=system.clk_domain
2704 default_p_state=UNDEFINED
2705 eventq_index=0
2706 ignore_access=false
2707 p_state_clk_gate_bins=20
2708 p_state_clk_gate_max=1000000000000
2709 p_state_clk_gate_min=1000
2710 pio_addr=470089728
2711 pio_latency=100000
2712 power_model=Null
2713 system=system
2714 pio=system.iobus.master[21]
2715
2716 [system.realview.nvmem]
2717 type=SimpleMemory
2718 bandwidth=73.000000
2719 clk_domain=system.clk_domain
2720 conf_table_reported=false
2721 default_p_state=UNDEFINED
2722 eventq_index=0
2723 in_addr_map=true
2724 kvm_map=true
2725 latency=30000
2726 latency_var=0
2727 null=false
2728 p_state_clk_gate_bins=20
2729 p_state_clk_gate_max=1000000000000
2730 p_state_clk_gate_min=1000
2731 power_model=Null
2732 range=0:67108863:0:0:0:0
2733 port=system.membus.master[1]
2734
2735 [system.realview.pci_host]
2736 type=GenericPciHost
2737 clk_domain=system.clk_domain
2738 conf_base=805306368
2739 conf_device_bits=16
2740 conf_size=268435456
2741 default_p_state=UNDEFINED
2742 eventq_index=0
2743 p_state_clk_gate_bins=20
2744 p_state_clk_gate_max=1000000000000
2745 p_state_clk_gate_min=1000
2746 pci_dma_base=0
2747 pci_mem_base=0
2748 pci_pio_base=0
2749 platform=system.realview
2750 power_model=Null
2751 system=system
2752 pio=system.iobus.master[2]
2753
2754 [system.realview.realview_io]
2755 type=RealViewCtrl
2756 clk_domain=system.clk_domain
2757 default_p_state=UNDEFINED
2758 eventq_index=0
2759 idreg=35979264
2760 p_state_clk_gate_bins=20
2761 p_state_clk_gate_max=1000000000000
2762 p_state_clk_gate_min=1000
2763 pio_addr=469827584
2764 pio_latency=100000
2765 power_model=Null
2766 proc_id0=335544320
2767 proc_id1=335544320
2768 system=system
2769 pio=system.iobus.master[1]
2770
2771 [system.realview.rtc]
2772 type=PL031
2773 amba_id=3412017
2774 clk_domain=system.clk_domain
2775 default_p_state=UNDEFINED
2776 eventq_index=0
2777 gic=system.realview.gic
2778 int_delay=100000
2779 int_num=36
2780 p_state_clk_gate_bins=20
2781 p_state_clk_gate_max=1000000000000
2782 p_state_clk_gate_min=1000
2783 pio_addr=471269376
2784 pio_latency=100000
2785 power_model=Null
2786 system=system
2787 time=Thu Jan  1 00:00:00 2009
2788 pio=system.iobus.master[10]
2789
2790 [system.realview.sp810_fake]
2791 type=AmbaFake
2792 amba_id=0
2793 clk_domain=system.clk_domain
2794 default_p_state=UNDEFINED
2795 eventq_index=0
2796 ignore_access=true
2797 p_state_clk_gate_bins=20
2798 p_state_clk_gate_max=1000000000000
2799 p_state_clk_gate_min=1000
2800 pio_addr=469893120
2801 pio_latency=100000
2802 power_model=Null
2803 system=system
2804 pio=system.iobus.master[16]
2805
2806 [system.realview.timer0]
2807 type=Sp804
2808 amba_id=1316868
2809 clk_domain=system.clk_domain
2810 clock0=1000000
2811 clock1=1000000
2812 default_p_state=UNDEFINED
2813 eventq_index=0
2814 gic=system.realview.gic
2815 int_num0=34
2816 int_num1=34
2817 p_state_clk_gate_bins=20
2818 p_state_clk_gate_max=1000000000000
2819 p_state_clk_gate_min=1000
2820 pio_addr=470876160
2821 pio_latency=100000
2822 power_model=Null
2823 system=system
2824 pio=system.iobus.master[3]
2825
2826 [system.realview.timer1]
2827 type=Sp804
2828 amba_id=1316868
2829 clk_domain=system.clk_domain
2830 clock0=1000000
2831 clock1=1000000
2832 default_p_state=UNDEFINED
2833 eventq_index=0
2834 gic=system.realview.gic
2835 int_num0=35
2836 int_num1=35
2837 p_state_clk_gate_bins=20
2838 p_state_clk_gate_max=1000000000000
2839 p_state_clk_gate_min=1000
2840 pio_addr=470941696
2841 pio_latency=100000
2842 power_model=Null
2843 system=system
2844 pio=system.iobus.master[4]
2845
2846 [system.realview.uart]
2847 type=Pl011
2848 clk_domain=system.clk_domain
2849 default_p_state=UNDEFINED
2850 end_on_eot=false
2851 eventq_index=0
2852 gic=system.realview.gic
2853 int_delay=100000
2854 int_num=37
2855 p_state_clk_gate_bins=20
2856 p_state_clk_gate_max=1000000000000
2857 p_state_clk_gate_min=1000
2858 pio_addr=470351872
2859 pio_latency=100000
2860 platform=system.realview
2861 power_model=Null
2862 system=system
2863 terminal=system.terminal
2864 pio=system.iobus.master[0]
2865
2866 [system.realview.uart1_fake]
2867 type=AmbaFake
2868 amba_id=0
2869 clk_domain=system.clk_domain
2870 default_p_state=UNDEFINED
2871 eventq_index=0
2872 ignore_access=false
2873 p_state_clk_gate_bins=20
2874 p_state_clk_gate_max=1000000000000
2875 p_state_clk_gate_min=1000
2876 pio_addr=470417408
2877 pio_latency=100000
2878 power_model=Null
2879 system=system
2880 pio=system.iobus.master[13]
2881
2882 [system.realview.uart2_fake]
2883 type=AmbaFake
2884 amba_id=0
2885 clk_domain=system.clk_domain
2886 default_p_state=UNDEFINED
2887 eventq_index=0
2888 ignore_access=false
2889 p_state_clk_gate_bins=20
2890 p_state_clk_gate_max=1000000000000
2891 p_state_clk_gate_min=1000
2892 pio_addr=470482944
2893 pio_latency=100000
2894 power_model=Null
2895 system=system
2896 pio=system.iobus.master[14]
2897
2898 [system.realview.uart3_fake]
2899 type=AmbaFake
2900 amba_id=0
2901 clk_domain=system.clk_domain
2902 default_p_state=UNDEFINED
2903 eventq_index=0
2904 ignore_access=false
2905 p_state_clk_gate_bins=20
2906 p_state_clk_gate_max=1000000000000
2907 p_state_clk_gate_min=1000
2908 pio_addr=470548480
2909 pio_latency=100000
2910 power_model=Null
2911 system=system
2912 pio=system.iobus.master[15]
2913
2914 [system.realview.usb_fake]
2915 type=IsaFake
2916 clk_domain=system.clk_domain
2917 default_p_state=UNDEFINED
2918 eventq_index=0
2919 fake_mem=false
2920 p_state_clk_gate_bins=20
2921 p_state_clk_gate_max=1000000000000
2922 p_state_clk_gate_min=1000
2923 pio_addr=452984832
2924 pio_latency=100000
2925 pio_size=131071
2926 power_model=Null
2927 ret_bad_addr=false
2928 ret_data16=65535
2929 ret_data32=4294967295
2930 ret_data64=18446744073709551615
2931 ret_data8=255
2932 system=system
2933 update_data=false
2934 warn_access=
2935 pio=system.iobus.master[20]
2936
2937 [system.realview.vgic]
2938 type=VGic
2939 clk_domain=system.clk_domain
2940 default_p_state=UNDEFINED
2941 eventq_index=0
2942 gic=system.realview.gic
2943 hv_addr=738213888
2944 p_state_clk_gate_bins=20
2945 p_state_clk_gate_max=1000000000000
2946 p_state_clk_gate_min=1000
2947 pio_delay=10000
2948 platform=system.realview
2949 power_model=Null
2950 ppint=25
2951 system=system
2952 vcpu_addr=738222080
2953 pio=system.membus.master[3]
2954
2955 [system.realview.vram]
2956 type=SimpleMemory
2957 bandwidth=73.000000
2958 clk_domain=system.clk_domain
2959 conf_table_reported=false
2960 default_p_state=UNDEFINED
2961 eventq_index=0
2962 in_addr_map=true
2963 kvm_map=true
2964 latency=30000
2965 latency_var=0
2966 null=false
2967 p_state_clk_gate_bins=20
2968 p_state_clk_gate_max=1000000000000
2969 p_state_clk_gate_min=1000
2970 power_model=Null
2971 range=402653184:436207615:0:0:0:0
2972 port=system.iobus.master[11]
2973
2974 [system.realview.watchdog_fake]
2975 type=AmbaFake
2976 amba_id=0
2977 clk_domain=system.clk_domain
2978 default_p_state=UNDEFINED
2979 eventq_index=0
2980 ignore_access=false
2981 p_state_clk_gate_bins=20
2982 p_state_clk_gate_max=1000000000000
2983 p_state_clk_gate_min=1000
2984 pio_addr=470745088
2985 pio_latency=100000
2986 power_model=Null
2987 system=system
2988 pio=system.iobus.master[17]
2989
2990 [system.terminal]
2991 type=Terminal
2992 eventq_index=0
2993 intr_control=system.intrctrl
2994 number=0
2995 output=true
2996 port=3456
2997
2998 [system.toL2Bus]
2999 type=CoherentXBar
3000 children=snoop_filter
3001 clk_domain=system.cpu_clk_domain
3002 default_p_state=UNDEFINED
3003 eventq_index=0
3004 forward_latency=0
3005 frontend_latency=1
3006 p_state_clk_gate_bins=20
3007 p_state_clk_gate_max=1000000000000
3008 p_state_clk_gate_min=1000
3009 point_of_coherency=false
3010 power_model=Null
3011 response_latency=1
3012 snoop_filter=system.toL2Bus.snoop_filter
3013 snoop_response_latency=1
3014 system=system
3015 use_default_range=false
3016 width=32
3017 master=system.l2c.cpu_side
3018 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
3019
3020 [system.toL2Bus.snoop_filter]
3021 type=SnoopFilter
3022 eventq_index=0
3023 lookup_latency=0
3024 max_capacity=8388608
3025 system=system
3026
3027 [system.vncserver]
3028 type=VncServer
3029 eventq_index=0
3030 frame_capture=false
3031 number=0
3032 port=5900
3033
3034 [system.voltage_domain]
3035 type=VoltageDomain
3036 eventq_index=0
3037 voltage=1.000000
3038