2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 47.310816 # Number of seconds simulated
4 sim_ticks 47310816168000 # Number of ticks simulated
5 final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 279196 # Simulator instruction rate (inst/s)
8 host_op_rate 332505 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 15871048208 # Simulator tick rate (ticks/s)
10 host_mem_usage 770320 # Number of bytes of host memory used
11 host_seconds 2980.95 # Real time elapsed on the host
12 sim_insts 832269934 # Number of instructions simulated
13 sim_ops 991180133 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory
26 system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory
27 system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory
28 system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory
29 system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory
31 system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory
32 system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory
33 system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34 system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35 system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory
36 system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory
46 system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory
47 system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory
48 system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory
49 system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50 system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51 system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory
52 system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s)
71 system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s)
84 system.physmem.readReqs 1084146 # Number of read requests accepted
85 system.physmem.writeReqs 1315173 # Number of write requests accepted
86 system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue
87 system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue
88 system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM
89 system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue
90 system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM
91 system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side
92 system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side
93 system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue
94 system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
95 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96 system.physmem.perBankRdBursts::0 69238 # Per bank write bursts
97 system.physmem.perBankRdBursts::1 72128 # Per bank write bursts
98 system.physmem.perBankRdBursts::2 62859 # Per bank write bursts
99 system.physmem.perBankRdBursts::3 64909 # Per bank write bursts
100 system.physmem.perBankRdBursts::4 64833 # Per bank write bursts
101 system.physmem.perBankRdBursts::5 74280 # Per bank write bursts
102 system.physmem.perBankRdBursts::6 68552 # Per bank write bursts
103 system.physmem.perBankRdBursts::7 74109 # Per bank write bursts
104 system.physmem.perBankRdBursts::8 62269 # Per bank write bursts
105 system.physmem.perBankRdBursts::9 70311 # Per bank write bursts
106 system.physmem.perBankRdBursts::10 59842 # Per bank write bursts
107 system.physmem.perBankRdBursts::11 70232 # Per bank write bursts
108 system.physmem.perBankRdBursts::12 64744 # Per bank write bursts
109 system.physmem.perBankRdBursts::13 72876 # Per bank write bursts
110 system.physmem.perBankRdBursts::14 66012 # Per bank write bursts
111 system.physmem.perBankRdBursts::15 66520 # Per bank write bursts
112 system.physmem.perBankWrBursts::0 83559 # Per bank write bursts
113 system.physmem.perBankWrBursts::1 83793 # Per bank write bursts
114 system.physmem.perBankWrBursts::2 79464 # Per bank write bursts
115 system.physmem.perBankWrBursts::3 82775 # Per bank write bursts
116 system.physmem.perBankWrBursts::4 80648 # Per bank write bursts
117 system.physmem.perBankWrBursts::5 87124 # Per bank write bursts
118 system.physmem.perBankWrBursts::6 80406 # Per bank write bursts
119 system.physmem.perBankWrBursts::7 83854 # Per bank write bursts
120 system.physmem.perBankWrBursts::8 77300 # Per bank write bursts
121 system.physmem.perBankWrBursts::9 82321 # Per bank write bursts
122 system.physmem.perBankWrBursts::10 78447 # Per bank write bursts
123 system.physmem.perBankWrBursts::11 84798 # Per bank write bursts
124 system.physmem.perBankWrBursts::12 79286 # Per bank write bursts
125 system.physmem.perBankWrBursts::13 85569 # Per bank write bursts
126 system.physmem.perBankWrBursts::14 81705 # Per bank write bursts
127 system.physmem.perBankWrBursts::15 81847 # Per bank write bursts
128 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129 system.physmem.numWrRetry 404 # Number of times write queue was full causing retry
130 system.physmem.totGap 47310814104000 # Total gap between requests
131 system.physmem.readPktSize::0 0 # Read request sizes (log2)
132 system.physmem.readPktSize::1 0 # Read request sizes (log2)
133 system.physmem.readPktSize::2 0 # Read request sizes (log2)
134 system.physmem.readPktSize::3 25 # Read request sizes (log2)
135 system.physmem.readPktSize::4 5 # Read request sizes (log2)
136 system.physmem.readPktSize::5 0 # Read request sizes (log2)
137 system.physmem.readPktSize::6 1084116 # Read request sizes (log2)
138 system.physmem.writePktSize::0 0 # Write request sizes (log2)
139 system.physmem.writePktSize::1 0 # Write request sizes (log2)
140 system.physmem.writePktSize::2 2 # Write request sizes (log2)
141 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142 system.physmem.writePktSize::4 0 # Write request sizes (log2)
143 system.physmem.writePktSize::5 0 # Write request sizes (log2)
144 system.physmem.writePktSize::6 1312599 # Write request sizes (log2)
145 system.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::6 29577 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::7 26712 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::8 23659 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::9 6340 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::10 2474 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::11 1816 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::12 1451 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::13 1051 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::14 661 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::15 562 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::16 469 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::17 366 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
176 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
177 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::15 25826 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::17 51697 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::18 60223 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::19 67549 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::20 71954 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::21 74550 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::22 77056 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::23 80172 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::24 80848 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::25 83842 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::26 85747 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::27 82598 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::33 5576 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::35 2165 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::36 1766 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::40 972 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::43 845 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::44 859 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::45 720 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::46 777 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::47 704 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::48 661 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::49 705 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::50 720 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::52 655 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see
240 system.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see
241 system.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation
255 system.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes
256 system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes
257 system.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes
258 system.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes
259 system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
261 system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
262 system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
263 system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes
264 system.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads
299 system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads
300 system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads
301 system.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads
302 system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads
303 system.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads
304 system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads
305 system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads
306 system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads
307 system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
308 system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads
309 system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads
310 system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads
311 system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads
312 system.physmem.totQLat 57570179828 # Total ticks spent queuing
313 system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM
314 system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers
315 system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst
316 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
317 system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst
318 system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s
319 system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
320 system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s
321 system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
322 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
323 system.physmem.busUtil 0.03 # Data bus utilization in percentage
324 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
325 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
326 system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
327 system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing
328 system.physmem.readRowHits 798943 # Number of row buffer hits during reads
329 system.physmem.writeRowHits 553978 # Number of row buffer hits during writes
330 system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads
331 system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes
332 system.physmem.avgGap 19718434.32 # Average gap between requests
333 system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined
334 system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ)
335 system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ)
336 system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ)
337 system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ)
338 system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ)
339 system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ)
340 system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ)
341 system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ)
342 system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ)
343 system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ)
344 system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ)
345 system.physmem_0.averagePower 242.939265 # Core power per rank (mW)
346 system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank
347 system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states
348 system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states
349 system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states
350 system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states
351 system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states
352 system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states
353 system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ)
354 system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ)
355 system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ)
356 system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ)
357 system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ)
358 system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ)
359 system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ)
360 system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ)
361 system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ)
362 system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ)
363 system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ)
364 system.physmem_1.averagePower 242.827762 # Core power per rank (mW)
365 system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank
366 system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states
367 system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states
368 system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states
369 system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states
370 system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states
371 system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states
372 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
373 system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
374 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
375 system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
376 system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
377 system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
378 system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
379 system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
380 system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
381 system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
382 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
383 system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
384 system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
385 system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
386 system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
387 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
388 system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s)
389 system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
390 system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
391 system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
392 system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
393 system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
394 system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
395 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
396 system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
397 system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
398 system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
399 system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
400 system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
401 system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
402 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
403 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
404 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
405 system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
406 system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
407 system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
408 system.cpu0.branchPred.lookups 116746639 # Number of BP lookups
409 system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted
410 system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect
411 system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups
412 system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits
413 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
414 system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage
415 system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target.
416 system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions.
417 system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups.
418 system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits.
419 system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses.
420 system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches.
421 system.cpu_clk_domain.clock 500 # Clock period in ticks
422 system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
423 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
424 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
425 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
426 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
427 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
428 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
429 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
430 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
431 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
432 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
433 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
434 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
435 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
436 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
437 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
438 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
439 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
440 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
441 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
442 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
443 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
444 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
445 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
446 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
447 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
448 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
449 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
450 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
451 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
452 system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
453 system.cpu0.dtb.walker.walks 291933 # Table walker walks requested
454 system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors
455 system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate
456 system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate
457 system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency
458 system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency
459 system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency
460 system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency
461 system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency
462 system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency
463 system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency
464 system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency
465 system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency
466 system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency
467 system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency
468 system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
469 system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
470 system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
471 system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
472 system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
473 system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
474 system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency
475 system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution
476 system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution
477 system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution
478 system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated
479 system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated
480 system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated
481 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst
482 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
483 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst
484 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst
485 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
486 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst
487 system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst
488 system.cpu0.dtb.inst_hits 0 # ITB inst hits
489 system.cpu0.dtb.inst_misses 0 # ITB inst misses
490 system.cpu0.dtb.read_hits 91107490 # DTB read hits
491 system.cpu0.dtb.read_misses 238663 # DTB read misses
492 system.cpu0.dtb.write_hits 81148084 # DTB write hits
493 system.cpu0.dtb.write_misses 53270 # DTB write misses
494 system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
495 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
496 system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
497 system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
498 system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB
499 system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions
500 system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch
501 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
502 system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions
503 system.cpu0.dtb.read_accesses 91346153 # DTB read accesses
504 system.cpu0.dtb.write_accesses 81201354 # DTB write accesses
505 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
506 system.cpu0.dtb.hits 172255574 # DTB hits
507 system.cpu0.dtb.misses 291933 # DTB misses
508 system.cpu0.dtb.accesses 172547507 # DTB accesses
509 system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
510 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
511 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
512 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
513 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
514 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
515 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
516 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
517 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
518 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
519 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
520 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
521 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
522 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
523 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
524 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
525 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
526 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
527 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
528 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
529 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
530 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
531 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
532 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
533 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
534 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
535 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
536 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
537 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
538 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
539 system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
540 system.cpu0.itb.walker.walks 65131 # Table walker walks requested
541 system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors
542 system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate
543 system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate
544 system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency
545 system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency
546 system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency
547 system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency
548 system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency
549 system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency
550 system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency
551 system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency
552 system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency
553 system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency
554 system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency
555 system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency
556 system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
557 system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
558 system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency
559 system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency
560 system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution
561 system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution
562 system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution
563 system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated
564 system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated
565 system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated
566 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
567 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst
568 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst
569 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
570 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst
571 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst
572 system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst
573 system.cpu0.itb.inst_hits 201165320 # ITB inst hits
574 system.cpu0.itb.inst_misses 65131 # ITB inst misses
575 system.cpu0.itb.read_hits 0 # DTB read hits
576 system.cpu0.itb.read_misses 0 # DTB read misses
577 system.cpu0.itb.write_hits 0 # DTB write hits
578 system.cpu0.itb.write_misses 0 # DTB write misses
579 system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
580 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
581 system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
582 system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
583 system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB
584 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
585 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
586 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
587 system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions
588 system.cpu0.itb.read_accesses 0 # DTB read accesses
589 system.cpu0.itb.write_accesses 0 # DTB write accesses
590 system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses
591 system.cpu0.itb.hits 201165320 # DTB hits
592 system.cpu0.itb.misses 65131 # DTB misses
593 system.cpu0.itb.accesses 201230451 # DTB accesses
594 system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions
595 system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state
596 system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state
597 system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state
598 system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state
599 system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state
600 system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
601 system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
602 system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
603 system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
604 system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
605 system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
606 system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
607 system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
608 system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
609 system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
610 system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state
611 system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state
612 system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states
613 system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states
614 system.cpu0.numCycles 923231946 # number of cpu cycles simulated
615 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
616 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
617 system.cpu0.committedInsts 433947137 # Number of instructions committed
618 system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed
619 system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit
620 system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching
621 system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
622 system.cpu0.cpi 2.127522 # CPI: cycles per instruction
623 system.cpu0.ipc 0.470030 # IPC: instructions per cycle
624 system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
625 system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction
626 system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction
627 system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction
628 system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction
629 system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction
630 system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction
631 system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction
632 system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction
633 system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction
634 system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction
635 system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction
636 system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction
637 system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction
638 system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction
639 system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction
640 system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction
641 system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction
642 system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction
643 system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction
644 system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction
645 system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction
646 system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction
647 system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction
648 system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction
649 system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction
650 system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction
651 system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction
652 system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction
653 system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction
654 system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction
655 system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction
656 system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction
657 system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction
658 system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction
659 system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction
660 system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
661 system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
662 system.cpu0.op_class_0::total 516803462 # Class of committed instruction
663 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
664 system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed
665 system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked
666 system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped
667 system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
668 system.cpu0.dcache.tags.replacements 6005277 # number of replacements
669 system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use
670 system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks.
671 system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks.
672 system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks.
673 system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit.
674 system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor
675 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy
676 system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy
677 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
678 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
679 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
680 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
681 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
682 system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses
683 system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses
684 system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
685 system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits
686 system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits
687 system.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits
688 system.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits
689 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits
690 system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits
691 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits
692 system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits
693 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits
694 system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits
695 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits
696 system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits
697 system.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits
698 system.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits
699 system.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits
700 system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits
701 system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses
702 system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses
703 system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses
704 system.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses
705 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses
706 system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses
707 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses
708 system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses
709 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses
710 system.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses
711 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses
712 system.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses
713 system.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses
714 system.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses
715 system.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses
716 system.cpu0.dcache.overall_misses::total 7527165 # number of overall misses
717 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles
718 system.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles
719 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles
720 system.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles
721 system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles
722 system.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles
723 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles
724 system.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles
725 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles
726 system.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles
727 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles
728 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles
729 system.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles
730 system.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles
731 system.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles
732 system.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles
733 system.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses)
734 system.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses)
735 system.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses)
736 system.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses)
737 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses)
738 system.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses)
739 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses)
740 system.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses)
741 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses)
742 system.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses)
743 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses)
744 system.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses)
745 system.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses
746 system.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses
747 system.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses
748 system.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses
749 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses
750 system.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses
751 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses
752 system.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses
753 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses
754 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses
755 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses
756 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses
757 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses
758 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses
759 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses
760 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses
761 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses
762 system.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses
763 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses
764 system.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses
765 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency
766 system.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency
767 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency
768 system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency
769 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency
770 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency
771 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency
772 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency
773 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency
774 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency
775 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
776 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
777 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency
778 system.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency
779 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency
780 system.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency
781 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
782 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
783 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
784 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
785 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
787 system.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks
788 system.cpu0.dcache.writebacks::total 6005280 # number of writebacks
789 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits
790 system.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits
791 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits
792 system.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits
793 system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits
794 system.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits
795 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits
796 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits
797 system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits
798 system.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
799 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits
800 system.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits
801 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits
802 system.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits
803 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses
804 system.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses
805 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses
806 system.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses
807 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses
808 system.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses
809 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses
810 system.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses
811 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses
812 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses
813 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses
814 system.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses
815 system.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses
816 system.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses
817 system.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses
818 system.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses
819 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
820 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable
821 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
822 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
823 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
824 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses
825 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles
826 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles
827 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles
828 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles
829 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles
830 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles
831 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles
832 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles
833 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles
834 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles
835 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles
836 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles
837 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles
838 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles
839 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles
840 system.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles
841 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles
842 system.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles
843 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles
844 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles
845 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles
846 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles
847 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses
848 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses
849 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses
850 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses
851 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses
852 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses
853 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses
854 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses
855 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses
856 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses
857 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses
858 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses
859 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses
860 system.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses
861 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses
862 system.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses
863 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency
864 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency
865 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency
866 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency
867 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency
868 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency
869 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency
870 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency
871 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency
872 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency
873 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency
874 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency
875 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
876 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
877 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency
878 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency
879 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency
880 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency
881 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency
882 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency
883 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency
884 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency
885 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
886 system.cpu0.icache.tags.replacements 9998472 # number of replacements
887 system.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use
888 system.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks.
889 system.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks.
890 system.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks.
891 system.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit.
892 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor
893 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy
894 system.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy
895 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
896 system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
897 system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
898 system.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
899 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
900 system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses
901 system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses
902 system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
903 system.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits
904 system.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits
905 system.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits
906 system.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits
907 system.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits
908 system.cpu0.icache.overall_hits::total 190986664 # number of overall hits
909 system.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses
910 system.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses
911 system.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses
912 system.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses
913 system.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses
914 system.cpu0.icache.overall_misses::total 9998995 # number of overall misses
915 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles
916 system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles
917 system.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles
918 system.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles
919 system.cpu0.icache.overall_miss_latency::cpu0.inst 104315202000 # number of overall miss cycles
920 system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles
921 system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses)
922 system.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses)
923 system.cpu0.icache.demand_accesses::cpu0.inst 200985659 # number of demand (read+write) accesses
924 system.cpu0.icache.demand_accesses::total 200985659 # number of demand (read+write) accesses
925 system.cpu0.icache.overall_accesses::cpu0.inst 200985659 # number of overall (read+write) accesses
926 system.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses
927 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049750 # miss rate for ReadReq accesses
928 system.cpu0.icache.ReadReq_miss_rate::total 0.049750 # miss rate for ReadReq accesses
929 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049750 # miss rate for demand accesses
930 system.cpu0.icache.demand_miss_rate::total 0.049750 # miss rate for demand accesses
931 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049750 # miss rate for overall accesses
932 system.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses
933 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency
934 system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency
935 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
936 system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency
937 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
938 system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency
939 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
940 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
941 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
942 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
943 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
944 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
945 system.cpu0.icache.writebacks::writebacks 9998472 # number of writebacks
946 system.cpu0.icache.writebacks::total 9998472 # number of writebacks
947 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9998995 # number of ReadReq MSHR misses
948 system.cpu0.icache.ReadReq_mshr_misses::total 9998995 # number of ReadReq MSHR misses
949 system.cpu0.icache.demand_mshr_misses::cpu0.inst 9998995 # number of demand (read+write) MSHR misses
950 system.cpu0.icache.demand_mshr_misses::total 9998995 # number of demand (read+write) MSHR misses
951 system.cpu0.icache.overall_mshr_misses::cpu0.inst 9998995 # number of overall MSHR misses
952 system.cpu0.icache.overall_mshr_misses::total 9998995 # number of overall MSHR misses
953 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
954 system.cpu0.icache.ReadReq_mshr_uncacheable::total 4283 # number of ReadReq MSHR uncacheable
955 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
956 system.cpu0.icache.overall_mshr_uncacheable_misses::total 4283 # number of overall MSHR uncacheable misses
957 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99315705000 # number of ReadReq MSHR miss cycles
958 system.cpu0.icache.ReadReq_mshr_miss_latency::total 99315705000 # number of ReadReq MSHR miss cycles
959 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99315705000 # number of demand (read+write) MSHR miss cycles
960 system.cpu0.icache.demand_mshr_miss_latency::total 99315705000 # number of demand (read+write) MSHR miss cycles
961 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99315705000 # number of overall MSHR miss cycles
962 system.cpu0.icache.overall_mshr_miss_latency::total 99315705000 # number of overall MSHR miss cycles
963 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 427814500 # number of ReadReq MSHR uncacheable cycles
964 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 427814500 # number of ReadReq MSHR uncacheable cycles
965 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 427814500 # number of overall MSHR uncacheable cycles
966 system.cpu0.icache.overall_mshr_uncacheable_latency::total 427814500 # number of overall MSHR uncacheable cycles
967 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for ReadReq accesses
968 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.049750 # mshr miss rate for ReadReq accesses
969 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for demand accesses
970 system.cpu0.icache.demand_mshr_miss_rate::total 0.049750 # mshr miss rate for demand accesses
971 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for overall accesses
972 system.cpu0.icache.overall_mshr_miss_rate::total 0.049750 # mshr miss rate for overall accesses
973 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average ReadReq mshr miss latency
974 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.568723 # average ReadReq mshr miss latency
975 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
976 system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
977 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
978 system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
979 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average ReadReq mshr uncacheable latency
980 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency
981 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency
982 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency
983 system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
984 system.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued
985 system.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified
986 system.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue
987 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
988 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
989 system.cpu0.l2cache.prefetcher.pfSpanPage 1047741 # number of prefetches not generated due to page crossing
990 system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
991 system.cpu0.l2cache.tags.replacements 2932551 # number of replacements
992 system.cpu0.l2cache.tags.tagsinuse 15705.924224 # Cycle average of tags in use
993 system.cpu0.l2cache.tags.total_refs 14272950 # Total number of references to valid blocks.
994 system.cpu0.l2cache.tags.sampled_refs 2948325 # Sample count of references to valid blocks.
995 system.cpu0.l2cache.tags.avg_refs 4.841037 # Average number of references to valid blocks.
996 system.cpu0.l2cache.tags.warmup_cycle 1130072000 # Cycle when the warmup percentage was hit.
997 system.cpu0.l2cache.tags.occ_blocks::writebacks 15376.526197 # Average occupied blocks per requestor
998 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 37.361518 # Average occupied blocks per requestor
999 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 20.248621 # Average occupied blocks per requestor
1000 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 271.787888 # Average occupied blocks per requestor
1001 system.cpu0.l2cache.tags.occ_percent::writebacks 0.938509 # Average percentage of cache occupancy
1002 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002280 # Average percentage of cache occupancy
1003 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001236 # Average percentage of cache occupancy
1004 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016589 # Average percentage of cache occupancy
1005 system.cpu0.l2cache.tags.occ_percent::total 0.958614 # Average percentage of cache occupancy
1006 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 362 # Occupied blocks per task id
1007 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
1008 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id
1009 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
1010 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 176 # Occupied blocks per task id
1011 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id
1012 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id
1013 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
1014 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
1015 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
1016 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
1017 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2130 # Occupied blocks per task id
1018 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6262 # Occupied blocks per task id
1019 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5229 # Occupied blocks per task id
1020 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id
1021 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022095 # Percentage of cache occupancy per task id
1022 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id
1023 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id
1024 system.cpu0.l2cache.tags.tag_accesses 549297414 # Number of tag accesses
1025 system.cpu0.l2cache.tags.data_accesses 549297414 # Number of data accesses
1026 system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1027 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539317 # number of ReadReq hits
1028 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 165054 # number of ReadReq hits
1029 system.cpu0.l2cache.ReadReq_hits::total 704371 # number of ReadReq hits
1030 system.cpu0.l2cache.WritebackDirty_hits::writebacks 3976191 # number of WritebackDirty hits
1031 system.cpu0.l2cache.WritebackDirty_hits::total 3976191 # number of WritebackDirty hits
1032 system.cpu0.l2cache.WritebackClean_hits::writebacks 12024318 # number of WritebackClean hits
1033 system.cpu0.l2cache.WritebackClean_hits::total 12024318 # number of WritebackClean hits
1034 system.cpu0.l2cache.ReadExReq_hits::cpu0.data 971762 # number of ReadExReq hits
1035 system.cpu0.l2cache.ReadExReq_hits::total 971762 # number of ReadExReq hits
1036 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9224160 # number of ReadCleanReq hits
1037 system.cpu0.l2cache.ReadCleanReq_hits::total 9224160 # number of ReadCleanReq hits
1038 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2947596 # number of ReadSharedReq hits
1039 system.cpu0.l2cache.ReadSharedReq_hits::total 2947596 # number of ReadSharedReq hits
1040 system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 209682 # number of InvalidateReq hits
1041 system.cpu0.l2cache.InvalidateReq_hits::total 209682 # number of InvalidateReq hits
1042 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539317 # number of demand (read+write) hits
1043 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 165054 # number of demand (read+write) hits
1044 system.cpu0.l2cache.demand_hits::cpu0.inst 9224160 # number of demand (read+write) hits
1045 system.cpu0.l2cache.demand_hits::cpu0.data 3919358 # number of demand (read+write) hits
1046 system.cpu0.l2cache.demand_hits::total 13847889 # number of demand (read+write) hits
1047 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539317 # number of overall hits
1048 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 165054 # number of overall hits
1049 system.cpu0.l2cache.overall_hits::cpu0.inst 9224160 # number of overall hits
1050 system.cpu0.l2cache.overall_hits::cpu0.data 3919358 # number of overall hits
1051 system.cpu0.l2cache.overall_hits::total 13847889 # number of overall hits
1052 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21966 # number of ReadReq misses
1053 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10468 # number of ReadReq misses
1054 system.cpu0.l2cache.ReadReq_misses::total 32434 # number of ReadReq misses
1055 system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
1056 system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
1057 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257791 # number of UpgradeReq misses
1058 system.cpu0.l2cache.UpgradeReq_misses::total 257791 # number of UpgradeReq misses
1059 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202293 # number of SCUpgradeReq misses
1060 system.cpu0.l2cache.SCUpgradeReq_misses::total 202293 # number of SCUpgradeReq misses
1061 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
1062 system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
1063 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289245 # number of ReadExReq misses
1064 system.cpu0.l2cache.ReadExReq_misses::total 289245 # number of ReadExReq misses
1065 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 774834 # number of ReadCleanReq misses
1066 system.cpu0.l2cache.ReadCleanReq_misses::total 774834 # number of ReadCleanReq misses
1067 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1075153 # number of ReadSharedReq misses
1068 system.cpu0.l2cache.ReadSharedReq_misses::total 1075153 # number of ReadSharedReq misses
1069 system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597922 # number of InvalidateReq misses
1070 system.cpu0.l2cache.InvalidateReq_misses::total 597922 # number of InvalidateReq misses
1071 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21966 # number of demand (read+write) misses
1072 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10468 # number of demand (read+write) misses
1073 system.cpu0.l2cache.demand_misses::cpu0.inst 774834 # number of demand (read+write) misses
1074 system.cpu0.l2cache.demand_misses::cpu0.data 1364398 # number of demand (read+write) misses
1075 system.cpu0.l2cache.demand_misses::total 2171666 # number of demand (read+write) misses
1076 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21966 # number of overall misses
1077 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10468 # number of overall misses
1078 system.cpu0.l2cache.overall_misses::cpu0.inst 774834 # number of overall misses
1079 system.cpu0.l2cache.overall_misses::cpu0.data 1364398 # number of overall misses
1080 system.cpu0.l2cache.overall_misses::total 2171666 # number of overall misses
1081 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 715984000 # number of ReadReq miss cycles
1082 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 391759500 # number of ReadReq miss cycles
1083 system.cpu0.l2cache.ReadReq_miss_latency::total 1107743500 # number of ReadReq miss cycles
1084 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 860565000 # number of UpgradeReq miss cycles
1085 system.cpu0.l2cache.UpgradeReq_miss_latency::total 860565000 # number of UpgradeReq miss cycles
1086 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 334549500 # number of SCUpgradeReq miss cycles
1087 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 334549500 # number of SCUpgradeReq miss cycles
1088 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1814999 # number of SCUpgradeFailReq miss cycles
1089 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1814999 # number of SCUpgradeFailReq miss cycles
1090 system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15808379497 # number of ReadExReq miss cycles
1091 system.cpu0.l2cache.ReadExReq_miss_latency::total 15808379497 # number of ReadExReq miss cycles
1092 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 28621690500 # number of ReadCleanReq miss cycles
1093 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 28621690500 # number of ReadCleanReq miss cycles
1094 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40818686990 # number of ReadSharedReq miss cycles
1095 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40818686990 # number of ReadSharedReq miss cycles
1096 system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles
1097 system.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles
1098 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 715984000 # number of demand (read+write) miss cycles
1099 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 391759500 # number of demand (read+write) miss cycles
1100 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 28621690500 # number of demand (read+write) miss cycles
1101 system.cpu0.l2cache.demand_miss_latency::cpu0.data 56627066487 # number of demand (read+write) miss cycles
1102 system.cpu0.l2cache.demand_miss_latency::total 86356500487 # number of demand (read+write) miss cycles
1103 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 715984000 # number of overall miss cycles
1104 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 391759500 # number of overall miss cycles
1105 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 28621690500 # number of overall miss cycles
1106 system.cpu0.l2cache.overall_miss_latency::cpu0.data 56627066487 # number of overall miss cycles
1107 system.cpu0.l2cache.overall_miss_latency::total 86356500487 # number of overall miss cycles
1108 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 561283 # number of ReadReq accesses(hits+misses)
1109 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175522 # number of ReadReq accesses(hits+misses)
1110 system.cpu0.l2cache.ReadReq_accesses::total 736805 # number of ReadReq accesses(hits+misses)
1111 system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3976191 # number of WritebackDirty accesses(hits+misses)
1112 system.cpu0.l2cache.WritebackDirty_accesses::total 3976191 # number of WritebackDirty accesses(hits+misses)
1113 system.cpu0.l2cache.WritebackClean_accesses::writebacks 12024319 # number of WritebackClean accesses(hits+misses)
1114 system.cpu0.l2cache.WritebackClean_accesses::total 12024319 # number of WritebackClean accesses(hits+misses)
1115 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257791 # number of UpgradeReq accesses(hits+misses)
1116 system.cpu0.l2cache.UpgradeReq_accesses::total 257791 # number of UpgradeReq accesses(hits+misses)
1117 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202293 # number of SCUpgradeReq accesses(hits+misses)
1118 system.cpu0.l2cache.SCUpgradeReq_accesses::total 202293 # number of SCUpgradeReq accesses(hits+misses)
1119 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
1120 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
1121 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1261007 # number of ReadExReq accesses(hits+misses)
1122 system.cpu0.l2cache.ReadExReq_accesses::total 1261007 # number of ReadExReq accesses(hits+misses)
1123 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9998994 # number of ReadCleanReq accesses(hits+misses)
1124 system.cpu0.l2cache.ReadCleanReq_accesses::total 9998994 # number of ReadCleanReq accesses(hits+misses)
1125 system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4022749 # number of ReadSharedReq accesses(hits+misses)
1126 system.cpu0.l2cache.ReadSharedReq_accesses::total 4022749 # number of ReadSharedReq accesses(hits+misses)
1127 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 807604 # number of InvalidateReq accesses(hits+misses)
1128 system.cpu0.l2cache.InvalidateReq_accesses::total 807604 # number of InvalidateReq accesses(hits+misses)
1129 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 561283 # number of demand (read+write) accesses
1130 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175522 # number of demand (read+write) accesses
1131 system.cpu0.l2cache.demand_accesses::cpu0.inst 9998994 # number of demand (read+write) accesses
1132 system.cpu0.l2cache.demand_accesses::cpu0.data 5283756 # number of demand (read+write) accesses
1133 system.cpu0.l2cache.demand_accesses::total 16019555 # number of demand (read+write) accesses
1134 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 561283 # number of overall (read+write) accesses
1135 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175522 # number of overall (read+write) accesses
1136 system.cpu0.l2cache.overall_accesses::cpu0.inst 9998994 # number of overall (read+write) accesses
1137 system.cpu0.l2cache.overall_accesses::cpu0.data 5283756 # number of overall (read+write) accesses
1138 system.cpu0.l2cache.overall_accesses::total 16019555 # number of overall (read+write) accesses
1139 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for ReadReq accesses
1140 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059639 # miss rate for ReadReq accesses
1141 system.cpu0.l2cache.ReadReq_miss_rate::total 0.044020 # miss rate for ReadReq accesses
1142 system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
1143 system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
1144 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1145 system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1146 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1147 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1148 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1149 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1150 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229376 # miss rate for ReadExReq accesses
1151 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.229376 # miss rate for ReadExReq accesses
1152 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.077491 # miss rate for ReadCleanReq accesses
1153 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.077491 # miss rate for ReadCleanReq accesses
1154 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267268 # miss rate for ReadSharedReq accesses
1155 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267268 # miss rate for ReadSharedReq accesses
1156 system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.740365 # miss rate for InvalidateReq accesses
1157 system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.740365 # miss rate for InvalidateReq accesses
1158 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for demand accesses
1159 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059639 # miss rate for demand accesses
1160 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.077491 # miss rate for demand accesses
1161 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258225 # miss rate for demand accesses
1162 system.cpu0.l2cache.demand_miss_rate::total 0.135563 # miss rate for demand accesses
1163 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for overall accesses
1164 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059639 # miss rate for overall accesses
1165 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.077491 # miss rate for overall accesses
1166 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258225 # miss rate for overall accesses
1167 system.cpu0.l2cache.overall_miss_rate::total 0.135563 # miss rate for overall accesses
1168 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average ReadReq miss latency
1169 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37424.484142 # average ReadReq miss latency
1170 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34153.773818 # average ReadReq miss latency
1171 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3338.227479 # average UpgradeReq miss latency
1172 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3338.227479 # average UpgradeReq miss latency
1173 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1653.786834 # average SCUpgradeReq miss latency
1174 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1653.786834 # average SCUpgradeReq miss latency
1175 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 453749.750000 # average SCUpgradeFailReq miss latency
1176 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 453749.750000 # average SCUpgradeFailReq miss latency
1177 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54653.942149 # average ReadExReq miss latency
1178 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54653.942149 # average ReadExReq miss latency
1179 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36939.125671 # average ReadCleanReq miss latency
1180 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36939.125671 # average ReadCleanReq miss latency
1181 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37965.468161 # average ReadSharedReq miss latency
1182 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37965.468161 # average ReadSharedReq miss latency
1183 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.173936 # average InvalidateReq miss latency
1184 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.173936 # average InvalidateReq miss latency
1185 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency
1186 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency
1187 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency
1188 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency
1189 system.cpu0.l2cache.demand_avg_miss_latency::total 39765.093015 # average overall miss latency
1190 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency
1191 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency
1192 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency
1193 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency
1194 system.cpu0.l2cache.overall_avg_miss_latency::total 39765.093015 # average overall miss latency
1195 system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked
1196 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1197 system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1198 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1199 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked
1200 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1201 system.cpu0.l2cache.unused_prefetches 48917 # number of HardPF blocks evicted w/o reference
1202 system.cpu0.l2cache.writebacks::writebacks 1795601 # number of writebacks
1203 system.cpu0.l2cache.writebacks::total 1795601 # number of writebacks
1204 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits
1205 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 90 # number of ReadReq MSHR hits
1206 system.cpu0.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
1207 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10129 # number of ReadExReq MSHR hits
1208 system.cpu0.l2cache.ReadExReq_mshr_hits::total 10129 # number of ReadExReq MSHR hits
1209 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits
1210 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1211 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 992 # number of ReadSharedReq MSHR hits
1212 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 992 # number of ReadSharedReq MSHR hits
1213 system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits
1214 system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
1215 system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits
1216 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 90 # number of demand (read+write) MSHR hits
1217 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
1218 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11121 # number of demand (read+write) MSHR hits
1219 system.cpu0.l2cache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits
1220 system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits
1221 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 90 # number of overall MSHR hits
1222 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
1223 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11121 # number of overall MSHR hits
1224 system.cpu0.l2cache.overall_mshr_hits::total 11245 # number of overall MSHR hits
1225 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21943 # number of ReadReq MSHR misses
1226 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10378 # number of ReadReq MSHR misses
1227 system.cpu0.l2cache.ReadReq_mshr_misses::total 32321 # number of ReadReq MSHR misses
1228 system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
1229 system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
1230 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of HardPFReq MSHR misses
1231 system.cpu0.l2cache.HardPFReq_mshr_misses::total 836449 # number of HardPFReq MSHR misses
1232 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257791 # number of UpgradeReq MSHR misses
1233 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257791 # number of UpgradeReq MSHR misses
1234 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202293 # number of SCUpgradeReq MSHR misses
1235 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202293 # number of SCUpgradeReq MSHR misses
1236 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
1237 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
1238 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279116 # number of ReadExReq MSHR misses
1239 system.cpu0.l2cache.ReadExReq_mshr_misses::total 279116 # number of ReadExReq MSHR misses
1240 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 774823 # number of ReadCleanReq MSHR misses
1241 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 774823 # number of ReadCleanReq MSHR misses
1242 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074161 # number of ReadSharedReq MSHR misses
1243 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074161 # number of ReadSharedReq MSHR misses
1244 system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 597920 # number of InvalidateReq MSHR misses
1245 system.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses
1246 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses
1247 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses
1248 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses
1249 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353277 # number of demand (read+write) MSHR misses
1250 system.cpu0.l2cache.demand_mshr_misses::total 2160421 # number of demand (read+write) MSHR misses
1251 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21943 # number of overall MSHR misses
1252 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses
1253 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 774823 # number of overall MSHR misses
1254 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353277 # number of overall MSHR misses
1255 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of overall MSHR misses
1256 system.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses
1257 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
1258 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
1259 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable
1260 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
1261 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
1262 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
1263 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
1264 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses
1265 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles
1266 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles
1267 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles
1268 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles
1269 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles
1270 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles
1271 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles
1272 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles
1273 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles
1274 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles
1275 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles
1276 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles
1277 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles
1278 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles
1279 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles
1280 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles
1281 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles
1282 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles
1283 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles
1284 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles
1285 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles
1286 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles
1287 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles
1288 system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles
1289 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles
1290 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles
1291 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles
1292 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles
1293 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles
1294 system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles
1295 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles
1296 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles
1297 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles
1298 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles
1299 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles
1300 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles
1301 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses
1302 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses
1303 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses
1304 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
1305 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1306 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1307 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1308 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1309 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1310 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1311 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1312 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1313 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1314 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses
1315 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses
1316 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses
1317 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses
1318 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses
1319 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses
1320 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses
1321 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses
1322 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses
1323 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses
1324 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses
1325 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses
1326 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses
1327 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses
1328 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses
1329 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses
1330 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses
1331 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1332 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses
1333 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency
1334 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency
1335 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency
1336 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency
1337 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency
1338 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency
1339 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency
1340 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency
1341 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency
1342 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency
1343 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency
1344 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency
1345 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency
1346 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency
1347 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency
1348 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency
1349 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency
1350 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency
1351 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency
1352 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
1353 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
1354 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
1355 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
1356 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency
1357 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
1358 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
1359 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
1360 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
1361 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency
1362 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency
1363 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency
1364 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency
1365 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency
1366 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency
1367 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency
1368 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency
1369 system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter.
1370 system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1371 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1372 system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter.
1373 system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1374 system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1375 system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1376 system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution
1377 system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution
1378 system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1379 system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution
1380 system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution
1381 system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution
1382 system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution
1383 system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution
1384 system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution
1385 system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
1386 system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution
1387 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution
1388 system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution
1389 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
1390 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
1391 system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution
1392 system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution
1393 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution
1394 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution
1395 system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution
1396 system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution
1397 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes)
1398 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes)
1399 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes)
1400 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes)
1401 system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes)
1402 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes)
1403 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes)
1404 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes)
1405 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes)
1406 system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes)
1407 system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count)
1408 system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes)
1409 system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram
1410 system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram
1411 system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram
1412 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1413 system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram
1414 system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram
1415 system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram
1416 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1417 system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1418 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1419 system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram
1420 system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks)
1421 system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1422 system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks)
1423 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1424 system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks)
1425 system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1426 system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks)
1427 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1428 system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks)
1429 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1430 system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks)
1431 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1432 system.cpu1.branchPred.lookups 106657949 # Number of BP lookups
1433 system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted
1434 system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect
1435 system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups
1436 system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits
1437 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1438 system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage
1439 system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target.
1440 system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions.
1441 system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups.
1442 system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits.
1443 system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses.
1444 system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches.
1445 system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1446 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1447 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1448 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1449 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1450 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1451 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1452 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1453 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1454 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1455 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1456 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1457 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1458 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1459 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1460 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1461 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1462 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1463 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1464 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1465 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1466 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1467 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1468 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1469 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1470 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1471 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1472 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1473 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1474 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1475 system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1476 system.cpu1.dtb.walker.walks 277975 # Table walker walks requested
1477 system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors
1478 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate
1479 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate
1480 system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency
1481 system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1482 system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency
1483 system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency
1484 system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency
1485 system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency
1486 system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency
1487 system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency
1488 system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency
1489 system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency
1490 system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency
1491 system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency
1492 system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency
1493 system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
1494 system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
1495 system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
1496 system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency
1497 system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution
1498 system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution
1499 system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution
1500 system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated
1501 system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated
1502 system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated
1503 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst
1504 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1505 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst
1506 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst
1507 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1508 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst
1509 system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst
1510 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1511 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1512 system.cpu1.dtb.read_hits 85144665 # DTB read hits
1513 system.cpu1.dtb.read_misses 232605 # DTB read misses
1514 system.cpu1.dtb.write_hits 73861979 # DTB write hits
1515 system.cpu1.dtb.write_misses 45370 # DTB write misses
1516 system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1517 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1518 system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
1519 system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
1520 system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB
1521 system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
1522 system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch
1523 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1524 system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions
1525 system.cpu1.dtb.read_accesses 85377270 # DTB read accesses
1526 system.cpu1.dtb.write_accesses 73907349 # DTB write accesses
1527 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1528 system.cpu1.dtb.hits 159006644 # DTB hits
1529 system.cpu1.dtb.misses 277975 # DTB misses
1530 system.cpu1.dtb.accesses 159284619 # DTB accesses
1531 system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1532 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1533 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1534 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1535 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1536 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1537 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1538 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1539 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1540 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1541 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1542 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1543 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1544 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1545 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1546 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1547 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1548 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1549 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1550 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1551 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1552 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1553 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1554 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1555 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1556 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1557 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1558 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1559 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1560 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1561 system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1562 system.cpu1.itb.walker.walks 63204 # Table walker walks requested
1563 system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors
1564 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate
1565 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate
1566 system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency
1567 system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1568 system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency
1569 system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency
1570 system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency
1571 system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency
1572 system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency
1573 system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency
1574 system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency
1575 system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency
1576 system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency
1577 system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency
1578 system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency
1579 system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
1580 system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1581 system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
1582 system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency
1583 system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution
1584 system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution
1585 system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution
1586 system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated
1587 system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated
1588 system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated
1589 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1590 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst
1591 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst
1592 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1593 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst
1594 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst
1595 system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst
1596 system.cpu1.itb.inst_hits 184175570 # ITB inst hits
1597 system.cpu1.itb.inst_misses 63204 # ITB inst misses
1598 system.cpu1.itb.read_hits 0 # DTB read hits
1599 system.cpu1.itb.read_misses 0 # DTB read misses
1600 system.cpu1.itb.write_hits 0 # DTB write hits
1601 system.cpu1.itb.write_misses 0 # DTB write misses
1602 system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1603 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1604 system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
1605 system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
1606 system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB
1607 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1608 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1609 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1610 system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions
1611 system.cpu1.itb.read_accesses 0 # DTB read accesses
1612 system.cpu1.itb.write_accesses 0 # DTB write accesses
1613 system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses
1614 system.cpu1.itb.hits 184175570 # DTB hits
1615 system.cpu1.itb.misses 63204 # DTB misses
1616 system.cpu1.itb.accesses 184238774 # DTB accesses
1617 system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions
1618 system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state
1619 system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state
1620 system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state
1621 system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state
1622 system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state
1623 system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state
1624 system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
1625 system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state
1626 system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
1627 system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
1628 system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state
1629 system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1630 system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state
1631 system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state
1632 system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states
1633 system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states
1634 system.cpu1.numCycles 798693745 # number of cpu cycles simulated
1635 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1636 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1637 system.cpu1.committedInsts 398322797 # Number of instructions committed
1638 system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed
1639 system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit
1640 system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching
1641 system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1642 system.cpu1.cpi 2.005142 # CPI: cycles per instruction
1643 system.cpu1.ipc 0.498718 # IPC: instructions per cycle
1644 system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1645 system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction
1646 system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction
1647 system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction
1648 system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction
1649 system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction
1650 system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction
1651 system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction
1652 system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction
1653 system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction
1654 system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction
1655 system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction
1656 system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction
1657 system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction
1658 system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction
1659 system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction
1660 system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction
1661 system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction
1662 system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction
1663 system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction
1664 system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction
1665 system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction
1666 system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction
1667 system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction
1668 system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction
1669 system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction
1670 system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction
1671 system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction
1672 system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction
1673 system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction
1674 system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction
1675 system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction
1676 system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction
1677 system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction
1678 system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction
1679 system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction
1680 system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1681 system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1682 system.cpu1.op_class_0::total 474376671 # Class of committed instruction
1683 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1684 system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed
1685 system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked
1686 system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped
1687 system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1688 system.cpu1.dcache.tags.replacements 5132038 # number of replacements
1689 system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use
1690 system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks.
1691 system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks.
1692 system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks.
1693 system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit.
1694 system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor
1695 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy
1696 system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy
1697 system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1698 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
1699 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
1700 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
1701 system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1702 system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses
1703 system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses
1704 system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1705 system.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits
1706 system.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits
1707 system.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits
1708 system.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits
1709 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits
1710 system.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits
1711 system.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits
1712 system.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits
1713 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits
1714 system.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits
1715 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits
1716 system.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits
1717 system.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits
1718 system.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits
1719 system.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits
1720 system.cpu1.dcache.overall_hits::total 147592391 # number of overall hits
1721 system.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses
1722 system.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses
1723 system.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses
1724 system.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses
1725 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses
1726 system.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses
1727 system.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses
1728 system.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses
1729 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses
1730 system.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses
1731 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses
1732 system.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses
1733 system.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses
1734 system.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses
1735 system.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses
1736 system.cpu1.dcache.overall_misses::total 6353870 # number of overall misses
1737 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles
1738 system.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles
1739 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles
1740 system.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles
1741 system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles
1742 system.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles
1743 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles
1744 system.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles
1745 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles
1746 system.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles
1747 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles
1748 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles
1749 system.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles
1750 system.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles
1751 system.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles
1752 system.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles
1753 system.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses)
1754 system.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses)
1755 system.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses)
1756 system.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses)
1757 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses)
1758 system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses)
1759 system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses)
1760 system.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses)
1761 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses)
1762 system.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses)
1763 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses)
1764 system.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses)
1765 system.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses
1766 system.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses
1767 system.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses
1768 system.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses
1769 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses
1770 system.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses
1771 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses
1772 system.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses
1773 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses
1774 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses
1775 system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses
1776 system.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses
1777 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses
1778 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses
1779 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses
1780 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses
1781 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses
1782 system.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses
1783 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses
1784 system.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses
1785 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency
1786 system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency
1787 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency
1788 system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency
1789 system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency
1790 system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency
1791 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency
1792 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency
1793 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency
1794 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency
1795 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1796 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1797 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency
1798 system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency
1799 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency
1800 system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency
1801 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1802 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1803 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1804 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1805 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1806 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1807 system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks
1808 system.cpu1.dcache.writebacks::total 5132050 # number of writebacks
1809 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits
1810 system.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits
1811 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits
1812 system.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits
1813 system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits
1814 system.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits
1815 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits
1816 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits
1817 system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits
1818 system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
1819 system.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits
1820 system.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits
1821 system.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits
1822 system.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits
1823 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses
1824 system.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses
1825 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses
1826 system.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses
1827 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses
1828 system.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses
1829 system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses
1830 system.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses
1831 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses
1832 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses
1833 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses
1834 system.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses
1835 system.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses
1836 system.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses
1837 system.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses
1838 system.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses
1839 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
1840 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable
1841 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
1842 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
1843 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
1844 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses
1845 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles
1846 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles
1847 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles
1848 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles
1849 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles
1850 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles
1851 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles
1852 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles
1853 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles
1854 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles
1855 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles
1856 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles
1857 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles
1858 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles
1859 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles
1860 system.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles
1861 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles
1862 system.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles
1863 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles
1864 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles
1865 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles
1866 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles
1867 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses
1868 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses
1869 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses
1870 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses
1871 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses
1872 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses
1873 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses
1874 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses
1875 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses
1876 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses
1877 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses
1878 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses
1879 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses
1880 system.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses
1881 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses
1882 system.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses
1883 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency
1884 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency
1885 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency
1886 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency
1887 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency
1888 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency
1889 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency
1890 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency
1891 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency
1892 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency
1893 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency
1894 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency
1895 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1896 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1897 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency
1898 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency
1899 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency
1900 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency
1901 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency
1902 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency
1903 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency
1904 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency
1905 system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1906 system.cpu1.icache.tags.replacements 8722673 # number of replacements
1907 system.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use
1908 system.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks.
1909 system.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks.
1910 system.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks.
1911 system.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit.
1912 system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor
1913 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy
1914 system.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy
1915 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1916 system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
1917 system.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
1918 system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
1919 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1920 system.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses
1921 system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses
1922 system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1923 system.cpu1.icache.ReadReq_hits::cpu1.inst 175283400 # number of ReadReq hits
1924 system.cpu1.icache.ReadReq_hits::total 175283400 # number of ReadReq hits
1925 system.cpu1.icache.demand_hits::cpu1.inst 175283400 # number of demand (read+write) hits
1926 system.cpu1.icache.demand_hits::total 175283400 # number of demand (read+write) hits
1927 system.cpu1.icache.overall_hits::cpu1.inst 175283400 # number of overall hits
1928 system.cpu1.icache.overall_hits::total 175283400 # number of overall hits
1929 system.cpu1.icache.ReadReq_misses::cpu1.inst 8723185 # number of ReadReq misses
1930 system.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses
1931 system.cpu1.icache.demand_misses::cpu1.inst 8723185 # number of demand (read+write) misses
1932 system.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses
1933 system.cpu1.icache.overall_misses::cpu1.inst 8723185 # number of overall misses
1934 system.cpu1.icache.overall_misses::total 8723185 # number of overall misses
1935 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 89772651500 # number of ReadReq miss cycles
1936 system.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles
1937 system.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles
1938 system.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles
1939 system.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles
1940 system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles
1941 system.cpu1.icache.ReadReq_accesses::cpu1.inst 184006585 # number of ReadReq accesses(hits+misses)
1942 system.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses)
1943 system.cpu1.icache.demand_accesses::cpu1.inst 184006585 # number of demand (read+write) accesses
1944 system.cpu1.icache.demand_accesses::total 184006585 # number of demand (read+write) accesses
1945 system.cpu1.icache.overall_accesses::cpu1.inst 184006585 # number of overall (read+write) accesses
1946 system.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses
1947 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.047407 # miss rate for ReadReq accesses
1948 system.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses
1949 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.047407 # miss rate for demand accesses
1950 system.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses
1951 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.047407 # miss rate for overall accesses
1952 system.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses
1953 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency
1954 system.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency
1955 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
1956 system.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency
1957 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
1958 system.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency
1959 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1960 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1961 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1962 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1963 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1964 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1965 system.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks
1966 system.cpu1.icache.writebacks::total 8722673 # number of writebacks
1967 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses
1968 system.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses
1969 system.cpu1.icache.demand_mshr_misses::cpu1.inst 8723185 # number of demand (read+write) MSHR misses
1970 system.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses
1971 system.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses
1972 system.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses
1973 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
1974 system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable
1975 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
1976 system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses
1977 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles
1978 system.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles
1979 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles
1980 system.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles
1981 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles
1982 system.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles
1983 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9620500 # number of ReadReq MSHR uncacheable cycles
1984 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles
1985 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # number of overall MSHR uncacheable cycles
1986 system.cpu1.icache.overall_mshr_uncacheable_latency::total 9620500 # number of overall MSHR uncacheable cycles
1987 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for ReadReq accesses
1988 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.047407 # mshr miss rate for ReadReq accesses
1989 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for demand accesses
1990 system.cpu1.icache.demand_mshr_miss_rate::total 0.047407 # mshr miss rate for demand accesses
1991 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for overall accesses
1992 system.cpu1.icache.overall_mshr_miss_rate::total 0.047407 # mshr miss rate for overall accesses
1993 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average ReadReq mshr miss latency
1994 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9791.269932 # average ReadReq mshr miss latency
1995 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
1996 system.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
1997 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
1998 system.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
1999 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency
2000 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency
2001 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency
2002 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency
2003 system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2004 system.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued
2005 system.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified
2006 system.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue
2007 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2008 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2009 system.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing
2010 system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2011 system.cpu1.l2cache.tags.replacements 2217652 # number of replacements
2012 system.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use
2013 system.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks.
2014 system.cpu1.l2cache.tags.sampled_refs 2233219 # Sample count of references to valid blocks.
2015 system.cpu1.l2cache.tags.avg_refs 5.690987 # Average number of references to valid blocks.
2016 system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2017 system.cpu1.l2cache.tags.occ_blocks::writebacks 12703.923602 # Average occupied blocks per requestor
2018 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.973948 # Average occupied blocks per requestor
2019 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.153172 # Average occupied blocks per requestor
2020 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 317.528681 # Average occupied blocks per requestor
2021 system.cpu1.l2cache.tags.occ_percent::writebacks 0.775386 # Average percentage of cache occupancy
2022 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001890 # Average percentage of cache occupancy
2023 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000925 # Average percentage of cache occupancy
2024 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019380 # Average percentage of cache occupancy
2025 system.cpu1.l2cache.tags.occ_percent::total 0.797582 # Average percentage of cache occupancy
2026 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 287 # Occupied blocks per task id
2027 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id
2028 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id
2029 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id
2030 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 84 # Occupied blocks per task id
2031 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id
2032 system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
2033 system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
2034 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id
2035 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
2036 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
2037 system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id
2038 system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id
2039 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id
2040 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id
2041 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id
2042 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id
2043 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id
2044 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id
2045 system.cpu1.l2cache.tags.tag_accesses 477362276 # Number of tag accesses
2046 system.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses
2047 system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2048 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532002 # number of ReadReq hits
2049 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159372 # number of ReadReq hits
2050 system.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits
2051 system.cpu1.l2cache.WritebackDirty_hits::writebacks 3201676 # number of WritebackDirty hits
2052 system.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits
2053 system.cpu1.l2cache.WritebackClean_hits::writebacks 10651334 # number of WritebackClean hits
2054 system.cpu1.l2cache.WritebackClean_hits::total 10651334 # number of WritebackClean hits
2055 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 860878 # number of ReadExReq hits
2056 system.cpu1.l2cache.ReadExReq_hits::total 860878 # number of ReadExReq hits
2057 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8051210 # number of ReadCleanReq hits
2058 system.cpu1.l2cache.ReadCleanReq_hits::total 8051210 # number of ReadCleanReq hits
2059 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2757056 # number of ReadSharedReq hits
2060 system.cpu1.l2cache.ReadSharedReq_hits::total 2757056 # number of ReadSharedReq hits
2061 system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173091 # number of InvalidateReq hits
2062 system.cpu1.l2cache.InvalidateReq_hits::total 173091 # number of InvalidateReq hits
2063 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532002 # number of demand (read+write) hits
2064 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159372 # number of demand (read+write) hits
2065 system.cpu1.l2cache.demand_hits::cpu1.inst 8051210 # number of demand (read+write) hits
2066 system.cpu1.l2cache.demand_hits::cpu1.data 3617934 # number of demand (read+write) hits
2067 system.cpu1.l2cache.demand_hits::total 12360518 # number of demand (read+write) hits
2068 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532002 # number of overall hits
2069 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159372 # number of overall hits
2070 system.cpu1.l2cache.overall_hits::cpu1.inst 8051210 # number of overall hits
2071 system.cpu1.l2cache.overall_hits::cpu1.data 3617934 # number of overall hits
2072 system.cpu1.l2cache.overall_hits::total 12360518 # number of overall hits
2073 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21589 # number of ReadReq misses
2074 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10425 # number of ReadReq misses
2075 system.cpu1.l2cache.ReadReq_misses::total 32014 # number of ReadReq misses
2076 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206575 # number of UpgradeReq misses
2077 system.cpu1.l2cache.UpgradeReq_misses::total 206575 # number of UpgradeReq misses
2078 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199341 # number of SCUpgradeReq misses
2079 system.cpu1.l2cache.SCUpgradeReq_misses::total 199341 # number of SCUpgradeReq misses
2080 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
2081 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
2082 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 222346 # number of ReadExReq misses
2083 system.cpu1.l2cache.ReadExReq_misses::total 222346 # number of ReadExReq misses
2084 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 671975 # number of ReadCleanReq misses
2085 system.cpu1.l2cache.ReadCleanReq_misses::total 671975 # number of ReadCleanReq misses
2086 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 945788 # number of ReadSharedReq misses
2087 system.cpu1.l2cache.ReadSharedReq_misses::total 945788 # number of ReadSharedReq misses
2088 system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266132 # number of InvalidateReq misses
2089 system.cpu1.l2cache.InvalidateReq_misses::total 266132 # number of InvalidateReq misses
2090 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21589 # number of demand (read+write) misses
2091 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10425 # number of demand (read+write) misses
2092 system.cpu1.l2cache.demand_misses::cpu1.inst 671975 # number of demand (read+write) misses
2093 system.cpu1.l2cache.demand_misses::cpu1.data 1168134 # number of demand (read+write) misses
2094 system.cpu1.l2cache.demand_misses::total 1872123 # number of demand (read+write) misses
2095 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21589 # number of overall misses
2096 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10425 # number of overall misses
2097 system.cpu1.l2cache.overall_misses::cpu1.inst 671975 # number of overall misses
2098 system.cpu1.l2cache.overall_misses::cpu1.data 1168134 # number of overall misses
2099 system.cpu1.l2cache.overall_misses::total 1872123 # number of overall misses
2100 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 733662000 # number of ReadReq miss cycles
2101 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 446226000 # number of ReadReq miss cycles
2102 system.cpu1.l2cache.ReadReq_miss_latency::total 1179888000 # number of ReadReq miss cycles
2103 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 870385500 # number of UpgradeReq miss cycles
2104 system.cpu1.l2cache.UpgradeReq_miss_latency::total 870385500 # number of UpgradeReq miss cycles
2105 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 311325000 # number of SCUpgradeReq miss cycles
2106 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 311325000 # number of SCUpgradeReq miss cycles
2107 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1930000 # number of SCUpgradeFailReq miss cycles
2108 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1930000 # number of SCUpgradeFailReq miss cycles
2109 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11310487497 # number of ReadExReq miss cycles
2110 system.cpu1.l2cache.ReadExReq_miss_latency::total 11310487497 # number of ReadExReq miss cycles
2111 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 23715219500 # number of ReadCleanReq miss cycles
2112 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 23715219500 # number of ReadCleanReq miss cycles
2113 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36332241992 # number of ReadSharedReq miss cycles
2114 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36332241992 # number of ReadSharedReq miss cycles
2115 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 733662000 # number of demand (read+write) miss cycles
2116 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 446226000 # number of demand (read+write) miss cycles
2117 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23715219500 # number of demand (read+write) miss cycles
2118 system.cpu1.l2cache.demand_miss_latency::cpu1.data 47642729489 # number of demand (read+write) miss cycles
2119 system.cpu1.l2cache.demand_miss_latency::total 72537836989 # number of demand (read+write) miss cycles
2120 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 733662000 # number of overall miss cycles
2121 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 446226000 # number of overall miss cycles
2122 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23715219500 # number of overall miss cycles
2123 system.cpu1.l2cache.overall_miss_latency::cpu1.data 47642729489 # number of overall miss cycles
2124 system.cpu1.l2cache.overall_miss_latency::total 72537836989 # number of overall miss cycles
2125 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 553591 # number of ReadReq accesses(hits+misses)
2126 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169797 # number of ReadReq accesses(hits+misses)
2127 system.cpu1.l2cache.ReadReq_accesses::total 723388 # number of ReadReq accesses(hits+misses)
2128 system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3201676 # number of WritebackDirty accesses(hits+misses)
2129 system.cpu1.l2cache.WritebackDirty_accesses::total 3201676 # number of WritebackDirty accesses(hits+misses)
2130 system.cpu1.l2cache.WritebackClean_accesses::writebacks 10651334 # number of WritebackClean accesses(hits+misses)
2131 system.cpu1.l2cache.WritebackClean_accesses::total 10651334 # number of WritebackClean accesses(hits+misses)
2132 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206575 # number of UpgradeReq accesses(hits+misses)
2133 system.cpu1.l2cache.UpgradeReq_accesses::total 206575 # number of UpgradeReq accesses(hits+misses)
2134 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199341 # number of SCUpgradeReq accesses(hits+misses)
2135 system.cpu1.l2cache.SCUpgradeReq_accesses::total 199341 # number of SCUpgradeReq accesses(hits+misses)
2136 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
2137 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
2138 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1083224 # number of ReadExReq accesses(hits+misses)
2139 system.cpu1.l2cache.ReadExReq_accesses::total 1083224 # number of ReadExReq accesses(hits+misses)
2140 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8723185 # number of ReadCleanReq accesses(hits+misses)
2141 system.cpu1.l2cache.ReadCleanReq_accesses::total 8723185 # number of ReadCleanReq accesses(hits+misses)
2142 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3702844 # number of ReadSharedReq accesses(hits+misses)
2143 system.cpu1.l2cache.ReadSharedReq_accesses::total 3702844 # number of ReadSharedReq accesses(hits+misses)
2144 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439223 # number of InvalidateReq accesses(hits+misses)
2145 system.cpu1.l2cache.InvalidateReq_accesses::total 439223 # number of InvalidateReq accesses(hits+misses)
2146 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 553591 # number of demand (read+write) accesses
2147 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169797 # number of demand (read+write) accesses
2148 system.cpu1.l2cache.demand_accesses::cpu1.inst 8723185 # number of demand (read+write) accesses
2149 system.cpu1.l2cache.demand_accesses::cpu1.data 4786068 # number of demand (read+write) accesses
2150 system.cpu1.l2cache.demand_accesses::total 14232641 # number of demand (read+write) accesses
2151 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 553591 # number of overall (read+write) accesses
2152 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169797 # number of overall (read+write) accesses
2153 system.cpu1.l2cache.overall_accesses::cpu1.inst 8723185 # number of overall (read+write) accesses
2154 system.cpu1.l2cache.overall_accesses::cpu1.data 4786068 # number of overall (read+write) accesses
2155 system.cpu1.l2cache.overall_accesses::total 14232641 # number of overall (read+write) accesses
2156 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for ReadReq accesses
2157 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061397 # miss rate for ReadReq accesses
2158 system.cpu1.l2cache.ReadReq_miss_rate::total 0.044256 # miss rate for ReadReq accesses
2159 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2160 system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2161 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2162 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2163 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2164 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2165 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.205263 # miss rate for ReadExReq accesses
2166 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.205263 # miss rate for ReadExReq accesses
2167 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077033 # miss rate for ReadCleanReq accesses
2168 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077033 # miss rate for ReadCleanReq accesses
2169 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255422 # miss rate for ReadSharedReq accesses
2170 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255422 # miss rate for ReadSharedReq accesses
2171 system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.605915 # miss rate for InvalidateReq accesses
2172 system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.605915 # miss rate for InvalidateReq accesses
2173 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for demand accesses
2174 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061397 # miss rate for demand accesses
2175 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077033 # miss rate for demand accesses
2176 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244070 # miss rate for demand accesses
2177 system.cpu1.l2cache.demand_miss_rate::total 0.131537 # miss rate for demand accesses
2178 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for overall accesses
2179 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061397 # miss rate for overall accesses
2180 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077033 # miss rate for overall accesses
2181 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244070 # miss rate for overall accesses
2182 system.cpu1.l2cache.overall_miss_rate::total 0.131537 # miss rate for overall accesses
2183 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average ReadReq miss latency
2184 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42803.453237 # average ReadReq miss latency
2185 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36855.375773 # average ReadReq miss latency
2186 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4213.411594 # average UpgradeReq miss latency
2187 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4213.411594 # average UpgradeReq miss latency
2188 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1561.771036 # average SCUpgradeReq miss latency
2189 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1561.771036 # average SCUpgradeReq miss latency
2190 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 643333.333333 # average SCUpgradeFailReq miss latency
2191 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 643333.333333 # average SCUpgradeFailReq miss latency
2192 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50868.859782 # average ReadExReq miss latency
2193 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50868.859782 # average ReadExReq miss latency
2194 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35291.818148 # average ReadCleanReq miss latency
2195 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35291.818148 # average ReadCleanReq miss latency
2196 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38414.784277 # average ReadSharedReq miss latency
2197 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38414.784277 # average ReadSharedReq miss latency
2198 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
2199 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
2200 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
2201 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
2202 system.cpu1.l2cache.demand_avg_miss_latency::total 38746.298715 # average overall miss latency
2203 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
2204 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
2205 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
2206 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
2207 system.cpu1.l2cache.overall_avg_miss_latency::total 38746.298715 # average overall miss latency
2208 system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2209 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2210 system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2211 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2212 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2213 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2214 system.cpu1.l2cache.unused_prefetches 44670 # number of HardPF blocks evicted w/o reference
2215 system.cpu1.l2cache.writebacks::writebacks 1164875 # number of writebacks
2216 system.cpu1.l2cache.writebacks::total 1164875 # number of writebacks
2217 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 19 # number of ReadReq MSHR hits
2218 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 106 # number of ReadReq MSHR hits
2219 system.cpu1.l2cache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits
2220 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8703 # number of ReadExReq MSHR hits
2221 system.cpu1.l2cache.ReadExReq_mshr_hits::total 8703 # number of ReadExReq MSHR hits
2222 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
2223 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2224 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 710 # number of ReadSharedReq MSHR hits
2225 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 710 # number of ReadSharedReq MSHR hits
2226 system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 19 # number of demand (read+write) MSHR hits
2227 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 106 # number of demand (read+write) MSHR hits
2228 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2229 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9413 # number of demand (read+write) MSHR hits
2230 system.cpu1.l2cache.demand_mshr_hits::total 9539 # number of demand (read+write) MSHR hits
2231 system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 19 # number of overall MSHR hits
2232 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 106 # number of overall MSHR hits
2233 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2234 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9413 # number of overall MSHR hits
2235 system.cpu1.l2cache.overall_mshr_hits::total 9539 # number of overall MSHR hits
2236 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21570 # number of ReadReq MSHR misses
2237 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10319 # number of ReadReq MSHR misses
2238 system.cpu1.l2cache.ReadReq_mshr_misses::total 31889 # number of ReadReq MSHR misses
2239 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of HardPFReq MSHR misses
2240 system.cpu1.l2cache.HardPFReq_mshr_misses::total 740053 # number of HardPFReq MSHR misses
2241 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206575 # number of UpgradeReq MSHR misses
2242 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206575 # number of UpgradeReq MSHR misses
2243 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199341 # number of SCUpgradeReq MSHR misses
2244 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199341 # number of SCUpgradeReq MSHR misses
2245 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2246 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2247 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 213643 # number of ReadExReq MSHR misses
2248 system.cpu1.l2cache.ReadExReq_mshr_misses::total 213643 # number of ReadExReq MSHR misses
2249 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 671974 # number of ReadCleanReq MSHR misses
2250 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 671974 # number of ReadCleanReq MSHR misses
2251 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 945078 # number of ReadSharedReq MSHR misses
2252 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 945078 # number of ReadSharedReq MSHR misses
2253 system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266132 # number of InvalidateReq MSHR misses
2254 system.cpu1.l2cache.InvalidateReq_mshr_misses::total 266132 # number of InvalidateReq MSHR misses
2255 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21570 # number of demand (read+write) MSHR misses
2256 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10319 # number of demand (read+write) MSHR misses
2257 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 671974 # number of demand (read+write) MSHR misses
2258 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1158721 # number of demand (read+write) MSHR misses
2259 system.cpu1.l2cache.demand_mshr_misses::total 1862584 # number of demand (read+write) MSHR misses
2260 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21570 # number of overall MSHR misses
2261 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10319 # number of overall MSHR misses
2262 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 671974 # number of overall MSHR misses
2263 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1158721 # number of overall MSHR misses
2264 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of overall MSHR misses
2265 system.cpu1.l2cache.overall_mshr_misses::total 2602637 # number of overall MSHR misses
2266 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
2267 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
2268 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5425 # number of ReadReq MSHR uncacheable
2269 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
2270 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
2271 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
2272 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
2273 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10691 # number of overall MSHR uncacheable misses
2274 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of ReadReq MSHR miss cycles
2275 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 382493500 # number of ReadReq MSHR miss cycles
2276 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 986284000 # number of ReadReq MSHR miss cycles
2277 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of HardPFReq MSHR miss cycles
2278 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 37370954173 # number of HardPFReq MSHR miss cycles
2279 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3898631994 # number of UpgradeReq MSHR miss cycles
2280 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3898631994 # number of UpgradeReq MSHR miss cycles
2281 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3073389997 # number of SCUpgradeReq MSHR miss cycles
2282 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3073389997 # number of SCUpgradeReq MSHR miss cycles
2283 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1642000 # number of SCUpgradeFailReq MSHR miss cycles
2284 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1642000 # number of SCUpgradeFailReq MSHR miss cycles
2285 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8857402997 # number of ReadExReq MSHR miss cycles
2286 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8857402997 # number of ReadExReq MSHR miss cycles
2287 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19683346000 # number of ReadCleanReq MSHR miss cycles
2288 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles
2289 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles
2290 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles
2291 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles
2292 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles
2293 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles
2294 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles
2295 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles
2296 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles
2297 system.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles
2298 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles
2299 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles
2300 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles
2301 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles
2302 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles
2303 system.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles
2304 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles
2305 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles
2306 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles
2307 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles
2308 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles
2309 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles
2310 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses
2311 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses
2312 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses
2313 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2314 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2315 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2316 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2317 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2318 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2319 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2320 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2321 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses
2322 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses
2323 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses
2324 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses
2325 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses
2326 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses
2327 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses
2328 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses
2329 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses
2330 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses
2331 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses
2332 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses
2333 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses
2334 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses
2335 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses
2336 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses
2337 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses
2338 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2339 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses
2340 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency
2341 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency
2342 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency
2343 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency
2344 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency
2345 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency
2346 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency
2347 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency
2348 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency
2349 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency
2350 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency
2351 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency
2352 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency
2353 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency
2354 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency
2355 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency
2356 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency
2357 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency
2358 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency
2359 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
2360 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
2361 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
2362 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
2363 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency
2364 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
2365 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
2366 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
2367 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
2368 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency
2369 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency
2370 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency
2371 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency
2372 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency
2373 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency
2374 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency
2375 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency
2376 system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter.
2377 system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2378 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2379 system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter.
2380 system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2381 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2382 system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2383 system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution
2384 system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution
2385 system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution
2386 system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution
2387 system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution
2388 system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution
2389 system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution
2390 system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution
2391 system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
2392 system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution
2393 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution
2394 system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution
2395 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
2396 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
2397 system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution
2398 system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution
2399 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution
2400 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution
2401 system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution
2402 system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution
2403 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes)
2404 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes)
2405 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes)
2406 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes)
2407 system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes)
2408 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes)
2409 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes)
2410 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes)
2411 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes)
2412 system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes)
2413 system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count)
2414 system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes)
2415 system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram
2416 system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram
2417 system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram
2418 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2419 system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram
2420 system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram
2421 system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram
2422 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2423 system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2424 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2425 system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram
2426 system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks)
2427 system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2428 system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks)
2429 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2430 system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks)
2431 system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2432 system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks)
2433 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2434 system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks)
2435 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2436 system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks)
2437 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2438 system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2439 system.iobus.trans_dist::ReadReq 40225 # Transaction distribution
2440 system.iobus.trans_dist::ReadResp 40225 # Transaction distribution
2441 system.iobus.trans_dist::WriteReq 136513 # Transaction distribution
2442 system.iobus.trans_dist::WriteResp 136513 # Transaction distribution
2443 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes)
2444 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2445 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2446 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2447 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2448 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2449 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2450 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2451 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2452 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2453 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2454 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2455 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2456 system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes)
2457 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
2458 system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
2459 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2460 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2461 system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes)
2462 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes)
2463 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2464 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2465 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2466 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2467 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2468 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2469 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2470 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2471 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2472 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2473 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2474 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2475 system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes)
2476 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
2477 system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
2478 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2479 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2480 system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes)
2481 system.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks)
2482 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2483 system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
2484 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2485 system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
2486 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2487 system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2488 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2489 system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
2490 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2491 system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2492 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2493 system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
2494 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2495 system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
2496 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2497 system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
2498 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2499 system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
2500 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2501 system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
2502 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2503 system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks)
2504 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2505 system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks)
2506 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2507 system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks)
2508 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2509 system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks)
2510 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2511 system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks)
2512 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2513 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2514 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2515 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2516 system.iocache.tags.replacements 115597 # number of replacements
2517 system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use
2518 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2519 system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks.
2520 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2521 system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit.
2522 system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor
2523 system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor
2524 system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy
2525 system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy
2526 system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy
2527 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2528 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2529 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2530 system.iocache.tags.tag_accesses 1040910 # Number of tag accesses
2531 system.iocache.tags.data_accesses 1040910 # Number of data accesses
2532 system.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2533 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2534 system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
2535 system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
2536 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2537 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2538 system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2539 system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2540 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2541 system.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses
2542 system.iocache.demand_misses::total 115657 # number of demand (read+write) misses
2543 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2544 system.iocache.overall_misses::realview.ide 115617 # number of overall misses
2545 system.iocache.overall_misses::total 115657 # number of overall misses
2546 system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles
2547 system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles
2548 system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles
2549 system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2550 system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2551 system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles
2552 system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles
2553 system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles
2554 system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles
2555 system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles
2556 system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles
2557 system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles
2558 system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles
2559 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2560 system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
2561 system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
2562 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2563 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2564 system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2565 system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2566 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2567 system.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses
2568 system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses
2569 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2570 system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses
2571 system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses
2572 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2573 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2574 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2575 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2576 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2577 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2578 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2579 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2580 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2581 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2582 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2583 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2584 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2585 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency
2586 system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency
2587 system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency
2588 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2589 system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2590 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency
2591 system.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency
2592 system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
2593 system.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
2594 system.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency
2595 system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
2596 system.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
2597 system.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency
2598 system.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked
2599 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2600 system.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked
2601 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2602 system.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked
2603 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2604 system.iocache.writebacks::writebacks 106693 # number of writebacks
2605 system.iocache.writebacks::total 106693 # number of writebacks
2606 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2607 system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
2608 system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
2609 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2610 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2611 system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2612 system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2613 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2614 system.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses
2615 system.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses
2616 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2617 system.iocache.overall_mshr_misses::realview.ide 115617 # number of overall MSHR misses
2618 system.iocache.overall_mshr_misses::total 115657 # number of overall MSHR misses
2619 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles
2620 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1535756431 # number of ReadReq MSHR miss cycles
2621 system.iocache.ReadReq_mshr_miss_latency::total 1539102931 # number of ReadReq MSHR miss cycles
2622 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2623 system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2624 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7847855187 # number of WriteLineReq MSHR miss cycles
2625 system.iocache.WriteLineReq_mshr_miss_latency::total 7847855187 # number of WriteLineReq MSHR miss cycles
2626 system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles
2627 system.iocache.demand_mshr_miss_latency::realview.ide 9383611618 # number of demand (read+write) MSHR miss cycles
2628 system.iocache.demand_mshr_miss_latency::total 9387177118 # number of demand (read+write) MSHR miss cycles
2629 system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles
2630 system.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles
2631 system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles
2632 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2633 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2634 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2635 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2636 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2637 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2638 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2639 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2640 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2641 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2642 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2643 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2644 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2645 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency
2646 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172770.438857 # average ReadReq mshr miss latency
2647 system.iocache.ReadReq_avg_mshr_miss_latency::total 172429.187878 # average ReadReq mshr miss latency
2648 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2649 system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2650 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency
2651 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency
2652 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
2653 system.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
2654 system.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
2655 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
2656 system.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
2657 system.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
2658 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2659 system.l2c.tags.replacements 1609900 # number of replacements
2660 system.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use
2661 system.l2c.tags.total_refs 7484861 # Total number of references to valid blocks.
2662 system.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks.
2663 system.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks.
2664 system.l2c.tags.warmup_cycle 3329231500 # Cycle when the warmup percentage was hit.
2665 system.l2c.tags.occ_blocks::writebacks 10396.250510 # Average occupied blocks per requestor
2666 system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.300313 # Average occupied blocks per requestor
2667 system.l2c.tags.occ_blocks::cpu0.itb.walker 163.171529 # Average occupied blocks per requestor
2668 system.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor
2669 system.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor
2670 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor
2671 system.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor
2672 system.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor
2673 system.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor
2674 system.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor
2675 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11426.785423 # Average occupied blocks per requestor
2676 system.l2c.tags.occ_percent::writebacks 0.158634 # Average percentage of cache occupancy
2677 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002644 # Average percentage of cache occupancy
2678 system.l2c.tags.occ_percent::cpu0.itb.walker 0.002490 # Average percentage of cache occupancy
2679 system.l2c.tags.occ_percent::cpu0.inst 0.074771 # Average percentage of cache occupancy
2680 system.l2c.tags.occ_percent::cpu0.data 0.195435 # Average percentage of cache occupancy
2681 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146971 # Average percentage of cache occupancy
2682 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004438 # Average percentage of cache occupancy
2683 system.l2c.tags.occ_percent::cpu1.itb.walker 0.004707 # Average percentage of cache occupancy
2684 system.l2c.tags.occ_percent::cpu1.inst 0.053940 # Average percentage of cache occupancy
2685 system.l2c.tags.occ_percent::cpu1.data 0.175828 # Average percentage of cache occupancy
2686 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.174359 # Average percentage of cache occupancy
2687 system.l2c.tags.occ_percent::total 0.994217 # Average percentage of cache occupancy
2688 system.l2c.tags.occ_task_id_blocks::1022 10593 # Occupied blocks per task id
2689 system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id
2690 system.l2c.tags.occ_task_id_blocks::1024 51026 # Occupied blocks per task id
2691 system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id
2692 system.l2c.tags.age_task_id_blocks_1022::3 461 # Occupied blocks per task id
2693 system.l2c.tags.age_task_id_blocks_1022::4 10006 # Occupied blocks per task id
2694 system.l2c.tags.age_task_id_blocks_1023::4 251 # Occupied blocks per task id
2695 system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
2696 system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
2697 system.l2c.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id
2698 system.l2c.tags.age_task_id_blocks_1024::3 4614 # Occupied blocks per task id
2699 system.l2c.tags.age_task_id_blocks_1024::4 44401 # Occupied blocks per task id
2700 system.l2c.tags.occ_task_id_percent::1022 0.161636 # Percentage of cache occupancy per task id
2701 system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id
2702 system.l2c.tags.occ_task_id_percent::1024 0.778595 # Percentage of cache occupancy per task id
2703 system.l2c.tags.tag_accesses 82772579 # Number of tag accesses
2704 system.l2c.tags.data_accesses 82772579 # Number of data accesses
2705 system.l2c.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2706 system.l2c.WritebackDirty_hits::writebacks 2960473 # number of WritebackDirty hits
2707 system.l2c.WritebackDirty_hits::total 2960473 # number of WritebackDirty hits
2708 system.l2c.UpgradeReq_hits::cpu0.data 214775 # number of UpgradeReq hits
2709 system.l2c.UpgradeReq_hits::cpu1.data 151269 # number of UpgradeReq hits
2710 system.l2c.UpgradeReq_hits::total 366044 # number of UpgradeReq hits
2711 system.l2c.SCUpgradeReq_hits::cpu0.data 56896 # number of SCUpgradeReq hits
2712 system.l2c.SCUpgradeReq_hits::cpu1.data 55474 # number of SCUpgradeReq hits
2713 system.l2c.SCUpgradeReq_hits::total 112370 # number of SCUpgradeReq hits
2714 system.l2c.ReadExReq_hits::cpu0.data 67148 # number of ReadExReq hits
2715 system.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits
2716 system.l2c.ReadExReq_hits::total 118780 # number of ReadExReq hits
2717 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 14203 # number of ReadSharedReq hits
2718 system.l2c.ReadSharedReq_hits::cpu0.itb.walker 6226 # number of ReadSharedReq hits
2719 system.l2c.ReadSharedReq_hits::cpu0.inst 695308 # number of ReadSharedReq hits
2720 system.l2c.ReadSharedReq_hits::cpu0.data 685955 # number of ReadSharedReq hits
2721 system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 328258 # number of ReadSharedReq hits
2722 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12341 # number of ReadSharedReq hits
2723 system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4684 # number of ReadSharedReq hits
2724 system.l2c.ReadSharedReq_hits::cpu1.inst 616265 # number of ReadSharedReq hits
2725 system.l2c.ReadSharedReq_hits::cpu1.data 560248 # number of ReadSharedReq hits
2726 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 290505 # number of ReadSharedReq hits
2727 system.l2c.ReadSharedReq_hits::total 3213993 # number of ReadSharedReq hits
2728 system.l2c.InvalidateReq_hits::cpu0.data 136732 # number of InvalidateReq hits
2729 system.l2c.InvalidateReq_hits::cpu1.data 122714 # number of InvalidateReq hits
2730 system.l2c.InvalidateReq_hits::total 259446 # number of InvalidateReq hits
2731 system.l2c.demand_hits::cpu0.dtb.walker 14203 # number of demand (read+write) hits
2732 system.l2c.demand_hits::cpu0.itb.walker 6226 # number of demand (read+write) hits
2733 system.l2c.demand_hits::cpu0.inst 695308 # number of demand (read+write) hits
2734 system.l2c.demand_hits::cpu0.data 753103 # number of demand (read+write) hits
2735 system.l2c.demand_hits::cpu0.l2cache.prefetcher 328258 # number of demand (read+write) hits
2736 system.l2c.demand_hits::cpu1.dtb.walker 12341 # number of demand (read+write) hits
2737 system.l2c.demand_hits::cpu1.itb.walker 4684 # number of demand (read+write) hits
2738 system.l2c.demand_hits::cpu1.inst 616265 # number of demand (read+write) hits
2739 system.l2c.demand_hits::cpu1.data 611880 # number of demand (read+write) hits
2740 system.l2c.demand_hits::cpu1.l2cache.prefetcher 290505 # number of demand (read+write) hits
2741 system.l2c.demand_hits::total 3332773 # number of demand (read+write) hits
2742 system.l2c.overall_hits::cpu0.dtb.walker 14203 # number of overall hits
2743 system.l2c.overall_hits::cpu0.itb.walker 6226 # number of overall hits
2744 system.l2c.overall_hits::cpu0.inst 695308 # number of overall hits
2745 system.l2c.overall_hits::cpu0.data 753103 # number of overall hits
2746 system.l2c.overall_hits::cpu0.l2cache.prefetcher 328258 # number of overall hits
2747 system.l2c.overall_hits::cpu1.dtb.walker 12341 # number of overall hits
2748 system.l2c.overall_hits::cpu1.itb.walker 4684 # number of overall hits
2749 system.l2c.overall_hits::cpu1.inst 616265 # number of overall hits
2750 system.l2c.overall_hits::cpu1.data 611880 # number of overall hits
2751 system.l2c.overall_hits::cpu1.l2cache.prefetcher 290505 # number of overall hits
2752 system.l2c.overall_hits::total 3332773 # number of overall hits
2753 system.l2c.UpgradeReq_misses::cpu0.data 20148 # number of UpgradeReq misses
2754 system.l2c.UpgradeReq_misses::cpu1.data 22532 # number of UpgradeReq misses
2755 system.l2c.UpgradeReq_misses::total 42680 # number of UpgradeReq misses
2756 system.l2c.SCUpgradeReq_misses::cpu0.data 632 # number of SCUpgradeReq misses
2757 system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses
2758 system.l2c.SCUpgradeReq_misses::total 1574 # number of SCUpgradeReq misses
2759 system.l2c.ReadExReq_misses::cpu0.data 82382 # number of ReadExReq misses
2760 system.l2c.ReadExReq_misses::cpu1.data 53449 # number of ReadExReq misses
2761 system.l2c.ReadExReq_misses::total 135831 # number of ReadExReq misses
2762 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq misses
2763 system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1618 # number of ReadSharedReq misses
2764 system.l2c.ReadSharedReq_misses::cpu0.inst 79514 # number of ReadSharedReq misses
2765 system.l2c.ReadSharedReq_misses::cpu0.data 147489 # number of ReadSharedReq misses
2766 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq misses
2767 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq misses
2768 system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2403 # number of ReadSharedReq misses
2769 system.l2c.ReadSharedReq_misses::cpu1.inst 55709 # number of ReadSharedReq misses
2770 system.l2c.ReadSharedReq_misses::cpu1.data 138924 # number of ReadSharedReq misses
2771 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq misses
2772 system.l2c.ReadSharedReq_misses::total 938667 # number of ReadSharedReq misses
2773 system.l2c.InvalidateReq_misses::cpu0.data 422083 # number of InvalidateReq misses
2774 system.l2c.InvalidateReq_misses::cpu1.data 110180 # number of InvalidateReq misses
2775 system.l2c.InvalidateReq_misses::total 532263 # number of InvalidateReq misses
2776 system.l2c.demand_misses::cpu0.dtb.walker 2080 # number of demand (read+write) misses
2777 system.l2c.demand_misses::cpu0.itb.walker 1618 # number of demand (read+write) misses
2778 system.l2c.demand_misses::cpu0.inst 79514 # number of demand (read+write) misses
2779 system.l2c.demand_misses::cpu0.data 229871 # number of demand (read+write) misses
2780 system.l2c.demand_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) misses
2781 system.l2c.demand_misses::cpu1.dtb.walker 2595 # number of demand (read+write) misses
2782 system.l2c.demand_misses::cpu1.itb.walker 2403 # number of demand (read+write) misses
2783 system.l2c.demand_misses::cpu1.inst 55709 # number of demand (read+write) misses
2784 system.l2c.demand_misses::cpu1.data 192373 # number of demand (read+write) misses
2785 system.l2c.demand_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) misses
2786 system.l2c.demand_misses::total 1074498 # number of demand (read+write) misses
2787 system.l2c.overall_misses::cpu0.dtb.walker 2080 # number of overall misses
2788 system.l2c.overall_misses::cpu0.itb.walker 1618 # number of overall misses
2789 system.l2c.overall_misses::cpu0.inst 79514 # number of overall misses
2790 system.l2c.overall_misses::cpu0.data 229871 # number of overall misses
2791 system.l2c.overall_misses::cpu0.l2cache.prefetcher 271925 # number of overall misses
2792 system.l2c.overall_misses::cpu1.dtb.walker 2595 # number of overall misses
2793 system.l2c.overall_misses::cpu1.itb.walker 2403 # number of overall misses
2794 system.l2c.overall_misses::cpu1.inst 55709 # number of overall misses
2795 system.l2c.overall_misses::cpu1.data 192373 # number of overall misses
2796 system.l2c.overall_misses::cpu1.l2cache.prefetcher 236410 # number of overall misses
2797 system.l2c.overall_misses::total 1074498 # number of overall misses
2798 system.l2c.UpgradeReq_miss_latency::cpu0.data 146038500 # number of UpgradeReq miss cycles
2799 system.l2c.UpgradeReq_miss_latency::cpu1.data 131790500 # number of UpgradeReq miss cycles
2800 system.l2c.UpgradeReq_miss_latency::total 277829000 # number of UpgradeReq miss cycles
2801 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 10352000 # number of SCUpgradeReq miss cycles
2802 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8549500 # number of SCUpgradeReq miss cycles
2803 system.l2c.SCUpgradeReq_miss_latency::total 18901500 # number of SCUpgradeReq miss cycles
2804 system.l2c.ReadExReq_miss_latency::cpu0.data 8710976500 # number of ReadExReq miss cycles
2805 system.l2c.ReadExReq_miss_latency::cpu1.data 5673543000 # number of ReadExReq miss cycles
2806 system.l2c.ReadExReq_miss_latency::total 14384519500 # number of ReadExReq miss cycles
2807 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 219387000 # number of ReadSharedReq miss cycles
2808 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 170599500 # number of ReadSharedReq miss cycles
2809 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8581562500 # number of ReadSharedReq miss cycles
2810 system.l2c.ReadSharedReq_miss_latency::cpu0.data 16399499000 # number of ReadSharedReq miss cycles
2811 system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of ReadSharedReq miss cycles
2812 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257094000 # number of ReadSharedReq miss cycles
2813 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 237286000 # number of ReadSharedReq miss cycles
2814 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6184697999 # number of ReadSharedReq miss cycles
2815 system.l2c.ReadSharedReq_miss_latency::cpu1.data 15199077000 # number of ReadSharedReq miss cycles
2816 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of ReadSharedReq miss cycles
2817 system.l2c.ReadSharedReq_miss_latency::total 118434367320 # number of ReadSharedReq miss cycles
2818 system.l2c.demand_miss_latency::cpu0.dtb.walker 219387000 # number of demand (read+write) miss cycles
2819 system.l2c.demand_miss_latency::cpu0.itb.walker 170599500 # number of demand (read+write) miss cycles
2820 system.l2c.demand_miss_latency::cpu0.inst 8581562500 # number of demand (read+write) miss cycles
2821 system.l2c.demand_miss_latency::cpu0.data 25110475500 # number of demand (read+write) miss cycles
2822 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of demand (read+write) miss cycles
2823 system.l2c.demand_miss_latency::cpu1.dtb.walker 257094000 # number of demand (read+write) miss cycles
2824 system.l2c.demand_miss_latency::cpu1.itb.walker 237286000 # number of demand (read+write) miss cycles
2825 system.l2c.demand_miss_latency::cpu1.inst 6184697999 # number of demand (read+write) miss cycles
2826 system.l2c.demand_miss_latency::cpu1.data 20872620000 # number of demand (read+write) miss cycles
2827 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of demand (read+write) miss cycles
2828 system.l2c.demand_miss_latency::total 132818886820 # number of demand (read+write) miss cycles
2829 system.l2c.overall_miss_latency::cpu0.dtb.walker 219387000 # number of overall miss cycles
2830 system.l2c.overall_miss_latency::cpu0.itb.walker 170599500 # number of overall miss cycles
2831 system.l2c.overall_miss_latency::cpu0.inst 8581562500 # number of overall miss cycles
2832 system.l2c.overall_miss_latency::cpu0.data 25110475500 # number of overall miss cycles
2833 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of overall miss cycles
2834 system.l2c.overall_miss_latency::cpu1.dtb.walker 257094000 # number of overall miss cycles
2835 system.l2c.overall_miss_latency::cpu1.itb.walker 237286000 # number of overall miss cycles
2836 system.l2c.overall_miss_latency::cpu1.inst 6184697999 # number of overall miss cycles
2837 system.l2c.overall_miss_latency::cpu1.data 20872620000 # number of overall miss cycles
2838 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of overall miss cycles
2839 system.l2c.overall_miss_latency::total 132818886820 # number of overall miss cycles
2840 system.l2c.WritebackDirty_accesses::writebacks 2960473 # number of WritebackDirty accesses(hits+misses)
2841 system.l2c.WritebackDirty_accesses::total 2960473 # number of WritebackDirty accesses(hits+misses)
2842 system.l2c.UpgradeReq_accesses::cpu0.data 234923 # number of UpgradeReq accesses(hits+misses)
2843 system.l2c.UpgradeReq_accesses::cpu1.data 173801 # number of UpgradeReq accesses(hits+misses)
2844 system.l2c.UpgradeReq_accesses::total 408724 # number of UpgradeReq accesses(hits+misses)
2845 system.l2c.SCUpgradeReq_accesses::cpu0.data 57528 # number of SCUpgradeReq accesses(hits+misses)
2846 system.l2c.SCUpgradeReq_accesses::cpu1.data 56416 # number of SCUpgradeReq accesses(hits+misses)
2847 system.l2c.SCUpgradeReq_accesses::total 113944 # number of SCUpgradeReq accesses(hits+misses)
2848 system.l2c.ReadExReq_accesses::cpu0.data 149530 # number of ReadExReq accesses(hits+misses)
2849 system.l2c.ReadExReq_accesses::cpu1.data 105081 # number of ReadExReq accesses(hits+misses)
2850 system.l2c.ReadExReq_accesses::total 254611 # number of ReadExReq accesses(hits+misses)
2851 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16283 # number of ReadSharedReq accesses(hits+misses)
2852 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7844 # number of ReadSharedReq accesses(hits+misses)
2853 system.l2c.ReadSharedReq_accesses::cpu0.inst 774822 # number of ReadSharedReq accesses(hits+misses)
2854 system.l2c.ReadSharedReq_accesses::cpu0.data 833444 # number of ReadSharedReq accesses(hits+misses)
2855 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 600183 # number of ReadSharedReq accesses(hits+misses)
2856 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14936 # number of ReadSharedReq accesses(hits+misses)
2857 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7087 # number of ReadSharedReq accesses(hits+misses)
2858 system.l2c.ReadSharedReq_accesses::cpu1.inst 671974 # number of ReadSharedReq accesses(hits+misses)
2859 system.l2c.ReadSharedReq_accesses::cpu1.data 699172 # number of ReadSharedReq accesses(hits+misses)
2860 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 526915 # number of ReadSharedReq accesses(hits+misses)
2861 system.l2c.ReadSharedReq_accesses::total 4152660 # number of ReadSharedReq accesses(hits+misses)
2862 system.l2c.InvalidateReq_accesses::cpu0.data 558815 # number of InvalidateReq accesses(hits+misses)
2863 system.l2c.InvalidateReq_accesses::cpu1.data 232894 # number of InvalidateReq accesses(hits+misses)
2864 system.l2c.InvalidateReq_accesses::total 791709 # number of InvalidateReq accesses(hits+misses)
2865 system.l2c.demand_accesses::cpu0.dtb.walker 16283 # number of demand (read+write) accesses
2866 system.l2c.demand_accesses::cpu0.itb.walker 7844 # number of demand (read+write) accesses
2867 system.l2c.demand_accesses::cpu0.inst 774822 # number of demand (read+write) accesses
2868 system.l2c.demand_accesses::cpu0.data 982974 # number of demand (read+write) accesses
2869 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 600183 # number of demand (read+write) accesses
2870 system.l2c.demand_accesses::cpu1.dtb.walker 14936 # number of demand (read+write) accesses
2871 system.l2c.demand_accesses::cpu1.itb.walker 7087 # number of demand (read+write) accesses
2872 system.l2c.demand_accesses::cpu1.inst 671974 # number of demand (read+write) accesses
2873 system.l2c.demand_accesses::cpu1.data 804253 # number of demand (read+write) accesses
2874 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 526915 # number of demand (read+write) accesses
2875 system.l2c.demand_accesses::total 4407271 # number of demand (read+write) accesses
2876 system.l2c.overall_accesses::cpu0.dtb.walker 16283 # number of overall (read+write) accesses
2877 system.l2c.overall_accesses::cpu0.itb.walker 7844 # number of overall (read+write) accesses
2878 system.l2c.overall_accesses::cpu0.inst 774822 # number of overall (read+write) accesses
2879 system.l2c.overall_accesses::cpu0.data 982974 # number of overall (read+write) accesses
2880 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 600183 # number of overall (read+write) accesses
2881 system.l2c.overall_accesses::cpu1.dtb.walker 14936 # number of overall (read+write) accesses
2882 system.l2c.overall_accesses::cpu1.itb.walker 7087 # number of overall (read+write) accesses
2883 system.l2c.overall_accesses::cpu1.inst 671974 # number of overall (read+write) accesses
2884 system.l2c.overall_accesses::cpu1.data 804253 # number of overall (read+write) accesses
2885 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 526915 # number of overall (read+write) accesses
2886 system.l2c.overall_accesses::total 4407271 # number of overall (read+write) accesses
2887 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.085764 # miss rate for UpgradeReq accesses
2888 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129643 # miss rate for UpgradeReq accesses
2889 system.l2c.UpgradeReq_miss_rate::total 0.104423 # miss rate for UpgradeReq accesses
2890 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010986 # miss rate for SCUpgradeReq accesses
2891 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016697 # miss rate for SCUpgradeReq accesses
2892 system.l2c.SCUpgradeReq_miss_rate::total 0.013814 # miss rate for SCUpgradeReq accesses
2893 system.l2c.ReadExReq_miss_rate::cpu0.data 0.550940 # miss rate for ReadExReq accesses
2894 system.l2c.ReadExReq_miss_rate::cpu1.data 0.508646 # miss rate for ReadExReq accesses
2895 system.l2c.ReadExReq_miss_rate::total 0.533484 # miss rate for ReadExReq accesses
2896 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for ReadSharedReq accesses
2897 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.206272 # miss rate for ReadSharedReq accesses
2898 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102622 # miss rate for ReadSharedReq accesses
2899 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.176963 # miss rate for ReadSharedReq accesses
2900 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for ReadSharedReq accesses
2901 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for ReadSharedReq accesses
2902 system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339072 # miss rate for ReadSharedReq accesses
2903 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.082904 # miss rate for ReadSharedReq accesses
2904 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.198698 # miss rate for ReadSharedReq accesses
2905 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for ReadSharedReq accesses
2906 system.l2c.ReadSharedReq_miss_rate::total 0.226040 # miss rate for ReadSharedReq accesses
2907 system.l2c.InvalidateReq_miss_rate::cpu0.data 0.755318 # miss rate for InvalidateReq accesses
2908 system.l2c.InvalidateReq_miss_rate::cpu1.data 0.473091 # miss rate for InvalidateReq accesses
2909 system.l2c.InvalidateReq_miss_rate::total 0.672296 # miss rate for InvalidateReq accesses
2910 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for demand accesses
2911 system.l2c.demand_miss_rate::cpu0.itb.walker 0.206272 # miss rate for demand accesses
2912 system.l2c.demand_miss_rate::cpu0.inst 0.102622 # miss rate for demand accesses
2913 system.l2c.demand_miss_rate::cpu0.data 0.233853 # miss rate for demand accesses
2914 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for demand accesses
2915 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for demand accesses
2916 system.l2c.demand_miss_rate::cpu1.itb.walker 0.339072 # miss rate for demand accesses
2917 system.l2c.demand_miss_rate::cpu1.inst 0.082904 # miss rate for demand accesses
2918 system.l2c.demand_miss_rate::cpu1.data 0.239195 # miss rate for demand accesses
2919 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for demand accesses
2920 system.l2c.demand_miss_rate::total 0.243801 # miss rate for demand accesses
2921 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for overall accesses
2922 system.l2c.overall_miss_rate::cpu0.itb.walker 0.206272 # miss rate for overall accesses
2923 system.l2c.overall_miss_rate::cpu0.inst 0.102622 # miss rate for overall accesses
2924 system.l2c.overall_miss_rate::cpu0.data 0.233853 # miss rate for overall accesses
2925 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for overall accesses
2926 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for overall accesses
2927 system.l2c.overall_miss_rate::cpu1.itb.walker 0.339072 # miss rate for overall accesses
2928 system.l2c.overall_miss_rate::cpu1.inst 0.082904 # miss rate for overall accesses
2929 system.l2c.overall_miss_rate::cpu1.data 0.239195 # miss rate for overall accesses
2930 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for overall accesses
2931 system.l2c.overall_miss_rate::total 0.243801 # miss rate for overall accesses
2932 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7248.287671 # average UpgradeReq miss latency
2933 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5849.036925 # average UpgradeReq miss latency
2934 system.l2c.UpgradeReq_avg_miss_latency::total 6509.582943 # average UpgradeReq miss latency
2935 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16379.746835 # average SCUpgradeReq miss latency
2936 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9075.902335 # average SCUpgradeReq miss latency
2937 system.l2c.SCUpgradeReq_avg_miss_latency::total 12008.576874 # average SCUpgradeReq miss latency
2938 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 105738.832512 # average ReadExReq miss latency
2939 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106148.721211 # average ReadExReq miss latency
2940 system.l2c.ReadExReq_avg_miss_latency::total 105900.122211 # average ReadExReq miss latency
2941 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average ReadSharedReq miss latency
2942 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105438.504326 # average ReadSharedReq miss latency
2943 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107925.176698 # average ReadSharedReq miss latency
2944 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111191.336303 # average ReadSharedReq miss latency
2945 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average ReadSharedReq miss latency
2946 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average ReadSharedReq miss latency
2947 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 98745.734499 # average ReadSharedReq miss latency
2948 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111017.932453 # average ReadSharedReq miss latency
2949 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 109405.696640 # average ReadSharedReq miss latency
2950 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average ReadSharedReq miss latency
2951 system.l2c.ReadSharedReq_avg_miss_latency::total 126172.931743 # average ReadSharedReq miss latency
2952 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency
2953 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency
2954 system.l2c.demand_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency
2955 system.l2c.demand_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency
2956 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency
2957 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency
2958 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency
2959 system.l2c.demand_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency
2960 system.l2c.demand_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency
2961 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency
2962 system.l2c.demand_avg_miss_latency::total 123610.175933 # average overall miss latency
2963 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency
2964 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency
2965 system.l2c.overall_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency
2966 system.l2c.overall_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency
2967 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency
2968 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency
2969 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency
2970 system.l2c.overall_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency
2971 system.l2c.overall_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency
2972 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency
2973 system.l2c.overall_avg_miss_latency::total 123610.175933 # average overall miss latency
2974 system.l2c.blocked_cycles::no_mshrs 1362 # number of cycles access was blocked
2975 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2976 system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked
2977 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2978 system.l2c.avg_blocked_cycles::no_mshrs 104.769231 # average number of cycles each access was blocked
2979 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2980 system.l2c.writebacks::writebacks 1205906 # number of writebacks
2981 system.l2c.writebacks::total 1205906 # number of writebacks
2982 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 171 # number of ReadSharedReq MSHR hits
2983 system.l2c.ReadSharedReq_mshr_hits::cpu0.data 38 # number of ReadSharedReq MSHR hits
2984 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 160 # number of ReadSharedReq MSHR hits
2985 system.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits
2986 system.l2c.ReadSharedReq_mshr_hits::total 380 # number of ReadSharedReq MSHR hits
2987 system.l2c.demand_mshr_hits::cpu0.inst 171 # number of demand (read+write) MSHR hits
2988 system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
2989 system.l2c.demand_mshr_hits::cpu1.inst 160 # number of demand (read+write) MSHR hits
2990 system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits
2991 system.l2c.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits
2992 system.l2c.overall_mshr_hits::cpu0.inst 171 # number of overall MSHR hits
2993 system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
2994 system.l2c.overall_mshr_hits::cpu1.inst 160 # number of overall MSHR hits
2995 system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits
2996 system.l2c.overall_mshr_hits::total 380 # number of overall MSHR hits
2997 system.l2c.CleanEvict_mshr_misses::writebacks 74973 # number of CleanEvict MSHR misses
2998 system.l2c.CleanEvict_mshr_misses::total 74973 # number of CleanEvict MSHR misses
2999 system.l2c.UpgradeReq_mshr_misses::cpu0.data 20148 # number of UpgradeReq MSHR misses
3000 system.l2c.UpgradeReq_mshr_misses::cpu1.data 22532 # number of UpgradeReq MSHR misses
3001 system.l2c.UpgradeReq_mshr_misses::total 42680 # number of UpgradeReq MSHR misses
3002 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 632 # number of SCUpgradeReq MSHR misses
3003 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 942 # number of SCUpgradeReq MSHR misses
3004 system.l2c.SCUpgradeReq_mshr_misses::total 1574 # number of SCUpgradeReq MSHR misses
3005 system.l2c.ReadExReq_mshr_misses::cpu0.data 82382 # number of ReadExReq MSHR misses
3006 system.l2c.ReadExReq_mshr_misses::cpu1.data 53449 # number of ReadExReq MSHR misses
3007 system.l2c.ReadExReq_mshr_misses::total 135831 # number of ReadExReq MSHR misses
3008 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq MSHR misses
3009 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1618 # number of ReadSharedReq MSHR misses
3010 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 79343 # number of ReadSharedReq MSHR misses
3011 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 147451 # number of ReadSharedReq MSHR misses
3012 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq MSHR misses
3013 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq MSHR misses
3014 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2403 # number of ReadSharedReq MSHR misses
3015 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 55549 # number of ReadSharedReq MSHR misses
3016 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 138913 # number of ReadSharedReq MSHR misses
3017 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq MSHR misses
3018 system.l2c.ReadSharedReq_mshr_misses::total 938287 # number of ReadSharedReq MSHR misses
3019 system.l2c.InvalidateReq_mshr_misses::cpu0.data 422083 # number of InvalidateReq MSHR misses
3020 system.l2c.InvalidateReq_mshr_misses::cpu1.data 110180 # number of InvalidateReq MSHR misses
3021 system.l2c.InvalidateReq_mshr_misses::total 532263 # number of InvalidateReq MSHR misses
3022 system.l2c.demand_mshr_misses::cpu0.dtb.walker 2080 # number of demand (read+write) MSHR misses
3023 system.l2c.demand_mshr_misses::cpu0.itb.walker 1618 # number of demand (read+write) MSHR misses
3024 system.l2c.demand_mshr_misses::cpu0.inst 79343 # number of demand (read+write) MSHR misses
3025 system.l2c.demand_mshr_misses::cpu0.data 229833 # number of demand (read+write) MSHR misses
3026 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) MSHR misses
3027 system.l2c.demand_mshr_misses::cpu1.dtb.walker 2595 # number of demand (read+write) MSHR misses
3028 system.l2c.demand_mshr_misses::cpu1.itb.walker 2403 # number of demand (read+write) MSHR misses
3029 system.l2c.demand_mshr_misses::cpu1.inst 55549 # number of demand (read+write) MSHR misses
3030 system.l2c.demand_mshr_misses::cpu1.data 192362 # number of demand (read+write) MSHR misses
3031 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) MSHR misses
3032 system.l2c.demand_mshr_misses::total 1074118 # number of demand (read+write) MSHR misses
3033 system.l2c.overall_mshr_misses::cpu0.dtb.walker 2080 # number of overall MSHR misses
3034 system.l2c.overall_mshr_misses::cpu0.itb.walker 1618 # number of overall MSHR misses
3035 system.l2c.overall_mshr_misses::cpu0.inst 79343 # number of overall MSHR misses
3036 system.l2c.overall_mshr_misses::cpu0.data 229833 # number of overall MSHR misses
3037 system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of overall MSHR misses
3038 system.l2c.overall_mshr_misses::cpu1.dtb.walker 2595 # number of overall MSHR misses
3039 system.l2c.overall_mshr_misses::cpu1.itb.walker 2403 # number of overall MSHR misses
3040 system.l2c.overall_mshr_misses::cpu1.inst 55549 # number of overall MSHR misses
3041 system.l2c.overall_mshr_misses::cpu1.data 192362 # number of overall MSHR misses
3042 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of overall MSHR misses
3043 system.l2c.overall_mshr_misses::total 1074118 # number of overall MSHR misses
3044 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
3045 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
3046 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
3047 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5328 # number of ReadReq MSHR uncacheable
3048 system.l2c.ReadReq_mshr_uncacheable::total 42476 # number of ReadReq MSHR uncacheable
3049 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
3050 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
3051 system.l2c.WriteReq_mshr_uncacheable::total 37999 # number of WriteReq MSHR uncacheable
3052 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
3053 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
3054 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
3055 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10594 # number of overall MSHR uncacheable misses
3056 system.l2c.overall_mshr_uncacheable_misses::total 80475 # number of overall MSHR uncacheable misses
3057 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 406966500 # number of UpgradeReq MSHR miss cycles
3058 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 461692998 # number of UpgradeReq MSHR miss cycles
3059 system.l2c.UpgradeReq_mshr_miss_latency::total 868659498 # number of UpgradeReq MSHR miss cycles
3060 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15287999 # number of SCUpgradeReq MSHR miss cycles
3061 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22938500 # number of SCUpgradeReq MSHR miss cycles
3062 system.l2c.SCUpgradeReq_mshr_miss_latency::total 38226499 # number of SCUpgradeReq MSHR miss cycles
3063 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7887118579 # number of ReadExReq MSHR miss cycles
3064 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5139033541 # number of ReadExReq MSHR miss cycles
3065 system.l2c.ReadExReq_mshr_miss_latency::total 13026152120 # number of ReadExReq MSHR miss cycles
3066 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of ReadSharedReq MSHR miss cycles
3067 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154419500 # number of ReadSharedReq MSHR miss cycles
3068 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7774295554 # number of ReadSharedReq MSHR miss cycles
3069 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14921316255 # number of ReadSharedReq MSHR miss cycles
3070 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of ReadSharedReq MSHR miss cycles
3071 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of ReadSharedReq MSHR miss cycles
3072 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 213255501 # number of ReadSharedReq MSHR miss cycles
3073 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5614526528 # number of ReadSharedReq MSHR miss cycles
3074 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13808714201 # number of ReadSharedReq MSHR miss cycles
3075 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of ReadSharedReq MSHR miss cycles
3076 system.l2c.ReadSharedReq_mshr_miss_latency::total 109017709147 # number of ReadSharedReq MSHR miss cycles
3077 system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8734501501 # number of InvalidateReq MSHR miss cycles
3078 system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2122534500 # number of InvalidateReq MSHR miss cycles
3079 system.l2c.InvalidateReq_mshr_miss_latency::total 10857036001 # number of InvalidateReq MSHR miss cycles
3080 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of demand (read+write) MSHR miss cycles
3081 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154419500 # number of demand (read+write) MSHR miss cycles
3082 system.l2c.demand_mshr_miss_latency::cpu0.inst 7774295554 # number of demand (read+write) MSHR miss cycles
3083 system.l2c.demand_mshr_miss_latency::cpu0.data 22808434834 # number of demand (read+write) MSHR miss cycles
3084 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of demand (read+write) MSHR miss cycles
3085 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of demand (read+write) MSHR miss cycles
3086 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 213255501 # number of demand (read+write) MSHR miss cycles
3087 system.l2c.demand_mshr_miss_latency::cpu1.inst 5614526528 # number of demand (read+write) MSHR miss cycles
3088 system.l2c.demand_mshr_miss_latency::cpu1.data 18947747742 # number of demand (read+write) MSHR miss cycles
3089 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of demand (read+write) MSHR miss cycles
3090 system.l2c.demand_mshr_miss_latency::total 122043861267 # number of demand (read+write) MSHR miss cycles
3091 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of overall MSHR miss cycles
3092 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154419500 # number of overall MSHR miss cycles
3093 system.l2c.overall_mshr_miss_latency::cpu0.inst 7774295554 # number of overall MSHR miss cycles
3094 system.l2c.overall_mshr_miss_latency::cpu0.data 22808434834 # number of overall MSHR miss cycles
3095 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of overall MSHR miss cycles
3096 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of overall MSHR miss cycles
3097 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 213255501 # number of overall MSHR miss cycles
3098 system.l2c.overall_mshr_miss_latency::cpu1.inst 5614526528 # number of overall MSHR miss cycles
3099 system.l2c.overall_mshr_miss_latency::cpu1.data 18947747742 # number of overall MSHR miss cycles
3100 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of overall MSHR miss cycles
3101 system.l2c.overall_mshr_miss_latency::total 122043861267 # number of overall MSHR miss cycles
3102 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 303607000 # number of ReadReq MSHR uncacheable cycles
3103 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5434541500 # number of ReadReq MSHR uncacheable cycles
3104 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6865000 # number of ReadReq MSHR uncacheable cycles
3105 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 495854501 # number of ReadReq MSHR uncacheable cycles
3106 system.l2c.ReadReq_mshr_uncacheable_latency::total 6240868001 # number of ReadReq MSHR uncacheable cycles
3107 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 303607000 # number of overall MSHR uncacheable cycles
3108 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5434541500 # number of overall MSHR uncacheable cycles
3109 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6865000 # number of overall MSHR uncacheable cycles
3110 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495854501 # number of overall MSHR uncacheable cycles
3111 system.l2c.overall_mshr_uncacheable_latency::total 6240868001 # number of overall MSHR uncacheable cycles
3112 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3113 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3114 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.085764 # mshr miss rate for UpgradeReq accesses
3115 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129643 # mshr miss rate for UpgradeReq accesses
3116 system.l2c.UpgradeReq_mshr_miss_rate::total 0.104423 # mshr miss rate for UpgradeReq accesses
3117 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010986 # mshr miss rate for SCUpgradeReq accesses
3118 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016697 # mshr miss rate for SCUpgradeReq accesses
3119 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013814 # mshr miss rate for SCUpgradeReq accesses
3120 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550940 # mshr miss rate for ReadExReq accesses
3121 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508646 # mshr miss rate for ReadExReq accesses
3122 system.l2c.ReadExReq_mshr_miss_rate::total 0.533484 # mshr miss rate for ReadExReq accesses
3123 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for ReadSharedReq accesses
3124 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for ReadSharedReq accesses
3125 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for ReadSharedReq accesses
3126 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.176918 # mshr miss rate for ReadSharedReq accesses
3127 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for ReadSharedReq accesses
3128 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for ReadSharedReq accesses
3129 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for ReadSharedReq accesses
3130 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for ReadSharedReq accesses
3131 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses
3132 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses
3133 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses
3134 system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses
3135 system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses
3136 system.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses
3137 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses
3138 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses
3139 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses
3140 system.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses
3141 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses
3142 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses
3143 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses
3144 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses
3145 system.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses
3146 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses
3147 system.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses
3148 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses
3149 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses
3150 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses
3151 system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses
3152 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses
3153 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses
3154 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses
3155 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses
3156 system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses
3157 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses
3158 system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses
3159 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency
3160 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency
3161 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency
3162 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency
3163 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency
3164 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency
3165 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency
3166 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency
3167 system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency
3168 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency
3169 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency
3170 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency
3171 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency
3172 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency
3173 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency
3174 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency
3175 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency
3176 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency
3177 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency
3178 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency
3179 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency
3180 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency
3181 system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency
3182 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
3183 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
3184 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
3185 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
3186 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
3187 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
3188 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
3189 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
3190 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
3191 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
3192 system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
3193 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
3194 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
3195 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
3196 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
3197 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
3198 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
3199 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
3200 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
3201 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
3202 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
3203 system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
3204 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency
3205 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency
3206 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency
3207 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency
3208 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency
3209 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency
3210 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency
3211 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency
3212 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency
3213 system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency
3214 system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter.
3215 system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3216 system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3217 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3218 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3219 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3220 system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3221 system.membus.trans_dist::ReadReq 42476 # Transaction distribution
3222 system.membus.trans_dist::ReadResp 989688 # Transaction distribution
3223 system.membus.trans_dist::WriteReq 37999 # Transaction distribution
3224 system.membus.trans_dist::WriteResp 37999 # Transaction distribution
3225 system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution
3226 system.membus.trans_dist::CleanEvict 291937 # Transaction distribution
3227 system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution
3228 system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution
3229 system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
3230 system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
3231 system.membus.trans_dist::ReadExReq 150791 # Transaction distribution
3232 system.membus.trans_dist::ReadExResp 135122 # Transaction distribution
3233 system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution
3234 system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution
3235 system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution
3236 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes)
3237 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
3238 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes)
3239 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes)
3240 system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes)
3241 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes)
3242 system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes)
3243 system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes)
3244 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes)
3245 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
3246 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes)
3247 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes)
3248 system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes)
3249 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes)
3250 system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes)
3251 system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes)
3252 system.membus.snoops 586564 # Total snoops (count)
3253 system.membus.snoopTraffic 164864 # Total snoop traffic (bytes)
3254 system.membus.snoop_fanout::samples 2402773 # Request fanout histogram
3255 system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram
3256 system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram
3257 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3258 system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram
3259 system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram
3260 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3261 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3262 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3263 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3264 system.membus.snoop_fanout::total 2402773 # Request fanout histogram
3265 system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks)
3266 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3267 system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
3268 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3269 system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks)
3270 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3271 system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks)
3272 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3273 system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks)
3274 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3275 system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks)
3276 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3277 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3278 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3279 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3280 system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3281 system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3282 system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3283 system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3284 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3285 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3286 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3287 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3288 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3289 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3290 system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3291 system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3292 system.realview.ethernet.txBytes 966 # Bytes Transmitted
3293 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3294 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3295 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3296 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3297 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3298 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3299 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3300 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3301 system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
3302 system.realview.ethernet.totPackets 3 # Total Packets
3303 system.realview.ethernet.totBytes 966 # Total Bytes
3304 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
3305 system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
3306 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
3307 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3308 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
3309 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3310 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3311 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
3312 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3313 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3314 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
3315 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3316 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3317 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
3318 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3319 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3320 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
3321 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3322 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3323 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
3324 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3325 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3326 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3327 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3328 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3329 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3330 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3331 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3332 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3333 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3334 system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3335 system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3336 system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3337 system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3338 system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3339 system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3340 system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3341 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3342 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3343 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3344 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3345 system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3346 system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3347 system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3348 system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3349 system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3350 system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3351 system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3352 system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3353 system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3354 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3355 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3356 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3357 system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter.
3358 system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3359 system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3360 system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter.
3361 system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3362 system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3363 system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3364 system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution
3365 system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution
3366 system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution
3367 system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution
3368 system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution
3369 system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
3370 system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution
3371 system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution
3372 system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution
3373 system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution
3374 system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
3375 system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
3376 system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution
3377 system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution
3378 system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution
3379 system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution
3380 system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution
3381 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes)
3382 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes)
3383 system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes)
3384 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes)
3385 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes)
3386 system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes)
3387 system.toL2Bus.snoops 3035429 # Total snoops (count)
3388 system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes)
3389 system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram
3390 system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram
3391 system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram
3392 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3393 system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram
3394 system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram
3395 system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram
3396 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3397 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3398 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3399 system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram
3400 system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks)
3401 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3402 system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks)
3403 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3404 system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks)
3405 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3406 system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks)
3407 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3409 ---------- End Simulation Statistics ----------
projects / gem5.git / blob