tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM64
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=MinorCPU
 115 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=system.cpu.branchPred
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 decodeCycleInput=true
 121 decodeInputBufferSize=3
 122 decodeInputWidth=2
 123 decodeToExecuteForwardDelay=1
 124 default_p_state=UNDEFINED
 125 do_checkpoint_insts=true
 126 do_quiesce=true
 127 do_statistics_insts=true
 128 dstage2_mmu=system.cpu.dstage2_mmu
 129 dtb=system.cpu.dtb
 130 enableIdling=true
 131 eventq_index=0
 132 executeAllowEarlyMemoryIssue=true
 133 executeBranchDelay=1
 134 executeCommitLimit=2
 135 executeCycleInput=true
 136 executeFuncUnits=system.cpu.executeFuncUnits
 137 executeInputBufferSize=7
 138 executeInputWidth=2
 139 executeIssueLimit=2
 140 executeLSQMaxStoreBufferStoresPerCycle=2
 141 executeLSQRequestsQueueSize=1
 142 executeLSQStoreBufferSize=5
 143 executeLSQTransfersQueueSize=2
 144 executeMaxAccessesInMemory=2
 145 executeMemoryCommitLimit=1
 146 executeMemoryIssueLimit=1
 147 executeMemoryWidth=0
 148 executeSetTraceTimeOnCommit=true
 149 executeSetTraceTimeOnIssue=false
 150 fetch1FetchLimit=1
 151 fetch1LineSnapWidth=0
 152 fetch1LineWidth=0
 153 fetch1ToFetch2BackwardDelay=1
 154 fetch1ToFetch2ForwardDelay=1
 155 fetch2CycleInput=true
 156 fetch2InputBufferSize=2
 157 fetch2ToDecodeForwardDelay=1
 158 function_trace=false
 159 function_trace_start=0
 160 interrupts=system.cpu.interrupts
 161 isa=system.cpu.isa
 162 istage2_mmu=system.cpu.istage2_mmu
 163 itb=system.cpu.itb
 164 max_insts_all_threads=0
 165 max_insts_any_thread=0
 166 max_loads_all_threads=0
 167 max_loads_any_thread=0
 168 numThreads=1
 169 p_state_clk_gate_bins=20
 170 p_state_clk_gate_max=1000000000000
 171 p_state_clk_gate_min=1000
 172 power_model=Null
 173 profile=0
 174 progress_interval=0
 175 simpoint_start_insts=
 176 socket_id=0
 177 switched_out=false
 178 system=system
 179 threadPolicy=RoundRobin
 180 tracer=system.cpu.tracer
 181 workload=
 182 dcache_port=system.cpu.dcache.cpu_side
 183 icache_port=system.cpu.icache.cpu_side
 184
 185 [system.cpu.branchPred]
 186 type=TournamentBP
 187 BTBEntries=4096
 188 BTBTagSize=16
 189 RASSize=16
 190 choiceCtrBits=2
 191 choicePredictorSize=8192
 192 eventq_index=0
 193 globalCtrBits=2
 194 globalPredictorSize=8192
 195 indirectHashGHR=true
 196 indirectHashTargets=true
 197 indirectPathLength=3
 198 indirectSets=256
 199 indirectTagSize=16
 200 indirectWays=2
 201 instShiftAmt=2
 202 localCtrBits=2
 203 localHistoryTableSize=2048
 204 localPredictorSize=2048
 205 numThreads=1
 206 useIndirect=true
 207
 208 [system.cpu.dcache]
 209 type=Cache
 210 children=tags
 211 addr_ranges=0:18446744073709551615:0:0:0:0
 212 assoc=4
 213 clk_domain=system.cpu_clk_domain
 214 clusivity=mostly_incl
 215 default_p_state=UNDEFINED
 216 demand_mshr_reserve=1
 217 eventq_index=0
 218 hit_latency=2
 219 is_read_only=false
 220 max_miss_count=0
 221 mshrs=4
 222 p_state_clk_gate_bins=20
 223 p_state_clk_gate_max=1000000000000
 224 p_state_clk_gate_min=1000
 225 power_model=Null
 226 prefetch_on_access=false
 227 prefetcher=Null
 228 response_latency=2
 229 sequential_access=false
 230 size=32768
 231 system=system
 232 tags=system.cpu.dcache.tags
 233 tgts_per_mshr=20
 234 write_buffers=8
 235 writeback_clean=false
 236 cpu_side=system.cpu.dcache_port
 237 mem_side=system.cpu.toL2Bus.slave[1]
 238
 239 [system.cpu.dcache.tags]
 240 type=LRU
 241 assoc=4
 242 block_size=64
 243 clk_domain=system.cpu_clk_domain
 244 default_p_state=UNDEFINED
 245 eventq_index=0
 246 hit_latency=2
 247 p_state_clk_gate_bins=20
 248 p_state_clk_gate_max=1000000000000
 249 p_state_clk_gate_min=1000
 250 power_model=Null
 251 sequential_access=false
 252 size=32768
 253
 254 [system.cpu.dstage2_mmu]
 255 type=ArmStage2MMU
 256 children=stage2_tlb
 257 eventq_index=0
 258 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 259 sys=system
 260 tlb=system.cpu.dtb
 261
 262 [system.cpu.dstage2_mmu.stage2_tlb]
 263 type=ArmTLB
 264 children=walker
 265 eventq_index=0
 266 is_stage2=true
 267 size=32
 268 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 269
 270 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 271 type=ArmTableWalker
 272 clk_domain=system.cpu_clk_domain
 273 default_p_state=UNDEFINED
 274 eventq_index=0
 275 is_stage2=true
 276 num_squash_per_cycle=2
 277 p_state_clk_gate_bins=20
 278 p_state_clk_gate_max=1000000000000
 279 p_state_clk_gate_min=1000
 280 power_model=Null
 281 sys=system
 282
 283 [system.cpu.dtb]
 284 type=ArmTLB
 285 children=walker
 286 eventq_index=0
 287 is_stage2=false
 288 size=64
 289 walker=system.cpu.dtb.walker
 290
 291 [system.cpu.dtb.walker]
 292 type=ArmTableWalker
 293 clk_domain=system.cpu_clk_domain
 294 default_p_state=UNDEFINED
 295 eventq_index=0
 296 is_stage2=false
 297 num_squash_per_cycle=2
 298 p_state_clk_gate_bins=20
 299 p_state_clk_gate_max=1000000000000
 300 p_state_clk_gate_min=1000
 301 power_model=Null
 302 sys=system
 303 port=system.cpu.toL2Bus.slave[3]
 304
 305 [system.cpu.executeFuncUnits]
 306 type=MinorFUPool
 307 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 308 eventq_index=0
 309 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 310
 311 [system.cpu.executeFuncUnits.funcUnits0]
 312 type=MinorFU
 313 children=opClasses timings
 314 cantForwardFromFUIndices=
 315 eventq_index=0
 316 issueLat=1
 317 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 318 opLat=3
 319 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 320
 321 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 322 type=MinorOpClassSet
 323 children=opClasses
 324 eventq_index=0
 325 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 326
 327 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 328 type=MinorOpClass
 329 eventq_index=0
 330 opClass=IntAlu
 331
 332 [system.cpu.executeFuncUnits.funcUnits0.timings]
 333 type=MinorFUTiming
 334 children=opClasses
 335 description=Int
 336 eventq_index=0
 337 extraAssumedLat=0
 338 extraCommitLat=0
 339 extraCommitLatExpr=Null
 340 mask=0
 341 match=0
 342 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 343 srcRegsRelativeLats=2
 344 suppress=false
 345
 346 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 347 type=MinorOpClassSet
 348 eventq_index=0
 349 opClasses=
 350
 351 [system.cpu.executeFuncUnits.funcUnits1]
 352 type=MinorFU
 353 children=opClasses timings
 354 cantForwardFromFUIndices=
 355 eventq_index=0
 356 issueLat=1
 357 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 358 opLat=3
 359 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 360
 361 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 362 type=MinorOpClassSet
 363 children=opClasses
 364 eventq_index=0
 365 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 366
 367 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 368 type=MinorOpClass
 369 eventq_index=0
 370 opClass=IntAlu
 371
 372 [system.cpu.executeFuncUnits.funcUnits1.timings]
 373 type=MinorFUTiming
 374 children=opClasses
 375 description=Int
 376 eventq_index=0
 377 extraAssumedLat=0
 378 extraCommitLat=0
 379 extraCommitLatExpr=Null
 380 mask=0
 381 match=0
 382 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 383 srcRegsRelativeLats=2
 384 suppress=false
 385
 386 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 387 type=MinorOpClassSet
 388 eventq_index=0
 389 opClasses=
 390
 391 [system.cpu.executeFuncUnits.funcUnits2]
 392 type=MinorFU
 393 children=opClasses timings
 394 cantForwardFromFUIndices=
 395 eventq_index=0
 396 issueLat=1
 397 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 398 opLat=3
 399 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 400
 401 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 402 type=MinorOpClassSet
 403 children=opClasses
 404 eventq_index=0
 405 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 406
 407 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 408 type=MinorOpClass
 409 eventq_index=0
 410 opClass=IntMult
 411
 412 [system.cpu.executeFuncUnits.funcUnits2.timings]
 413 type=MinorFUTiming
 414 children=opClasses
 415 description=Mul
 416 eventq_index=0
 417 extraAssumedLat=0
 418 extraCommitLat=0
 419 extraCommitLatExpr=Null
 420 mask=0
 421 match=0
 422 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 423 srcRegsRelativeLats=0
 424 suppress=false
 425
 426 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 427 type=MinorOpClassSet
 428 eventq_index=0
 429 opClasses=
 430
 431 [system.cpu.executeFuncUnits.funcUnits3]
 432 type=MinorFU
 433 children=opClasses
 434 cantForwardFromFUIndices=
 435 eventq_index=0
 436 issueLat=9
 437 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 438 opLat=9
 439 timings=
 440
 441 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 442 type=MinorOpClassSet
 443 children=opClasses
 444 eventq_index=0
 445 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 446
 447 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 448 type=MinorOpClass
 449 eventq_index=0
 450 opClass=IntDiv
 451
 452 [system.cpu.executeFuncUnits.funcUnits4]
 453 type=MinorFU
 454 children=opClasses timings
 455 cantForwardFromFUIndices=
 456 eventq_index=0
 457 issueLat=1
 458 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 459 opLat=6
 460 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 461
 462 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 463 type=MinorOpClassSet
 464 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 465 eventq_index=0
 466 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 467
 468 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 469 type=MinorOpClass
 470 eventq_index=0
 471 opClass=FloatAdd
 472
 473 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 474 type=MinorOpClass
 475 eventq_index=0
 476 opClass=FloatCmp
 477
 478 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 479 type=MinorOpClass
 480 eventq_index=0
 481 opClass=FloatCvt
 482
 483 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 484 type=MinorOpClass
 485 eventq_index=0
 486 opClass=FloatMult
 487
 488 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 489 type=MinorOpClass
 490 eventq_index=0
 491 opClass=FloatDiv
 492
 493 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 494 type=MinorOpClass
 495 eventq_index=0
 496 opClass=FloatSqrt
 497
 498 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 499 type=MinorOpClass
 500 eventq_index=0
 501 opClass=SimdAdd
 502
 503 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 504 type=MinorOpClass
 505 eventq_index=0
 506 opClass=SimdAddAcc
 507
 508 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 509 type=MinorOpClass
 510 eventq_index=0
 511 opClass=SimdAlu
 512
 513 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 514 type=MinorOpClass
 515 eventq_index=0
 516 opClass=SimdCmp
 517
 518 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 519 type=MinorOpClass
 520 eventq_index=0
 521 opClass=SimdCvt
 522
 523 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 524 type=MinorOpClass
 525 eventq_index=0
 526 opClass=SimdMisc
 527
 528 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 529 type=MinorOpClass
 530 eventq_index=0
 531 opClass=SimdMult
 532
 533 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 534 type=MinorOpClass
 535 eventq_index=0
 536 opClass=SimdMultAcc
 537
 538 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 539 type=MinorOpClass
 540 eventq_index=0
 541 opClass=SimdShift
 542
 543 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 544 type=MinorOpClass
 545 eventq_index=0
 546 opClass=SimdShiftAcc
 547
 548 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 549 type=MinorOpClass
 550 eventq_index=0
 551 opClass=SimdSqrt
 552
 553 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 554 type=MinorOpClass
 555 eventq_index=0
 556 opClass=SimdFloatAdd
 557
 558 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 559 type=MinorOpClass
 560 eventq_index=0
 561 opClass=SimdFloatAlu
 562
 563 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 564 type=MinorOpClass
 565 eventq_index=0
 566 opClass=SimdFloatCmp
 567
 568 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 569 type=MinorOpClass
 570 eventq_index=0
 571 opClass=SimdFloatCvt
 572
 573 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 574 type=MinorOpClass
 575 eventq_index=0
 576 opClass=SimdFloatDiv
 577
 578 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 579 type=MinorOpClass
 580 eventq_index=0
 581 opClass=SimdFloatMisc
 582
 583 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 584 type=MinorOpClass
 585 eventq_index=0
 586 opClass=SimdFloatMult
 587
 588 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 589 type=MinorOpClass
 590 eventq_index=0
 591 opClass=SimdFloatMultAcc
 592
 593 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 594 type=MinorOpClass
 595 eventq_index=0
 596 opClass=SimdFloatSqrt
 597
 598 [system.cpu.executeFuncUnits.funcUnits4.timings]
 599 type=MinorFUTiming
 600 children=opClasses
 601 description=FloatSimd
 602 eventq_index=0
 603 extraAssumedLat=0
 604 extraCommitLat=0
 605 extraCommitLatExpr=Null
 606 mask=0
 607 match=0
 608 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 609 srcRegsRelativeLats=2
 610 suppress=false
 611
 612 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 613 type=MinorOpClassSet
 614 eventq_index=0
 615 opClasses=
 616
 617 [system.cpu.executeFuncUnits.funcUnits5]
 618 type=MinorFU
 619 children=opClasses timings
 620 cantForwardFromFUIndices=
 621 eventq_index=0
 622 issueLat=1
 623 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 624 opLat=1
 625 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 626
 627 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 628 type=MinorOpClassSet
 629 children=opClasses0 opClasses1
 630 eventq_index=0
 631 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 632
 633 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 634 type=MinorOpClass
 635 eventq_index=0
 636 opClass=MemRead
 637
 638 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 639 type=MinorOpClass
 640 eventq_index=0
 641 opClass=MemWrite
 642
 643 [system.cpu.executeFuncUnits.funcUnits5.timings]
 644 type=MinorFUTiming
 645 children=opClasses
 646 description=Mem
 647 eventq_index=0
 648 extraAssumedLat=2
 649 extraCommitLat=0
 650 extraCommitLatExpr=Null
 651 mask=0
 652 match=0
 653 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 654 srcRegsRelativeLats=1
 655 suppress=false
 656
 657 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 658 type=MinorOpClassSet
 659 eventq_index=0
 660 opClasses=
 661
 662 [system.cpu.executeFuncUnits.funcUnits6]
 663 type=MinorFU
 664 children=opClasses
 665 cantForwardFromFUIndices=
 666 eventq_index=0
 667 issueLat=1
 668 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 669 opLat=1
 670 timings=
 671
 672 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 673 type=MinorOpClassSet
 674 children=opClasses0 opClasses1
 675 eventq_index=0
 676 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 677
 678 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 679 type=MinorOpClass
 680 eventq_index=0
 681 opClass=IprAccess
 682
 683 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 684 type=MinorOpClass
 685 eventq_index=0
 686 opClass=InstPrefetch
 687
 688 [system.cpu.icache]
 689 type=Cache
 690 children=tags
 691 addr_ranges=0:18446744073709551615:0:0:0:0
 692 assoc=1
 693 clk_domain=system.cpu_clk_domain
 694 clusivity=mostly_incl
 695 default_p_state=UNDEFINED
 696 demand_mshr_reserve=1
 697 eventq_index=0
 698 hit_latency=2
 699 is_read_only=true
 700 max_miss_count=0
 701 mshrs=4
 702 p_state_clk_gate_bins=20
 703 p_state_clk_gate_max=1000000000000
 704 p_state_clk_gate_min=1000
 705 power_model=Null
 706 prefetch_on_access=false
 707 prefetcher=Null
 708 response_latency=2
 709 sequential_access=false
 710 size=32768
 711 system=system
 712 tags=system.cpu.icache.tags
 713 tgts_per_mshr=20
 714 write_buffers=8
 715 writeback_clean=true
 716 cpu_side=system.cpu.icache_port
 717 mem_side=system.cpu.toL2Bus.slave[0]
 718
 719 [system.cpu.icache.tags]
 720 type=LRU
 721 assoc=1
 722 block_size=64
 723 clk_domain=system.cpu_clk_domain
 724 default_p_state=UNDEFINED
 725 eventq_index=0
 726 hit_latency=2
 727 p_state_clk_gate_bins=20
 728 p_state_clk_gate_max=1000000000000
 729 p_state_clk_gate_min=1000
 730 power_model=Null
 731 sequential_access=false
 732 size=32768
 733
 734 [system.cpu.interrupts]
 735 type=ArmInterrupts
 736 eventq_index=0
 737
 738 [system.cpu.isa]
 739 type=ArmISA
 740 decoderFlavour=Generic
 741 eventq_index=0
 742 fpsid=1090793632
 743 id_aa64afr0_el1=0
 744 id_aa64afr1_el1=0
 745 id_aa64dfr0_el1=1052678
 746 id_aa64dfr1_el1=0
 747 id_aa64isar0_el1=0
 748 id_aa64isar1_el1=0
 749 id_aa64mmfr0_el1=15728642
 750 id_aa64mmfr1_el1=0
 751 id_aa64pfr0_el1=34
 752 id_aa64pfr1_el1=0
 753 id_isar0=34607377
 754 id_isar1=34677009
 755 id_isar2=555950401
 756 id_isar3=17899825
 757 id_isar4=268501314
 758 id_isar5=0
 759 id_mmfr0=270536963
 760 id_mmfr1=0
 761 id_mmfr2=19070976
 762 id_mmfr3=34611729
 763 id_pfr0=49
 764 id_pfr1=4113
 765 midr=1091551472
 766 pmu=Null
 767 system=system
 768
 769 [system.cpu.istage2_mmu]
 770 type=ArmStage2MMU
 771 children=stage2_tlb
 772 eventq_index=0
 773 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 774 sys=system
 775 tlb=system.cpu.itb
 776
 777 [system.cpu.istage2_mmu.stage2_tlb]
 778 type=ArmTLB
 779 children=walker
 780 eventq_index=0
 781 is_stage2=true
 782 size=32
 783 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 784
 785 [system.cpu.istage2_mmu.stage2_tlb.walker]
 786 type=ArmTableWalker
 787 clk_domain=system.cpu_clk_domain
 788 default_p_state=UNDEFINED
 789 eventq_index=0
 790 is_stage2=true
 791 num_squash_per_cycle=2
 792 p_state_clk_gate_bins=20
 793 p_state_clk_gate_max=1000000000000
 794 p_state_clk_gate_min=1000
 795 power_model=Null
 796 sys=system
 797
 798 [system.cpu.itb]
 799 type=ArmTLB
 800 children=walker
 801 eventq_index=0
 802 is_stage2=false
 803 size=64
 804 walker=system.cpu.itb.walker
 805
 806 [system.cpu.itb.walker]
 807 type=ArmTableWalker
 808 clk_domain=system.cpu_clk_domain
 809 default_p_state=UNDEFINED
 810 eventq_index=0
 811 is_stage2=false
 812 num_squash_per_cycle=2
 813 p_state_clk_gate_bins=20
 814 p_state_clk_gate_max=1000000000000
 815 p_state_clk_gate_min=1000
 816 power_model=Null
 817 sys=system
 818 port=system.cpu.toL2Bus.slave[2]
 819
 820 [system.cpu.l2cache]
 821 type=Cache
 822 children=tags
 823 addr_ranges=0:18446744073709551615:0:0:0:0
 824 assoc=8
 825 clk_domain=system.cpu_clk_domain
 826 clusivity=mostly_incl
 827 default_p_state=UNDEFINED
 828 demand_mshr_reserve=1
 829 eventq_index=0
 830 hit_latency=20
 831 is_read_only=false
 832 max_miss_count=0
 833 mshrs=20
 834 p_state_clk_gate_bins=20
 835 p_state_clk_gate_max=1000000000000
 836 p_state_clk_gate_min=1000
 837 power_model=Null
 838 prefetch_on_access=false
 839 prefetcher=Null
 840 response_latency=20
 841 sequential_access=false
 842 size=4194304
 843 system=system
 844 tags=system.cpu.l2cache.tags
 845 tgts_per_mshr=12
 846 write_buffers=8
 847 writeback_clean=false
 848 cpu_side=system.cpu.toL2Bus.master[0]
 849 mem_side=system.membus.slave[2]
 850
 851 [system.cpu.l2cache.tags]
 852 type=LRU
 853 assoc=8
 854 block_size=64
 855 clk_domain=system.cpu_clk_domain
 856 default_p_state=UNDEFINED
 857 eventq_index=0
 858 hit_latency=20
 859 p_state_clk_gate_bins=20
 860 p_state_clk_gate_max=1000000000000
 861 p_state_clk_gate_min=1000
 862 power_model=Null
 863 sequential_access=false
 864 size=4194304
 865
 866 [system.cpu.toL2Bus]
 867 type=CoherentXBar
 868 children=snoop_filter
 869 clk_domain=system.cpu_clk_domain
 870 default_p_state=UNDEFINED
 871 eventq_index=0
 872 forward_latency=0
 873 frontend_latency=1
 874 p_state_clk_gate_bins=20
 875 p_state_clk_gate_max=1000000000000
 876 p_state_clk_gate_min=1000
 877 point_of_coherency=false
 878 power_model=Null
 879 response_latency=1
 880 snoop_filter=system.cpu.toL2Bus.snoop_filter
 881 snoop_response_latency=1
 882 system=system
 883 use_default_range=false
 884 width=32
 885 master=system.cpu.l2cache.cpu_side
 886 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 887
 888 [system.cpu.toL2Bus.snoop_filter]
 889 type=SnoopFilter
 890 eventq_index=0
 891 lookup_latency=0
 892 max_capacity=8388608
 893 system=system
 894
 895 [system.cpu.tracer]
 896 type=ExeTracer
 897 eventq_index=0
 898
 899 [system.cpu_clk_domain]
 900 type=SrcClockDomain
 901 clock=500
 902 domain_id=-1
 903 eventq_index=0
 904 init_perf_level=0
 905 voltage_domain=system.voltage_domain
 906
 907 [system.dvfs_handler]
 908 type=DVFSHandler
 909 domains=
 910 enable=false
 911 eventq_index=0
 912 sys_clk_domain=system.clk_domain
 913 transition_latency=100000000
 914
 915 [system.intrctrl]
 916 type=IntrControl
 917 eventq_index=0
 918 sys=system
 919
 920 [system.iobus]
 921 type=NoncoherentXBar
 922 clk_domain=system.clk_domain
 923 default_p_state=UNDEFINED
 924 eventq_index=0
 925 forward_latency=1
 926 frontend_latency=2
 927 p_state_clk_gate_bins=20
 928 p_state_clk_gate_max=1000000000000
 929 p_state_clk_gate_min=1000
 930 power_model=Null
 931 response_latency=2
 932 use_default_range=false
 933 width=16
 934 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 935 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 936
 937 [system.iocache]
 938 type=Cache
 939 children=tags
 940 addr_ranges=2147483648:2415919103:0:0:0:0
 941 assoc=8
 942 clk_domain=system.clk_domain
 943 clusivity=mostly_incl
 944 default_p_state=UNDEFINED
 945 demand_mshr_reserve=1
 946 eventq_index=0
 947 hit_latency=50
 948 is_read_only=false
 949 max_miss_count=0
 950 mshrs=20
 951 p_state_clk_gate_bins=20
 952 p_state_clk_gate_max=1000000000000
 953 p_state_clk_gate_min=1000
 954 power_model=Null
 955 prefetch_on_access=false
 956 prefetcher=Null
 957 response_latency=50
 958 sequential_access=false
 959 size=1024
 960 system=system
 961 tags=system.iocache.tags
 962 tgts_per_mshr=12
 963 write_buffers=8
 964 writeback_clean=false
 965 cpu_side=system.iobus.master[25]
 966 mem_side=system.membus.slave[3]
 967
 968 [system.iocache.tags]
 969 type=LRU
 970 assoc=8
 971 block_size=64
 972 clk_domain=system.clk_domain
 973 default_p_state=UNDEFINED
 974 eventq_index=0
 975 hit_latency=50
 976 p_state_clk_gate_bins=20
 977 p_state_clk_gate_max=1000000000000
 978 p_state_clk_gate_min=1000
 979 power_model=Null
 980 sequential_access=false
 981 size=1024
 982
 983 [system.membus]
 984 type=CoherentXBar
 985 children=badaddr_responder snoop_filter
 986 clk_domain=system.clk_domain
 987 default_p_state=UNDEFINED
 988 eventq_index=0
 989 forward_latency=4
 990 frontend_latency=3
 991 p_state_clk_gate_bins=20
 992 p_state_clk_gate_max=1000000000000
 993 p_state_clk_gate_min=1000
 994 point_of_coherency=true
 995 power_model=Null
 996 response_latency=2
 997 snoop_filter=system.membus.snoop_filter
 998 snoop_response_latency=4
 999 system=system
1000 use_default_range=false
1001 width=16
1002 default=system.membus.badaddr_responder.pio
1003 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1004 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
1005
1006 [system.membus.badaddr_responder]
1007 type=IsaFake
1008 clk_domain=system.clk_domain
1009 default_p_state=UNDEFINED
1010 eventq_index=0
1011 fake_mem=false
1012 p_state_clk_gate_bins=20
1013 p_state_clk_gate_max=1000000000000
1014 p_state_clk_gate_min=1000
1015 pio_addr=0
1016 pio_latency=100000
1017 pio_size=8
1018 power_model=Null
1019 ret_bad_addr=true
1020 ret_data16=65535
1021 ret_data32=4294967295
1022 ret_data64=18446744073709551615
1023 ret_data8=255
1024 system=system
1025 update_data=false
1026 warn_access=warn
1027 pio=system.membus.default
1028
1029 [system.membus.snoop_filter]
1030 type=SnoopFilter
1031 eventq_index=0
1032 lookup_latency=1
1033 max_capacity=8388608
1034 system=system
1035
1036 [system.physmem]
1037 type=DRAMCtrl
1038 IDD0=0.055000
1039 IDD02=0.000000
1040 IDD2N=0.032000
1041 IDD2N2=0.000000
1042 IDD2P0=0.000000
1043 IDD2P02=0.000000
1044 IDD2P1=0.032000
1045 IDD2P12=0.000000
1046 IDD3N=0.038000
1047 IDD3N2=0.000000
1048 IDD3P0=0.000000
1049 IDD3P02=0.000000
1050 IDD3P1=0.038000
1051 IDD3P12=0.000000
1052 IDD4R=0.157000
1053 IDD4R2=0.000000
1054 IDD4W=0.125000
1055 IDD4W2=0.000000
1056 IDD5=0.235000
1057 IDD52=0.000000
1058 IDD6=0.020000
1059 IDD62=0.000000
1060 VDD=1.500000
1061 VDD2=0.000000
1062 activation_limit=4
1063 addr_mapping=RoRaBaCoCh
1064 bank_groups_per_rank=0
1065 banks_per_rank=8
1066 burst_length=8
1067 channels=1
1068 clk_domain=system.clk_domain
1069 conf_table_reported=true
1070 default_p_state=UNDEFINED
1071 device_bus_width=8
1072 device_rowbuffer_size=1024
1073 device_size=536870912
1074 devices_per_rank=8
1075 dll=true
1076 eventq_index=0
1077 in_addr_map=true
1078 kvm_map=true
1079 max_accesses_per_row=16
1080 mem_sched_policy=frfcfs
1081 min_writes_per_switch=16
1082 null=false
1083 p_state_clk_gate_bins=20
1084 p_state_clk_gate_max=1000000000000
1085 p_state_clk_gate_min=1000
1086 page_policy=open_adaptive
1087 power_model=Null
1088 range=2147483648:2415919103:0:0:0:0
1089 ranks_per_channel=2
1090 read_buffer_size=32
1091 static_backend_latency=10000
1092 static_frontend_latency=10000
1093 tBURST=5000
1094 tCCD_L=0
1095 tCK=1250
1096 tCL=13750
1097 tCS=2500
1098 tRAS=35000
1099 tRCD=13750
1100 tREFI=7800000
1101 tRFC=260000
1102 tRP=13750
1103 tRRD=6000
1104 tRRD_L=0
1105 tRTP=7500
1106 tRTW=2500
1107 tWR=15000
1108 tWTR=7500
1109 tXAW=30000
1110 tXP=6000
1111 tXPDLL=0
1112 tXS=270000
1113 tXSDLL=0
1114 write_buffer_size=64
1115 write_high_thresh_perc=85
1116 write_low_thresh_perc=50
1117 port=system.membus.master[5]
1118
1119 [system.realview]
1120 type=RealView
1121 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1122 eventq_index=0
1123 intrctrl=system.intrctrl
1124 system=system
1125
1126 [system.realview.aaci_fake]
1127 type=AmbaFake
1128 amba_id=0
1129 clk_domain=system.clk_domain
1130 default_p_state=UNDEFINED
1131 eventq_index=0
1132 ignore_access=false
1133 p_state_clk_gate_bins=20
1134 p_state_clk_gate_max=1000000000000
1135 p_state_clk_gate_min=1000
1136 pio_addr=470024192
1137 pio_latency=100000
1138 power_model=Null
1139 system=system
1140 pio=system.iobus.master[18]
1141
1142 [system.realview.cf_ctrl]
1143 type=IdeController
1144 BAR0=471465984
1145 BAR0LegacyIO=true
1146 BAR0Size=256
1147 BAR1=471466240
1148 BAR1LegacyIO=true
1149 BAR1Size=4096
1150 BAR2=1
1151 BAR2LegacyIO=false
1152 BAR2Size=8
1153 BAR3=1
1154 BAR3LegacyIO=false
1155 BAR3Size=4
1156 BAR4=1
1157 BAR4LegacyIO=false
1158 BAR4Size=16
1159 BAR5=1
1160 BAR5LegacyIO=false
1161 BAR5Size=0
1162 BIST=0
1163 CacheLineSize=0
1164 CapabilityPtr=0
1165 CardbusCIS=0
1166 ClassCode=1
1167 Command=1
1168 DeviceID=28945
1169 ExpansionROM=0
1170 HeaderType=0
1171 InterruptLine=31
1172 InterruptPin=1
1173 LatencyTimer=0
1174 LegacyIOBase=0
1175 MSICAPBaseOffset=0
1176 MSICAPCapId=0
1177 MSICAPMaskBits=0
1178 MSICAPMsgAddr=0
1179 MSICAPMsgCtrl=0
1180 MSICAPMsgData=0
1181 MSICAPMsgUpperAddr=0
1182 MSICAPNextCapability=0
1183 MSICAPPendingBits=0
1184 MSIXCAPBaseOffset=0
1185 MSIXCAPCapId=0
1186 MSIXCAPNextCapability=0
1187 MSIXMsgCtrl=0
1188 MSIXPbaOffset=0
1189 MSIXTableOffset=0
1190 MaximumLatency=0
1191 MinimumGrant=0
1192 PMCAPBaseOffset=0
1193 PMCAPCapId=0
1194 PMCAPCapabilities=0
1195 PMCAPCtrlStatus=0
1196 PMCAPNextCapability=0
1197 PXCAPBaseOffset=0
1198 PXCAPCapId=0
1199 PXCAPCapabilities=0
1200 PXCAPDevCap2=0
1201 PXCAPDevCapabilities=0
1202 PXCAPDevCtrl=0
1203 PXCAPDevCtrl2=0
1204 PXCAPDevStatus=0
1205 PXCAPLinkCap=0
1206 PXCAPLinkCtrl=0
1207 PXCAPLinkStatus=0
1208 PXCAPNextCapability=0
1209 ProgIF=133
1210 Revision=0
1211 Status=640
1212 SubClassCode=1
1213 SubsystemID=0
1214 SubsystemVendorID=0
1215 VendorID=32902
1216 clk_domain=system.clk_domain
1217 config_latency=20000
1218 ctrl_offset=2
1219 default_p_state=UNDEFINED
1220 disks=
1221 eventq_index=0
1222 host=system.realview.pci_host
1223 io_shift=2
1224 p_state_clk_gate_bins=20
1225 p_state_clk_gate_max=1000000000000
1226 p_state_clk_gate_min=1000
1227 pci_bus=2
1228 pci_dev=0
1229 pci_func=0
1230 pio_latency=30000
1231 power_model=Null
1232 system=system
1233 dma=system.iobus.slave[2]
1234 pio=system.iobus.master[9]
1235
1236 [system.realview.clcd]
1237 type=Pl111
1238 amba_id=1315089
1239 clk_domain=system.clk_domain
1240 default_p_state=UNDEFINED
1241 enable_capture=true
1242 eventq_index=0
1243 gic=system.realview.gic
1244 int_num=46
1245 p_state_clk_gate_bins=20
1246 p_state_clk_gate_max=1000000000000
1247 p_state_clk_gate_min=1000
1248 pio_addr=471793664
1249 pio_latency=10000
1250 pixel_clock=41667
1251 power_model=Null
1252 system=system
1253 vnc=system.vncserver
1254 dma=system.iobus.slave[1]
1255 pio=system.iobus.master[5]
1256
1257 [system.realview.dcc]
1258 type=SubSystem
1259 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1260 eventq_index=0
1261 thermal_domain=Null
1262
1263 [system.realview.dcc.osc_cpu]
1264 type=RealViewOsc
1265 dcc=0
1266 device=0
1267 eventq_index=0
1268 freq=16667
1269 parent=system.realview.realview_io
1270 position=0
1271 site=1
1272 voltage_domain=system.voltage_domain
1273
1274 [system.realview.dcc.osc_ddr]
1275 type=RealViewOsc
1276 dcc=0
1277 device=8
1278 eventq_index=0
1279 freq=25000
1280 parent=system.realview.realview_io
1281 position=0
1282 site=1
1283 voltage_domain=system.voltage_domain
1284
1285 [system.realview.dcc.osc_hsbm]
1286 type=RealViewOsc
1287 dcc=0
1288 device=4
1289 eventq_index=0
1290 freq=25000
1291 parent=system.realview.realview_io
1292 position=0
1293 site=1
1294 voltage_domain=system.voltage_domain
1295
1296 [system.realview.dcc.osc_pxl]
1297 type=RealViewOsc
1298 dcc=0
1299 device=5
1300 eventq_index=0
1301 freq=42105
1302 parent=system.realview.realview_io
1303 position=0
1304 site=1
1305 voltage_domain=system.voltage_domain
1306
1307 [system.realview.dcc.osc_smb]
1308 type=RealViewOsc
1309 dcc=0
1310 device=6
1311 eventq_index=0
1312 freq=20000
1313 parent=system.realview.realview_io
1314 position=0
1315 site=1
1316 voltage_domain=system.voltage_domain
1317
1318 [system.realview.dcc.osc_sys]
1319 type=RealViewOsc
1320 dcc=0
1321 device=7
1322 eventq_index=0
1323 freq=16667
1324 parent=system.realview.realview_io
1325 position=0
1326 site=1
1327 voltage_domain=system.voltage_domain
1328
1329 [system.realview.energy_ctrl]
1330 type=EnergyCtrl
1331 clk_domain=system.clk_domain
1332 default_p_state=UNDEFINED
1333 dvfs_handler=system.dvfs_handler
1334 eventq_index=0
1335 p_state_clk_gate_bins=20
1336 p_state_clk_gate_max=1000000000000
1337 p_state_clk_gate_min=1000
1338 pio_addr=470286336
1339 pio_latency=100000
1340 power_model=Null
1341 system=system
1342 pio=system.iobus.master[22]
1343
1344 [system.realview.ethernet]
1345 type=IGbE
1346 BAR0=0
1347 BAR0LegacyIO=false
1348 BAR0Size=131072
1349 BAR1=0
1350 BAR1LegacyIO=false
1351 BAR1Size=0
1352 BAR2=0
1353 BAR2LegacyIO=false
1354 BAR2Size=0
1355 BAR3=0
1356 BAR3LegacyIO=false
1357 BAR3Size=0
1358 BAR4=0
1359 BAR4LegacyIO=false
1360 BAR4Size=0
1361 BAR5=0
1362 BAR5LegacyIO=false
1363 BAR5Size=0
1364 BIST=0
1365 CacheLineSize=0
1366 CapabilityPtr=0
1367 CardbusCIS=0
1368 ClassCode=2
1369 Command=0
1370 DeviceID=4213
1371 ExpansionROM=0
1372 HeaderType=0
1373 InterruptLine=1
1374 InterruptPin=1
1375 LatencyTimer=0
1376 LegacyIOBase=0
1377 MSICAPBaseOffset=0
1378 MSICAPCapId=0
1379 MSICAPMaskBits=0
1380 MSICAPMsgAddr=0
1381 MSICAPMsgCtrl=0
1382 MSICAPMsgData=0
1383 MSICAPMsgUpperAddr=0
1384 MSICAPNextCapability=0
1385 MSICAPPendingBits=0
1386 MSIXCAPBaseOffset=0
1387 MSIXCAPCapId=0
1388 MSIXCAPNextCapability=0
1389 MSIXMsgCtrl=0
1390 MSIXPbaOffset=0
1391 MSIXTableOffset=0
1392 MaximumLatency=0
1393 MinimumGrant=255
1394 PMCAPBaseOffset=0
1395 PMCAPCapId=0
1396 PMCAPCapabilities=0
1397 PMCAPCtrlStatus=0
1398 PMCAPNextCapability=0
1399 PXCAPBaseOffset=0
1400 PXCAPCapId=0
1401 PXCAPCapabilities=0
1402 PXCAPDevCap2=0
1403 PXCAPDevCapabilities=0
1404 PXCAPDevCtrl=0
1405 PXCAPDevCtrl2=0
1406 PXCAPDevStatus=0
1407 PXCAPLinkCap=0
1408 PXCAPLinkCtrl=0
1409 PXCAPLinkStatus=0
1410 PXCAPNextCapability=0
1411 ProgIF=0
1412 Revision=0
1413 Status=0
1414 SubClassCode=0
1415 SubsystemID=4104
1416 SubsystemVendorID=32902
1417 VendorID=32902
1418 clk_domain=system.clk_domain
1419 config_latency=20000
1420 default_p_state=UNDEFINED
1421 eventq_index=0
1422 fetch_comp_delay=10000
1423 fetch_delay=10000
1424 hardware_address=00:90:00:00:00:01
1425 host=system.realview.pci_host
1426 p_state_clk_gate_bins=20
1427 p_state_clk_gate_max=1000000000000
1428 p_state_clk_gate_min=1000
1429 pci_bus=0
1430 pci_dev=0
1431 pci_func=0
1432 phy_epid=896
1433 phy_pid=680
1434 pio_latency=30000
1435 power_model=Null
1436 rx_desc_cache_size=64
1437 rx_fifo_size=393216
1438 rx_write_delay=0
1439 system=system
1440 tx_desc_cache_size=64
1441 tx_fifo_size=393216
1442 tx_read_delay=0
1443 wb_comp_delay=10000
1444 wb_delay=10000
1445 dma=system.iobus.slave[4]
1446 pio=system.iobus.master[24]
1447
1448 [system.realview.generic_timer]
1449 type=GenericTimer
1450 eventq_index=0
1451 gic=system.realview.gic
1452 int_phys=29
1453 int_virt=27
1454 system=system
1455
1456 [system.realview.gic]
1457 type=Pl390
1458 clk_domain=system.clk_domain
1459 cpu_addr=738205696
1460 cpu_pio_delay=10000
1461 default_p_state=UNDEFINED
1462 dist_addr=738201600
1463 dist_pio_delay=10000
1464 eventq_index=0
1465 gem5_extensions=false
1466 int_latency=10000
1467 it_lines=128
1468 p_state_clk_gate_bins=20
1469 p_state_clk_gate_max=1000000000000
1470 p_state_clk_gate_min=1000
1471 platform=system.realview
1472 power_model=Null
1473 system=system
1474 pio=system.membus.master[2]
1475
1476 [system.realview.hdlcd]
1477 type=HDLcd
1478 amba_id=1314816
1479 clk_domain=system.clk_domain
1480 default_p_state=UNDEFINED
1481 enable_capture=true
1482 eventq_index=0
1483 gic=system.realview.gic
1484 int_num=117
1485 p_state_clk_gate_bins=20
1486 p_state_clk_gate_max=1000000000000
1487 p_state_clk_gate_min=1000
1488 pio_addr=721420288
1489 pio_latency=10000
1490 pixel_buffer_size=2048
1491 pixel_chunk=32
1492 power_model=Null
1493 pxl_clk=system.realview.dcc.osc_pxl
1494 system=system
1495 vnc=system.vncserver
1496 workaround_dma_line_count=true
1497 workaround_swap_rb=true
1498 dma=system.membus.slave[0]
1499 pio=system.iobus.master[6]
1500
1501 [system.realview.ide]
1502 type=IdeController
1503 BAR0=1
1504 BAR0LegacyIO=false
1505 BAR0Size=8
1506 BAR1=1
1507 BAR1LegacyIO=false
1508 BAR1Size=4
1509 BAR2=1
1510 BAR2LegacyIO=false
1511 BAR2Size=8
1512 BAR3=1
1513 BAR3LegacyIO=false
1514 BAR3Size=4
1515 BAR4=1
1516 BAR4LegacyIO=false
1517 BAR4Size=16
1518 BAR5=1
1519 BAR5LegacyIO=false
1520 BAR5Size=0
1521 BIST=0
1522 CacheLineSize=0
1523 CapabilityPtr=0
1524 CardbusCIS=0
1525 ClassCode=1
1526 Command=0
1527 DeviceID=28945
1528 ExpansionROM=0
1529 HeaderType=0
1530 InterruptLine=2
1531 InterruptPin=2
1532 LatencyTimer=0
1533 LegacyIOBase=0
1534 MSICAPBaseOffset=0
1535 MSICAPCapId=0
1536 MSICAPMaskBits=0
1537 MSICAPMsgAddr=0
1538 MSICAPMsgCtrl=0
1539 MSICAPMsgData=0
1540 MSICAPMsgUpperAddr=0
1541 MSICAPNextCapability=0
1542 MSICAPPendingBits=0
1543 MSIXCAPBaseOffset=0
1544 MSIXCAPCapId=0
1545 MSIXCAPNextCapability=0
1546 MSIXMsgCtrl=0
1547 MSIXPbaOffset=0
1548 MSIXTableOffset=0
1549 MaximumLatency=0
1550 MinimumGrant=0
1551 PMCAPBaseOffset=0
1552 PMCAPCapId=0
1553 PMCAPCapabilities=0
1554 PMCAPCtrlStatus=0
1555 PMCAPNextCapability=0
1556 PXCAPBaseOffset=0
1557 PXCAPCapId=0
1558 PXCAPCapabilities=0
1559 PXCAPDevCap2=0
1560 PXCAPDevCapabilities=0
1561 PXCAPDevCtrl=0
1562 PXCAPDevCtrl2=0
1563 PXCAPDevStatus=0
1564 PXCAPLinkCap=0
1565 PXCAPLinkCtrl=0
1566 PXCAPLinkStatus=0
1567 PXCAPNextCapability=0
1568 ProgIF=133
1569 Revision=0
1570 Status=640
1571 SubClassCode=1
1572 SubsystemID=0
1573 SubsystemVendorID=0
1574 VendorID=32902
1575 clk_domain=system.clk_domain
1576 config_latency=20000
1577 ctrl_offset=0
1578 default_p_state=UNDEFINED
1579 disks=system.cf0
1580 eventq_index=0
1581 host=system.realview.pci_host
1582 io_shift=0
1583 p_state_clk_gate_bins=20
1584 p_state_clk_gate_max=1000000000000
1585 p_state_clk_gate_min=1000
1586 pci_bus=0
1587 pci_dev=1
1588 pci_func=0
1589 pio_latency=30000
1590 power_model=Null
1591 system=system
1592 dma=system.iobus.slave[3]
1593 pio=system.iobus.master[23]
1594
1595 [system.realview.kmi0]
1596 type=Pl050
1597 amba_id=1314896
1598 clk_domain=system.clk_domain
1599 default_p_state=UNDEFINED
1600 eventq_index=0
1601 gic=system.realview.gic
1602 int_delay=1000000
1603 int_num=44
1604 is_mouse=false
1605 p_state_clk_gate_bins=20
1606 p_state_clk_gate_max=1000000000000
1607 p_state_clk_gate_min=1000
1608 pio_addr=470155264
1609 pio_latency=100000
1610 power_model=Null
1611 system=system
1612 vnc=system.vncserver
1613 pio=system.iobus.master[7]
1614
1615 [system.realview.kmi1]
1616 type=Pl050
1617 amba_id=1314896
1618 clk_domain=system.clk_domain
1619 default_p_state=UNDEFINED
1620 eventq_index=0
1621 gic=system.realview.gic
1622 int_delay=1000000
1623 int_num=45
1624 is_mouse=true
1625 p_state_clk_gate_bins=20
1626 p_state_clk_gate_max=1000000000000
1627 p_state_clk_gate_min=1000
1628 pio_addr=470220800
1629 pio_latency=100000
1630 power_model=Null
1631 system=system
1632 vnc=system.vncserver
1633 pio=system.iobus.master[8]
1634
1635 [system.realview.l2x0_fake]
1636 type=IsaFake
1637 clk_domain=system.clk_domain
1638 default_p_state=UNDEFINED
1639 eventq_index=0
1640 fake_mem=false
1641 p_state_clk_gate_bins=20
1642 p_state_clk_gate_max=1000000000000
1643 p_state_clk_gate_min=1000
1644 pio_addr=739246080
1645 pio_latency=100000
1646 pio_size=4095
1647 power_model=Null
1648 ret_bad_addr=false
1649 ret_data16=65535
1650 ret_data32=4294967295
1651 ret_data64=18446744073709551615
1652 ret_data8=255
1653 system=system
1654 update_data=false
1655 warn_access=
1656 pio=system.iobus.master[12]
1657
1658 [system.realview.lan_fake]
1659 type=IsaFake
1660 clk_domain=system.clk_domain
1661 default_p_state=UNDEFINED
1662 eventq_index=0
1663 fake_mem=false
1664 p_state_clk_gate_bins=20
1665 p_state_clk_gate_max=1000000000000
1666 p_state_clk_gate_min=1000
1667 pio_addr=436207616
1668 pio_latency=100000
1669 pio_size=65535
1670 power_model=Null
1671 ret_bad_addr=false
1672 ret_data16=65535
1673 ret_data32=4294967295
1674 ret_data64=18446744073709551615
1675 ret_data8=255
1676 system=system
1677 update_data=false
1678 warn_access=
1679 pio=system.iobus.master[19]
1680
1681 [system.realview.local_cpu_timer]
1682 type=CpuLocalTimer
1683 clk_domain=system.clk_domain
1684 default_p_state=UNDEFINED
1685 eventq_index=0
1686 gic=system.realview.gic
1687 int_num_timer=29
1688 int_num_watchdog=30
1689 p_state_clk_gate_bins=20
1690 p_state_clk_gate_max=1000000000000
1691 p_state_clk_gate_min=1000
1692 pio_addr=738721792
1693 pio_latency=100000
1694 power_model=Null
1695 system=system
1696 pio=system.membus.master[4]
1697
1698 [system.realview.mcc]
1699 type=SubSystem
1700 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1701 eventq_index=0
1702 thermal_domain=Null
1703
1704 [system.realview.mcc.osc_clcd]
1705 type=RealViewOsc
1706 dcc=0
1707 device=1
1708 eventq_index=0
1709 freq=42105
1710 parent=system.realview.realview_io
1711 position=0
1712 site=0
1713 voltage_domain=system.voltage_domain
1714
1715 [system.realview.mcc.osc_mcc]
1716 type=RealViewOsc
1717 dcc=0
1718 device=0
1719 eventq_index=0
1720 freq=20000
1721 parent=system.realview.realview_io
1722 position=0
1723 site=0
1724 voltage_domain=system.voltage_domain
1725
1726 [system.realview.mcc.osc_peripheral]
1727 type=RealViewOsc
1728 dcc=0
1729 device=2
1730 eventq_index=0
1731 freq=41667
1732 parent=system.realview.realview_io
1733 position=0
1734 site=0
1735 voltage_domain=system.voltage_domain
1736
1737 [system.realview.mcc.osc_system_bus]
1738 type=RealViewOsc
1739 dcc=0
1740 device=4
1741 eventq_index=0
1742 freq=41667
1743 parent=system.realview.realview_io
1744 position=0
1745 site=0
1746 voltage_domain=system.voltage_domain
1747
1748 [system.realview.mcc.temp_crtl]
1749 type=RealViewTemperatureSensor
1750 dcc=0
1751 device=0
1752 eventq_index=0
1753 parent=system.realview.realview_io
1754 position=0
1755 site=0
1756 system=system
1757
1758 [system.realview.mmc_fake]
1759 type=AmbaFake
1760 amba_id=0
1761 clk_domain=system.clk_domain
1762 default_p_state=UNDEFINED
1763 eventq_index=0
1764 ignore_access=false
1765 p_state_clk_gate_bins=20
1766 p_state_clk_gate_max=1000000000000
1767 p_state_clk_gate_min=1000
1768 pio_addr=470089728
1769 pio_latency=100000
1770 power_model=Null
1771 system=system
1772 pio=system.iobus.master[21]
1773
1774 [system.realview.nvmem]
1775 type=SimpleMemory
1776 bandwidth=73.000000
1777 clk_domain=system.clk_domain
1778 conf_table_reported=false
1779 default_p_state=UNDEFINED
1780 eventq_index=0
1781 in_addr_map=true
1782 kvm_map=true
1783 latency=30000
1784 latency_var=0
1785 null=false
1786 p_state_clk_gate_bins=20
1787 p_state_clk_gate_max=1000000000000
1788 p_state_clk_gate_min=1000
1789 power_model=Null
1790 range=0:67108863:0:0:0:0
1791 port=system.membus.master[1]
1792
1793 [system.realview.pci_host]
1794 type=GenericPciHost
1795 clk_domain=system.clk_domain
1796 conf_base=805306368
1797 conf_device_bits=12
1798 conf_size=268435456
1799 default_p_state=UNDEFINED
1800 eventq_index=0
1801 p_state_clk_gate_bins=20
1802 p_state_clk_gate_max=1000000000000
1803 p_state_clk_gate_min=1000
1804 pci_dma_base=0
1805 pci_mem_base=0
1806 pci_pio_base=788529152
1807 platform=system.realview
1808 power_model=Null
1809 system=system
1810 pio=system.iobus.master[2]
1811
1812 [system.realview.realview_io]
1813 type=RealViewCtrl
1814 clk_domain=system.clk_domain
1815 default_p_state=UNDEFINED
1816 eventq_index=0
1817 idreg=35979264
1818 p_state_clk_gate_bins=20
1819 p_state_clk_gate_max=1000000000000
1820 p_state_clk_gate_min=1000
1821 pio_addr=469827584
1822 pio_latency=100000
1823 power_model=Null
1824 proc_id0=335544320
1825 proc_id1=335544320
1826 system=system
1827 pio=system.iobus.master[1]
1828
1829 [system.realview.rtc]
1830 type=PL031
1831 amba_id=3412017
1832 clk_domain=system.clk_domain
1833 default_p_state=UNDEFINED
1834 eventq_index=0
1835 gic=system.realview.gic
1836 int_delay=100000
1837 int_num=36
1838 p_state_clk_gate_bins=20
1839 p_state_clk_gate_max=1000000000000
1840 p_state_clk_gate_min=1000
1841 pio_addr=471269376
1842 pio_latency=100000
1843 power_model=Null
1844 system=system
1845 time=Thu Jan  1 00:00:00 2009
1846 pio=system.iobus.master[10]
1847
1848 [system.realview.sp810_fake]
1849 type=AmbaFake
1850 amba_id=0
1851 clk_domain=system.clk_domain
1852 default_p_state=UNDEFINED
1853 eventq_index=0
1854 ignore_access=true
1855 p_state_clk_gate_bins=20
1856 p_state_clk_gate_max=1000000000000
1857 p_state_clk_gate_min=1000
1858 pio_addr=469893120
1859 pio_latency=100000
1860 power_model=Null
1861 system=system
1862 pio=system.iobus.master[16]
1863
1864 [system.realview.timer0]
1865 type=Sp804
1866 amba_id=1316868
1867 clk_domain=system.clk_domain
1868 clock0=1000000
1869 clock1=1000000
1870 default_p_state=UNDEFINED
1871 eventq_index=0
1872 gic=system.realview.gic
1873 int_num0=34
1874 int_num1=34
1875 p_state_clk_gate_bins=20
1876 p_state_clk_gate_max=1000000000000
1877 p_state_clk_gate_min=1000
1878 pio_addr=470876160
1879 pio_latency=100000
1880 power_model=Null
1881 system=system
1882 pio=system.iobus.master[3]
1883
1884 [system.realview.timer1]
1885 type=Sp804
1886 amba_id=1316868
1887 clk_domain=system.clk_domain
1888 clock0=1000000
1889 clock1=1000000
1890 default_p_state=UNDEFINED
1891 eventq_index=0
1892 gic=system.realview.gic
1893 int_num0=35
1894 int_num1=35
1895 p_state_clk_gate_bins=20
1896 p_state_clk_gate_max=1000000000000
1897 p_state_clk_gate_min=1000
1898 pio_addr=470941696
1899 pio_latency=100000
1900 power_model=Null
1901 system=system
1902 pio=system.iobus.master[4]
1903
1904 [system.realview.uart]
1905 type=Pl011
1906 clk_domain=system.clk_domain
1907 default_p_state=UNDEFINED
1908 end_on_eot=false
1909 eventq_index=0
1910 gic=system.realview.gic
1911 int_delay=100000
1912 int_num=37
1913 p_state_clk_gate_bins=20
1914 p_state_clk_gate_max=1000000000000
1915 p_state_clk_gate_min=1000
1916 pio_addr=470351872
1917 pio_latency=100000
1918 platform=system.realview
1919 power_model=Null
1920 system=system
1921 terminal=system.terminal
1922 pio=system.iobus.master[0]
1923
1924 [system.realview.uart1_fake]
1925 type=AmbaFake
1926 amba_id=0
1927 clk_domain=system.clk_domain
1928 default_p_state=UNDEFINED
1929 eventq_index=0
1930 ignore_access=false
1931 p_state_clk_gate_bins=20
1932 p_state_clk_gate_max=1000000000000
1933 p_state_clk_gate_min=1000
1934 pio_addr=470417408
1935 pio_latency=100000
1936 power_model=Null
1937 system=system
1938 pio=system.iobus.master[13]
1939
1940 [system.realview.uart2_fake]
1941 type=AmbaFake
1942 amba_id=0
1943 clk_domain=system.clk_domain
1944 default_p_state=UNDEFINED
1945 eventq_index=0
1946 ignore_access=false
1947 p_state_clk_gate_bins=20
1948 p_state_clk_gate_max=1000000000000
1949 p_state_clk_gate_min=1000
1950 pio_addr=470482944
1951 pio_latency=100000
1952 power_model=Null
1953 system=system
1954 pio=system.iobus.master[14]
1955
1956 [system.realview.uart3_fake]
1957 type=AmbaFake
1958 amba_id=0
1959 clk_domain=system.clk_domain
1960 default_p_state=UNDEFINED
1961 eventq_index=0
1962 ignore_access=false
1963 p_state_clk_gate_bins=20
1964 p_state_clk_gate_max=1000000000000
1965 p_state_clk_gate_min=1000
1966 pio_addr=470548480
1967 pio_latency=100000
1968 power_model=Null
1969 system=system
1970 pio=system.iobus.master[15]
1971
1972 [system.realview.usb_fake]
1973 type=IsaFake
1974 clk_domain=system.clk_domain
1975 default_p_state=UNDEFINED
1976 eventq_index=0
1977 fake_mem=false
1978 p_state_clk_gate_bins=20
1979 p_state_clk_gate_max=1000000000000
1980 p_state_clk_gate_min=1000
1981 pio_addr=452984832
1982 pio_latency=100000
1983 pio_size=131071
1984 power_model=Null
1985 ret_bad_addr=false
1986 ret_data16=65535
1987 ret_data32=4294967295
1988 ret_data64=18446744073709551615
1989 ret_data8=255
1990 system=system
1991 update_data=false
1992 warn_access=
1993 pio=system.iobus.master[20]
1994
1995 [system.realview.vgic]
1996 type=VGic
1997 clk_domain=system.clk_domain
1998 default_p_state=UNDEFINED
1999 eventq_index=0
2000 gic=system.realview.gic
2001 hv_addr=738213888
2002 p_state_clk_gate_bins=20
2003 p_state_clk_gate_max=1000000000000
2004 p_state_clk_gate_min=1000
2005 pio_delay=10000
2006 platform=system.realview
2007 power_model=Null
2008 ppint=25
2009 system=system
2010 vcpu_addr=738222080
2011 pio=system.membus.master[3]
2012
2013 [system.realview.vram]
2014 type=SimpleMemory
2015 bandwidth=73.000000
2016 clk_domain=system.clk_domain
2017 conf_table_reported=false
2018 default_p_state=UNDEFINED
2019 eventq_index=0
2020 in_addr_map=true
2021 kvm_map=true
2022 latency=30000
2023 latency_var=0
2024 null=false
2025 p_state_clk_gate_bins=20
2026 p_state_clk_gate_max=1000000000000
2027 p_state_clk_gate_min=1000
2028 power_model=Null
2029 range=402653184:436207615:0:0:0:0
2030 port=system.iobus.master[11]
2031
2032 [system.realview.watchdog_fake]
2033 type=AmbaFake
2034 amba_id=0
2035 clk_domain=system.clk_domain
2036 default_p_state=UNDEFINED
2037 eventq_index=0
2038 ignore_access=false
2039 p_state_clk_gate_bins=20
2040 p_state_clk_gate_max=1000000000000
2041 p_state_clk_gate_min=1000
2042 pio_addr=470745088
2043 pio_latency=100000
2044 power_model=Null
2045 system=system
2046 pio=system.iobus.master[17]
2047
2048 [system.terminal]
2049 type=Terminal
2050 eventq_index=0
2051 intr_control=system.intrctrl
2052 number=0
2053 output=true
2054 port=3456
2055
2056 [system.vncserver]
2057 type=VncServer
2058 eventq_index=0
2059 frame_capture=false
2060 number=0
2061 port=5900
2062
2063 [system.voltage_domain]
2064 type=VoltageDomain
2065 eventq_index=0
2066 voltage=1.000000
2067