tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM64
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=DerivO3CPU
 115 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 LFSTSize=1024
 117 LQEntries=16
 118 LSQCheckLoads=true
 119 LSQDepCheckShift=0
 120 SQEntries=16
 121 SSITSize=1024
 122 activity=0
 123 backComSize=5
 124 branchPred=system.cpu.branchPred
 125 cachePorts=200
 126 checker=Null
 127 clk_domain=system.cpu_clk_domain
 128 commitToDecodeDelay=1
 129 commitToFetchDelay=1
 130 commitToIEWDelay=1
 131 commitToRenameDelay=1
 132 commitWidth=8
 133 cpu_id=0
 134 decodeToFetchDelay=1
 135 decodeToRenameDelay=2
 136 decodeWidth=3
 137 default_p_state=UNDEFINED
 138 dispatchWidth=6
 139 do_checkpoint_insts=true
 140 do_quiesce=true
 141 do_statistics_insts=true
 142 dstage2_mmu=system.cpu.dstage2_mmu
 143 dtb=system.cpu.dtb
 144 eventq_index=0
 145 fetchBufferSize=16
 146 fetchQueueSize=32
 147 fetchToDecodeDelay=3
 148 fetchTrapLatency=1
 149 fetchWidth=3
 150 forwardComSize=5
 151 fuPool=system.cpu.fuPool
 152 function_trace=false
 153 function_trace_start=0
 154 iewToCommitDelay=1
 155 iewToDecodeDelay=1
 156 iewToFetchDelay=1
 157 iewToRenameDelay=1
 158 interrupts=system.cpu.interrupts
 159 isa=system.cpu.isa
 160 issueToExecuteDelay=1
 161 issueWidth=8
 162 istage2_mmu=system.cpu.istage2_mmu
 163 itb=system.cpu.itb
 164 max_insts_all_threads=0
 165 max_insts_any_thread=0
 166 max_loads_all_threads=0
 167 max_loads_any_thread=0
 168 needsTSO=false
 169 numIQEntries=32
 170 numPhysCCRegs=640
 171 numPhysFloatRegs=192
 172 numPhysIntRegs=128
 173 numROBEntries=40
 174 numRobs=1
 175 numThreads=1
 176 p_state_clk_gate_bins=20
 177 p_state_clk_gate_max=1000000000000
 178 p_state_clk_gate_min=1000
 179 power_model=Null
 180 profile=0
 181 progress_interval=0
 182 renameToDecodeDelay=1
 183 renameToFetchDelay=1
 184 renameToIEWDelay=1
 185 renameToROBDelay=1
 186 renameWidth=3
 187 simpoint_start_insts=
 188 smtCommitPolicy=RoundRobin
 189 smtFetchPolicy=SingleThread
 190 smtIQPolicy=Partitioned
 191 smtIQThreshold=100
 192 smtLSQPolicy=Partitioned
 193 smtLSQThreshold=100
 194 smtNumFetchingThreads=1
 195 smtROBPolicy=Partitioned
 196 smtROBThreshold=100
 197 socket_id=0
 198 squashWidth=8
 199 store_set_clear_period=250000
 200 switched_out=false
 201 system=system
 202 tracer=system.cpu.tracer
 203 trapLatency=13
 204 wbWidth=8
 205 workload=
 206 dcache_port=system.cpu.dcache.cpu_side
 207 icache_port=system.cpu.icache.cpu_side
 208
 209 [system.cpu.branchPred]
 210 type=BiModeBP
 211 BTBEntries=2048
 212 BTBTagSize=18
 213 RASSize=16
 214 choiceCtrBits=2
 215 choicePredictorSize=8192
 216 eventq_index=0
 217 globalCtrBits=2
 218 globalPredictorSize=8192
 219 indirectHashGHR=true
 220 indirectHashTargets=true
 221 indirectPathLength=3
 222 indirectSets=256
 223 indirectTagSize=16
 224 indirectWays=2
 225 instShiftAmt=2
 226 numThreads=1
 227 useIndirect=true
 228
 229 [system.cpu.dcache]
 230 type=Cache
 231 children=tags
 232 addr_ranges=0:18446744073709551615:0:0:0:0
 233 assoc=4
 234 clk_domain=system.cpu_clk_domain
 235 clusivity=mostly_incl
 236 default_p_state=UNDEFINED
 237 demand_mshr_reserve=1
 238 eventq_index=0
 239 hit_latency=2
 240 is_read_only=false
 241 max_miss_count=0
 242 mshrs=4
 243 p_state_clk_gate_bins=20
 244 p_state_clk_gate_max=1000000000000
 245 p_state_clk_gate_min=1000
 246 power_model=Null
 247 prefetch_on_access=false
 248 prefetcher=Null
 249 response_latency=2
 250 sequential_access=false
 251 size=32768
 252 system=system
 253 tags=system.cpu.dcache.tags
 254 tgts_per_mshr=20
 255 write_buffers=8
 256 writeback_clean=false
 257 cpu_side=system.cpu.dcache_port
 258 mem_side=system.cpu.toL2Bus.slave[1]
 259
 260 [system.cpu.dcache.tags]
 261 type=LRU
 262 assoc=4
 263 block_size=64
 264 clk_domain=system.cpu_clk_domain
 265 default_p_state=UNDEFINED
 266 eventq_index=0
 267 hit_latency=2
 268 p_state_clk_gate_bins=20
 269 p_state_clk_gate_max=1000000000000
 270 p_state_clk_gate_min=1000
 271 power_model=Null
 272 sequential_access=false
 273 size=32768
 274
 275 [system.cpu.dstage2_mmu]
 276 type=ArmStage2MMU
 277 children=stage2_tlb
 278 eventq_index=0
 279 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 280 sys=system
 281 tlb=system.cpu.dtb
 282
 283 [system.cpu.dstage2_mmu.stage2_tlb]
 284 type=ArmTLB
 285 children=walker
 286 eventq_index=0
 287 is_stage2=true
 288 size=32
 289 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 290
 291 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 292 type=ArmTableWalker
 293 clk_domain=system.cpu_clk_domain
 294 default_p_state=UNDEFINED
 295 eventq_index=0
 296 is_stage2=true
 297 num_squash_per_cycle=2
 298 p_state_clk_gate_bins=20
 299 p_state_clk_gate_max=1000000000000
 300 p_state_clk_gate_min=1000
 301 power_model=Null
 302 sys=system
 303
 304 [system.cpu.dtb]
 305 type=ArmTLB
 306 children=walker
 307 eventq_index=0
 308 is_stage2=false
 309 size=64
 310 walker=system.cpu.dtb.walker
 311
 312 [system.cpu.dtb.walker]
 313 type=ArmTableWalker
 314 clk_domain=system.cpu_clk_domain
 315 default_p_state=UNDEFINED
 316 eventq_index=0
 317 is_stage2=false
 318 num_squash_per_cycle=2
 319 p_state_clk_gate_bins=20
 320 p_state_clk_gate_max=1000000000000
 321 p_state_clk_gate_min=1000
 322 power_model=Null
 323 sys=system
 324 port=system.cpu.toL2Bus.slave[3]
 325
 326 [system.cpu.fuPool]
 327 type=FUPool
 328 children=FUList0 FUList1 FUList2 FUList3 FUList4
 329 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 330 eventq_index=0
 331
 332 [system.cpu.fuPool.FUList0]
 333 type=FUDesc
 334 children=opList
 335 count=2
 336 eventq_index=0
 337 opList=system.cpu.fuPool.FUList0.opList
 338
 339 [system.cpu.fuPool.FUList0.opList]
 340 type=OpDesc
 341 eventq_index=0
 342 opClass=IntAlu
 343 opLat=1
 344 pipelined=true
 345
 346 [system.cpu.fuPool.FUList1]
 347 type=FUDesc
 348 children=opList0 opList1 opList2
 349 count=1
 350 eventq_index=0
 351 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 352
 353 [system.cpu.fuPool.FUList1.opList0]
 354 type=OpDesc
 355 eventq_index=0
 356 opClass=IntMult
 357 opLat=3
 358 pipelined=true
 359
 360 [system.cpu.fuPool.FUList1.opList1]
 361 type=OpDesc
 362 eventq_index=0
 363 opClass=IntDiv
 364 opLat=12
 365 pipelined=false
 366
 367 [system.cpu.fuPool.FUList1.opList2]
 368 type=OpDesc
 369 eventq_index=0
 370 opClass=IprAccess
 371 opLat=3
 372 pipelined=true
 373
 374 [system.cpu.fuPool.FUList2]
 375 type=FUDesc
 376 children=opList
 377 count=1
 378 eventq_index=0
 379 opList=system.cpu.fuPool.FUList2.opList
 380
 381 [system.cpu.fuPool.FUList2.opList]
 382 type=OpDesc
 383 eventq_index=0
 384 opClass=MemRead
 385 opLat=2
 386 pipelined=true
 387
 388 [system.cpu.fuPool.FUList3]
 389 type=FUDesc
 390 children=opList
 391 count=1
 392 eventq_index=0
 393 opList=system.cpu.fuPool.FUList3.opList
 394
 395 [system.cpu.fuPool.FUList3.opList]
 396 type=OpDesc
 397 eventq_index=0
 398 opClass=MemWrite
 399 opLat=2
 400 pipelined=true
 401
 402 [system.cpu.fuPool.FUList4]
 403 type=FUDesc
 404 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
 405 count=2
 406 eventq_index=0
 407 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
 408
 409 [system.cpu.fuPool.FUList4.opList00]
 410 type=OpDesc
 411 eventq_index=0
 412 opClass=SimdAdd
 413 opLat=4
 414 pipelined=true
 415
 416 [system.cpu.fuPool.FUList4.opList01]
 417 type=OpDesc
 418 eventq_index=0
 419 opClass=SimdAddAcc
 420 opLat=4
 421 pipelined=true
 422
 423 [system.cpu.fuPool.FUList4.opList02]
 424 type=OpDesc
 425 eventq_index=0
 426 opClass=SimdAlu
 427 opLat=4
 428 pipelined=true
 429
 430 [system.cpu.fuPool.FUList4.opList03]
 431 type=OpDesc
 432 eventq_index=0
 433 opClass=SimdCmp
 434 opLat=4
 435 pipelined=true
 436
 437 [system.cpu.fuPool.FUList4.opList04]
 438 type=OpDesc
 439 eventq_index=0
 440 opClass=SimdCvt
 441 opLat=3
 442 pipelined=true
 443
 444 [system.cpu.fuPool.FUList4.opList05]
 445 type=OpDesc
 446 eventq_index=0
 447 opClass=SimdMisc
 448 opLat=3
 449 pipelined=true
 450
 451 [system.cpu.fuPool.FUList4.opList06]
 452 type=OpDesc
 453 eventq_index=0
 454 opClass=SimdMult
 455 opLat=5
 456 pipelined=true
 457
 458 [system.cpu.fuPool.FUList4.opList07]
 459 type=OpDesc
 460 eventq_index=0
 461 opClass=SimdMultAcc
 462 opLat=5
 463 pipelined=true
 464
 465 [system.cpu.fuPool.FUList4.opList08]
 466 type=OpDesc
 467 eventq_index=0
 468 opClass=SimdShift
 469 opLat=3
 470 pipelined=true
 471
 472 [system.cpu.fuPool.FUList4.opList09]
 473 type=OpDesc
 474 eventq_index=0
 475 opClass=SimdShiftAcc
 476 opLat=3
 477 pipelined=true
 478
 479 [system.cpu.fuPool.FUList4.opList10]
 480 type=OpDesc
 481 eventq_index=0
 482 opClass=SimdSqrt
 483 opLat=9
 484 pipelined=true
 485
 486 [system.cpu.fuPool.FUList4.opList11]
 487 type=OpDesc
 488 eventq_index=0
 489 opClass=SimdFloatAdd
 490 opLat=5
 491 pipelined=true
 492
 493 [system.cpu.fuPool.FUList4.opList12]
 494 type=OpDesc
 495 eventq_index=0
 496 opClass=SimdFloatAlu
 497 opLat=5
 498 pipelined=true
 499
 500 [system.cpu.fuPool.FUList4.opList13]
 501 type=OpDesc
 502 eventq_index=0
 503 opClass=SimdFloatCmp
 504 opLat=3
 505 pipelined=true
 506
 507 [system.cpu.fuPool.FUList4.opList14]
 508 type=OpDesc
 509 eventq_index=0
 510 opClass=SimdFloatCvt
 511 opLat=3
 512 pipelined=true
 513
 514 [system.cpu.fuPool.FUList4.opList15]
 515 type=OpDesc
 516 eventq_index=0
 517 opClass=SimdFloatDiv
 518 opLat=3
 519 pipelined=true
 520
 521 [system.cpu.fuPool.FUList4.opList16]
 522 type=OpDesc
 523 eventq_index=0
 524 opClass=SimdFloatMisc
 525 opLat=3
 526 pipelined=true
 527
 528 [system.cpu.fuPool.FUList4.opList17]
 529 type=OpDesc
 530 eventq_index=0
 531 opClass=SimdFloatMult
 532 opLat=3
 533 pipelined=true
 534
 535 [system.cpu.fuPool.FUList4.opList18]
 536 type=OpDesc
 537 eventq_index=0
 538 opClass=SimdFloatMultAcc
 539 opLat=1
 540 pipelined=true
 541
 542 [system.cpu.fuPool.FUList4.opList19]
 543 type=OpDesc
 544 eventq_index=0
 545 opClass=SimdFloatSqrt
 546 opLat=9
 547 pipelined=true
 548
 549 [system.cpu.fuPool.FUList4.opList20]
 550 type=OpDesc
 551 eventq_index=0
 552 opClass=FloatAdd
 553 opLat=5
 554 pipelined=true
 555
 556 [system.cpu.fuPool.FUList4.opList21]
 557 type=OpDesc
 558 eventq_index=0
 559 opClass=FloatCmp
 560 opLat=5
 561 pipelined=true
 562
 563 [system.cpu.fuPool.FUList4.opList22]
 564 type=OpDesc
 565 eventq_index=0
 566 opClass=FloatCvt
 567 opLat=5
 568 pipelined=true
 569
 570 [system.cpu.fuPool.FUList4.opList23]
 571 type=OpDesc
 572 eventq_index=0
 573 opClass=FloatDiv
 574 opLat=9
 575 pipelined=false
 576
 577 [system.cpu.fuPool.FUList4.opList24]
 578 type=OpDesc
 579 eventq_index=0
 580 opClass=FloatSqrt
 581 opLat=33
 582 pipelined=false
 583
 584 [system.cpu.fuPool.FUList4.opList25]
 585 type=OpDesc
 586 eventq_index=0
 587 opClass=FloatMult
 588 opLat=4
 589 pipelined=true
 590
 591 [system.cpu.icache]
 592 type=Cache
 593 children=tags
 594 addr_ranges=0:18446744073709551615:0:0:0:0
 595 assoc=1
 596 clk_domain=system.cpu_clk_domain
 597 clusivity=mostly_incl
 598 default_p_state=UNDEFINED
 599 demand_mshr_reserve=1
 600 eventq_index=0
 601 hit_latency=2
 602 is_read_only=true
 603 max_miss_count=0
 604 mshrs=4
 605 p_state_clk_gate_bins=20
 606 p_state_clk_gate_max=1000000000000
 607 p_state_clk_gate_min=1000
 608 power_model=Null
 609 prefetch_on_access=false
 610 prefetcher=Null
 611 response_latency=2
 612 sequential_access=false
 613 size=32768
 614 system=system
 615 tags=system.cpu.icache.tags
 616 tgts_per_mshr=20
 617 write_buffers=8
 618 writeback_clean=true
 619 cpu_side=system.cpu.icache_port
 620 mem_side=system.cpu.toL2Bus.slave[0]
 621
 622 [system.cpu.icache.tags]
 623 type=LRU
 624 assoc=1
 625 block_size=64
 626 clk_domain=system.cpu_clk_domain
 627 default_p_state=UNDEFINED
 628 eventq_index=0
 629 hit_latency=2
 630 p_state_clk_gate_bins=20
 631 p_state_clk_gate_max=1000000000000
 632 p_state_clk_gate_min=1000
 633 power_model=Null
 634 sequential_access=false
 635 size=32768
 636
 637 [system.cpu.interrupts]
 638 type=ArmInterrupts
 639 eventq_index=0
 640
 641 [system.cpu.isa]
 642 type=ArmISA
 643 decoderFlavour=Generic
 644 eventq_index=0
 645 fpsid=1090793632
 646 id_aa64afr0_el1=0
 647 id_aa64afr1_el1=0
 648 id_aa64dfr0_el1=1052678
 649 id_aa64dfr1_el1=0
 650 id_aa64isar0_el1=0
 651 id_aa64isar1_el1=0
 652 id_aa64mmfr0_el1=15728642
 653 id_aa64mmfr1_el1=0
 654 id_aa64pfr0_el1=34
 655 id_aa64pfr1_el1=0
 656 id_isar0=34607377
 657 id_isar1=34677009
 658 id_isar2=555950401
 659 id_isar3=17899825
 660 id_isar4=268501314
 661 id_isar5=0
 662 id_mmfr0=270536963
 663 id_mmfr1=0
 664 id_mmfr2=19070976
 665 id_mmfr3=34611729
 666 id_pfr0=49
 667 id_pfr1=4113
 668 midr=1091551472
 669 pmu=Null
 670 system=system
 671
 672 [system.cpu.istage2_mmu]
 673 type=ArmStage2MMU
 674 children=stage2_tlb
 675 eventq_index=0
 676 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 677 sys=system
 678 tlb=system.cpu.itb
 679
 680 [system.cpu.istage2_mmu.stage2_tlb]
 681 type=ArmTLB
 682 children=walker
 683 eventq_index=0
 684 is_stage2=true
 685 size=32
 686 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 687
 688 [system.cpu.istage2_mmu.stage2_tlb.walker]
 689 type=ArmTableWalker
 690 clk_domain=system.cpu_clk_domain
 691 default_p_state=UNDEFINED
 692 eventq_index=0
 693 is_stage2=true
 694 num_squash_per_cycle=2
 695 p_state_clk_gate_bins=20
 696 p_state_clk_gate_max=1000000000000
 697 p_state_clk_gate_min=1000
 698 power_model=Null
 699 sys=system
 700
 701 [system.cpu.itb]
 702 type=ArmTLB
 703 children=walker
 704 eventq_index=0
 705 is_stage2=false
 706 size=64
 707 walker=system.cpu.itb.walker
 708
 709 [system.cpu.itb.walker]
 710 type=ArmTableWalker
 711 clk_domain=system.cpu_clk_domain
 712 default_p_state=UNDEFINED
 713 eventq_index=0
 714 is_stage2=false
 715 num_squash_per_cycle=2
 716 p_state_clk_gate_bins=20
 717 p_state_clk_gate_max=1000000000000
 718 p_state_clk_gate_min=1000
 719 power_model=Null
 720 sys=system
 721 port=system.cpu.toL2Bus.slave[2]
 722
 723 [system.cpu.l2cache]
 724 type=Cache
 725 children=tags
 726 addr_ranges=0:18446744073709551615:0:0:0:0
 727 assoc=8
 728 clk_domain=system.cpu_clk_domain
 729 clusivity=mostly_incl
 730 default_p_state=UNDEFINED
 731 demand_mshr_reserve=1
 732 eventq_index=0
 733 hit_latency=20
 734 is_read_only=false
 735 max_miss_count=0
 736 mshrs=20
 737 p_state_clk_gate_bins=20
 738 p_state_clk_gate_max=1000000000000
 739 p_state_clk_gate_min=1000
 740 power_model=Null
 741 prefetch_on_access=false
 742 prefetcher=Null
 743 response_latency=20
 744 sequential_access=false
 745 size=4194304
 746 system=system
 747 tags=system.cpu.l2cache.tags
 748 tgts_per_mshr=12
 749 write_buffers=8
 750 writeback_clean=false
 751 cpu_side=system.cpu.toL2Bus.master[0]
 752 mem_side=system.membus.slave[2]
 753
 754 [system.cpu.l2cache.tags]
 755 type=LRU
 756 assoc=8
 757 block_size=64
 758 clk_domain=system.cpu_clk_domain
 759 default_p_state=UNDEFINED
 760 eventq_index=0
 761 hit_latency=20
 762 p_state_clk_gate_bins=20
 763 p_state_clk_gate_max=1000000000000
 764 p_state_clk_gate_min=1000
 765 power_model=Null
 766 sequential_access=false
 767 size=4194304
 768
 769 [system.cpu.toL2Bus]
 770 type=CoherentXBar
 771 children=snoop_filter
 772 clk_domain=system.cpu_clk_domain
 773 default_p_state=UNDEFINED
 774 eventq_index=0
 775 forward_latency=0
 776 frontend_latency=1
 777 p_state_clk_gate_bins=20
 778 p_state_clk_gate_max=1000000000000
 779 p_state_clk_gate_min=1000
 780 point_of_coherency=false
 781 power_model=Null
 782 response_latency=1
 783 snoop_filter=system.cpu.toL2Bus.snoop_filter
 784 snoop_response_latency=1
 785 system=system
 786 use_default_range=false
 787 width=32
 788 master=system.cpu.l2cache.cpu_side
 789 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 790
 791 [system.cpu.toL2Bus.snoop_filter]
 792 type=SnoopFilter
 793 eventq_index=0
 794 lookup_latency=0
 795 max_capacity=8388608
 796 system=system
 797
 798 [system.cpu.tracer]
 799 type=ExeTracer
 800 eventq_index=0
 801
 802 [system.cpu_clk_domain]
 803 type=SrcClockDomain
 804 clock=500
 805 domain_id=-1
 806 eventq_index=0
 807 init_perf_level=0
 808 voltage_domain=system.voltage_domain
 809
 810 [system.dvfs_handler]
 811 type=DVFSHandler
 812 domains=
 813 enable=false
 814 eventq_index=0
 815 sys_clk_domain=system.clk_domain
 816 transition_latency=100000000
 817
 818 [system.intrctrl]
 819 type=IntrControl
 820 eventq_index=0
 821 sys=system
 822
 823 [system.iobus]
 824 type=NoncoherentXBar
 825 clk_domain=system.clk_domain
 826 default_p_state=UNDEFINED
 827 eventq_index=0
 828 forward_latency=1
 829 frontend_latency=2
 830 p_state_clk_gate_bins=20
 831 p_state_clk_gate_max=1000000000000
 832 p_state_clk_gate_min=1000
 833 power_model=Null
 834 response_latency=2
 835 use_default_range=false
 836 width=16
 837 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 838 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 839
 840 [system.iocache]
 841 type=Cache
 842 children=tags
 843 addr_ranges=2147483648:2415919103:0:0:0:0
 844 assoc=8
 845 clk_domain=system.clk_domain
 846 clusivity=mostly_incl
 847 default_p_state=UNDEFINED
 848 demand_mshr_reserve=1
 849 eventq_index=0
 850 hit_latency=50
 851 is_read_only=false
 852 max_miss_count=0
 853 mshrs=20
 854 p_state_clk_gate_bins=20
 855 p_state_clk_gate_max=1000000000000
 856 p_state_clk_gate_min=1000
 857 power_model=Null
 858 prefetch_on_access=false
 859 prefetcher=Null
 860 response_latency=50
 861 sequential_access=false
 862 size=1024
 863 system=system
 864 tags=system.iocache.tags
 865 tgts_per_mshr=12
 866 write_buffers=8
 867 writeback_clean=false
 868 cpu_side=system.iobus.master[25]
 869 mem_side=system.membus.slave[3]
 870
 871 [system.iocache.tags]
 872 type=LRU
 873 assoc=8
 874 block_size=64
 875 clk_domain=system.clk_domain
 876 default_p_state=UNDEFINED
 877 eventq_index=0
 878 hit_latency=50
 879 p_state_clk_gate_bins=20
 880 p_state_clk_gate_max=1000000000000
 881 p_state_clk_gate_min=1000
 882 power_model=Null
 883 sequential_access=false
 884 size=1024
 885
 886 [system.membus]
 887 type=CoherentXBar
 888 children=badaddr_responder snoop_filter
 889 clk_domain=system.clk_domain
 890 default_p_state=UNDEFINED
 891 eventq_index=0
 892 forward_latency=4
 893 frontend_latency=3
 894 p_state_clk_gate_bins=20
 895 p_state_clk_gate_max=1000000000000
 896 p_state_clk_gate_min=1000
 897 point_of_coherency=true
 898 power_model=Null
 899 response_latency=2
 900 snoop_filter=system.membus.snoop_filter
 901 snoop_response_latency=4
 902 system=system
 903 use_default_range=false
 904 width=16
 905 default=system.membus.badaddr_responder.pio
 906 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 907 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 908
 909 [system.membus.badaddr_responder]
 910 type=IsaFake
 911 clk_domain=system.clk_domain
 912 default_p_state=UNDEFINED
 913 eventq_index=0
 914 fake_mem=false
 915 p_state_clk_gate_bins=20
 916 p_state_clk_gate_max=1000000000000
 917 p_state_clk_gate_min=1000
 918 pio_addr=0
 919 pio_latency=100000
 920 pio_size=8
 921 power_model=Null
 922 ret_bad_addr=true
 923 ret_data16=65535
 924 ret_data32=4294967295
 925 ret_data64=18446744073709551615
 926 ret_data8=255
 927 system=system
 928 update_data=false
 929 warn_access=warn
 930 pio=system.membus.default
 931
 932 [system.membus.snoop_filter]
 933 type=SnoopFilter
 934 eventq_index=0
 935 lookup_latency=1
 936 max_capacity=8388608
 937 system=system
 938
 939 [system.physmem]
 940 type=DRAMCtrl
 941 IDD0=0.055000
 942 IDD02=0.000000
 943 IDD2N=0.032000
 944 IDD2N2=0.000000
 945 IDD2P0=0.000000
 946 IDD2P02=0.000000
 947 IDD2P1=0.032000
 948 IDD2P12=0.000000
 949 IDD3N=0.038000
 950 IDD3N2=0.000000
 951 IDD3P0=0.000000
 952 IDD3P02=0.000000
 953 IDD3P1=0.038000
 954 IDD3P12=0.000000
 955 IDD4R=0.157000
 956 IDD4R2=0.000000
 957 IDD4W=0.125000
 958 IDD4W2=0.000000
 959 IDD5=0.235000
 960 IDD52=0.000000
 961 IDD6=0.020000
 962 IDD62=0.000000
 963 VDD=1.500000
 964 VDD2=0.000000
 965 activation_limit=4
 966 addr_mapping=RoRaBaCoCh
 967 bank_groups_per_rank=0
 968 banks_per_rank=8
 969 burst_length=8
 970 channels=1
 971 clk_domain=system.clk_domain
 972 conf_table_reported=true
 973 default_p_state=UNDEFINED
 974 device_bus_width=8
 975 device_rowbuffer_size=1024
 976 device_size=536870912
 977 devices_per_rank=8
 978 dll=true
 979 eventq_index=0
 980 in_addr_map=true
 981 kvm_map=true
 982 max_accesses_per_row=16
 983 mem_sched_policy=frfcfs
 984 min_writes_per_switch=16
 985 null=false
 986 p_state_clk_gate_bins=20
 987 p_state_clk_gate_max=1000000000000
 988 p_state_clk_gate_min=1000
 989 page_policy=open_adaptive
 990 power_model=Null
 991 range=2147483648:2415919103:0:0:0:0
 992 ranks_per_channel=2
 993 read_buffer_size=32
 994 static_backend_latency=10000
 995 static_frontend_latency=10000
 996 tBURST=5000
 997 tCCD_L=0
 998 tCK=1250
 999 tCL=13750
1000 tCS=2500
1001 tRAS=35000
1002 tRCD=13750
1003 tREFI=7800000
1004 tRFC=260000
1005 tRP=13750
1006 tRRD=6000
1007 tRRD_L=0
1008 tRTP=7500
1009 tRTW=2500
1010 tWR=15000
1011 tWTR=7500
1012 tXAW=30000
1013 tXP=6000
1014 tXPDLL=0
1015 tXS=270000
1016 tXSDLL=0
1017 write_buffer_size=64
1018 write_high_thresh_perc=85
1019 write_low_thresh_perc=50
1020 port=system.membus.master[5]
1021
1022 [system.realview]
1023 type=RealView
1024 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1025 eventq_index=0
1026 intrctrl=system.intrctrl
1027 system=system
1028
1029 [system.realview.aaci_fake]
1030 type=AmbaFake
1031 amba_id=0
1032 clk_domain=system.clk_domain
1033 default_p_state=UNDEFINED
1034 eventq_index=0
1035 ignore_access=false
1036 p_state_clk_gate_bins=20
1037 p_state_clk_gate_max=1000000000000
1038 p_state_clk_gate_min=1000
1039 pio_addr=470024192
1040 pio_latency=100000
1041 power_model=Null
1042 system=system
1043 pio=system.iobus.master[18]
1044
1045 [system.realview.cf_ctrl]
1046 type=IdeController
1047 BAR0=471465984
1048 BAR0LegacyIO=true
1049 BAR0Size=256
1050 BAR1=471466240
1051 BAR1LegacyIO=true
1052 BAR1Size=4096
1053 BAR2=1
1054 BAR2LegacyIO=false
1055 BAR2Size=8
1056 BAR3=1
1057 BAR3LegacyIO=false
1058 BAR3Size=4
1059 BAR4=1
1060 BAR4LegacyIO=false
1061 BAR4Size=16
1062 BAR5=1
1063 BAR5LegacyIO=false
1064 BAR5Size=0
1065 BIST=0
1066 CacheLineSize=0
1067 CapabilityPtr=0
1068 CardbusCIS=0
1069 ClassCode=1
1070 Command=1
1071 DeviceID=28945
1072 ExpansionROM=0
1073 HeaderType=0
1074 InterruptLine=31
1075 InterruptPin=1
1076 LatencyTimer=0
1077 LegacyIOBase=0
1078 MSICAPBaseOffset=0
1079 MSICAPCapId=0
1080 MSICAPMaskBits=0
1081 MSICAPMsgAddr=0
1082 MSICAPMsgCtrl=0
1083 MSICAPMsgData=0
1084 MSICAPMsgUpperAddr=0
1085 MSICAPNextCapability=0
1086 MSICAPPendingBits=0
1087 MSIXCAPBaseOffset=0
1088 MSIXCAPCapId=0
1089 MSIXCAPNextCapability=0
1090 MSIXMsgCtrl=0
1091 MSIXPbaOffset=0
1092 MSIXTableOffset=0
1093 MaximumLatency=0
1094 MinimumGrant=0
1095 PMCAPBaseOffset=0
1096 PMCAPCapId=0
1097 PMCAPCapabilities=0
1098 PMCAPCtrlStatus=0
1099 PMCAPNextCapability=0
1100 PXCAPBaseOffset=0
1101 PXCAPCapId=0
1102 PXCAPCapabilities=0
1103 PXCAPDevCap2=0
1104 PXCAPDevCapabilities=0
1105 PXCAPDevCtrl=0
1106 PXCAPDevCtrl2=0
1107 PXCAPDevStatus=0
1108 PXCAPLinkCap=0
1109 PXCAPLinkCtrl=0
1110 PXCAPLinkStatus=0
1111 PXCAPNextCapability=0
1112 ProgIF=133
1113 Revision=0
1114 Status=640
1115 SubClassCode=1
1116 SubsystemID=0
1117 SubsystemVendorID=0
1118 VendorID=32902
1119 clk_domain=system.clk_domain
1120 config_latency=20000
1121 ctrl_offset=2
1122 default_p_state=UNDEFINED
1123 disks=
1124 eventq_index=0
1125 host=system.realview.pci_host
1126 io_shift=2
1127 p_state_clk_gate_bins=20
1128 p_state_clk_gate_max=1000000000000
1129 p_state_clk_gate_min=1000
1130 pci_bus=2
1131 pci_dev=0
1132 pci_func=0
1133 pio_latency=30000
1134 power_model=Null
1135 system=system
1136 dma=system.iobus.slave[2]
1137 pio=system.iobus.master[9]
1138
1139 [system.realview.clcd]
1140 type=Pl111
1141 amba_id=1315089
1142 clk_domain=system.clk_domain
1143 default_p_state=UNDEFINED
1144 enable_capture=true
1145 eventq_index=0
1146 gic=system.realview.gic
1147 int_num=46
1148 p_state_clk_gate_bins=20
1149 p_state_clk_gate_max=1000000000000
1150 p_state_clk_gate_min=1000
1151 pio_addr=471793664
1152 pio_latency=10000
1153 pixel_clock=41667
1154 power_model=Null
1155 system=system
1156 vnc=system.vncserver
1157 dma=system.iobus.slave[1]
1158 pio=system.iobus.master[5]
1159
1160 [system.realview.dcc]
1161 type=SubSystem
1162 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1163 eventq_index=0
1164 thermal_domain=Null
1165
1166 [system.realview.dcc.osc_cpu]
1167 type=RealViewOsc
1168 dcc=0
1169 device=0
1170 eventq_index=0
1171 freq=16667
1172 parent=system.realview.realview_io
1173 position=0
1174 site=1
1175 voltage_domain=system.voltage_domain
1176
1177 [system.realview.dcc.osc_ddr]
1178 type=RealViewOsc
1179 dcc=0
1180 device=8
1181 eventq_index=0
1182 freq=25000
1183 parent=system.realview.realview_io
1184 position=0
1185 site=1
1186 voltage_domain=system.voltage_domain
1187
1188 [system.realview.dcc.osc_hsbm]
1189 type=RealViewOsc
1190 dcc=0
1191 device=4
1192 eventq_index=0
1193 freq=25000
1194 parent=system.realview.realview_io
1195 position=0
1196 site=1
1197 voltage_domain=system.voltage_domain
1198
1199 [system.realview.dcc.osc_pxl]
1200 type=RealViewOsc
1201 dcc=0
1202 device=5
1203 eventq_index=0
1204 freq=42105
1205 parent=system.realview.realview_io
1206 position=0
1207 site=1
1208 voltage_domain=system.voltage_domain
1209
1210 [system.realview.dcc.osc_smb]
1211 type=RealViewOsc
1212 dcc=0
1213 device=6
1214 eventq_index=0
1215 freq=20000
1216 parent=system.realview.realview_io
1217 position=0
1218 site=1
1219 voltage_domain=system.voltage_domain
1220
1221 [system.realview.dcc.osc_sys]
1222 type=RealViewOsc
1223 dcc=0
1224 device=7
1225 eventq_index=0
1226 freq=16667
1227 parent=system.realview.realview_io
1228 position=0
1229 site=1
1230 voltage_domain=system.voltage_domain
1231
1232 [system.realview.energy_ctrl]
1233 type=EnergyCtrl
1234 clk_domain=system.clk_domain
1235 default_p_state=UNDEFINED
1236 dvfs_handler=system.dvfs_handler
1237 eventq_index=0
1238 p_state_clk_gate_bins=20
1239 p_state_clk_gate_max=1000000000000
1240 p_state_clk_gate_min=1000
1241 pio_addr=470286336
1242 pio_latency=100000
1243 power_model=Null
1244 system=system
1245 pio=system.iobus.master[22]
1246
1247 [system.realview.ethernet]
1248 type=IGbE
1249 BAR0=0
1250 BAR0LegacyIO=false
1251 BAR0Size=131072
1252 BAR1=0
1253 BAR1LegacyIO=false
1254 BAR1Size=0
1255 BAR2=0
1256 BAR2LegacyIO=false
1257 BAR2Size=0
1258 BAR3=0
1259 BAR3LegacyIO=false
1260 BAR3Size=0
1261 BAR4=0
1262 BAR4LegacyIO=false
1263 BAR4Size=0
1264 BAR5=0
1265 BAR5LegacyIO=false
1266 BAR5Size=0
1267 BIST=0
1268 CacheLineSize=0
1269 CapabilityPtr=0
1270 CardbusCIS=0
1271 ClassCode=2
1272 Command=0
1273 DeviceID=4213
1274 ExpansionROM=0
1275 HeaderType=0
1276 InterruptLine=1
1277 InterruptPin=1
1278 LatencyTimer=0
1279 LegacyIOBase=0
1280 MSICAPBaseOffset=0
1281 MSICAPCapId=0
1282 MSICAPMaskBits=0
1283 MSICAPMsgAddr=0
1284 MSICAPMsgCtrl=0
1285 MSICAPMsgData=0
1286 MSICAPMsgUpperAddr=0
1287 MSICAPNextCapability=0
1288 MSICAPPendingBits=0
1289 MSIXCAPBaseOffset=0
1290 MSIXCAPCapId=0
1291 MSIXCAPNextCapability=0
1292 MSIXMsgCtrl=0
1293 MSIXPbaOffset=0
1294 MSIXTableOffset=0
1295 MaximumLatency=0
1296 MinimumGrant=255
1297 PMCAPBaseOffset=0
1298 PMCAPCapId=0
1299 PMCAPCapabilities=0
1300 PMCAPCtrlStatus=0
1301 PMCAPNextCapability=0
1302 PXCAPBaseOffset=0
1303 PXCAPCapId=0
1304 PXCAPCapabilities=0
1305 PXCAPDevCap2=0
1306 PXCAPDevCapabilities=0
1307 PXCAPDevCtrl=0
1308 PXCAPDevCtrl2=0
1309 PXCAPDevStatus=0
1310 PXCAPLinkCap=0
1311 PXCAPLinkCtrl=0
1312 PXCAPLinkStatus=0
1313 PXCAPNextCapability=0
1314 ProgIF=0
1315 Revision=0
1316 Status=0
1317 SubClassCode=0
1318 SubsystemID=4104
1319 SubsystemVendorID=32902
1320 VendorID=32902
1321 clk_domain=system.clk_domain
1322 config_latency=20000
1323 default_p_state=UNDEFINED
1324 eventq_index=0
1325 fetch_comp_delay=10000
1326 fetch_delay=10000
1327 hardware_address=00:90:00:00:00:01
1328 host=system.realview.pci_host
1329 p_state_clk_gate_bins=20
1330 p_state_clk_gate_max=1000000000000
1331 p_state_clk_gate_min=1000
1332 pci_bus=0
1333 pci_dev=0
1334 pci_func=0
1335 phy_epid=896
1336 phy_pid=680
1337 pio_latency=30000
1338 power_model=Null
1339 rx_desc_cache_size=64
1340 rx_fifo_size=393216
1341 rx_write_delay=0
1342 system=system
1343 tx_desc_cache_size=64
1344 tx_fifo_size=393216
1345 tx_read_delay=0
1346 wb_comp_delay=10000
1347 wb_delay=10000
1348 dma=system.iobus.slave[4]
1349 pio=system.iobus.master[24]
1350
1351 [system.realview.generic_timer]
1352 type=GenericTimer
1353 eventq_index=0
1354 gic=system.realview.gic
1355 int_phys=29
1356 int_virt=27
1357 system=system
1358
1359 [system.realview.gic]
1360 type=Pl390
1361 clk_domain=system.clk_domain
1362 cpu_addr=738205696
1363 cpu_pio_delay=10000
1364 default_p_state=UNDEFINED
1365 dist_addr=738201600
1366 dist_pio_delay=10000
1367 eventq_index=0
1368 gem5_extensions=false
1369 int_latency=10000
1370 it_lines=128
1371 p_state_clk_gate_bins=20
1372 p_state_clk_gate_max=1000000000000
1373 p_state_clk_gate_min=1000
1374 platform=system.realview
1375 power_model=Null
1376 system=system
1377 pio=system.membus.master[2]
1378
1379 [system.realview.hdlcd]
1380 type=HDLcd
1381 amba_id=1314816
1382 clk_domain=system.clk_domain
1383 default_p_state=UNDEFINED
1384 enable_capture=true
1385 eventq_index=0
1386 gic=system.realview.gic
1387 int_num=117
1388 p_state_clk_gate_bins=20
1389 p_state_clk_gate_max=1000000000000
1390 p_state_clk_gate_min=1000
1391 pio_addr=721420288
1392 pio_latency=10000
1393 pixel_buffer_size=2048
1394 pixel_chunk=32
1395 power_model=Null
1396 pxl_clk=system.realview.dcc.osc_pxl
1397 system=system
1398 vnc=system.vncserver
1399 workaround_dma_line_count=true
1400 workaround_swap_rb=true
1401 dma=system.membus.slave[0]
1402 pio=system.iobus.master[6]
1403
1404 [system.realview.ide]
1405 type=IdeController
1406 BAR0=1
1407 BAR0LegacyIO=false
1408 BAR0Size=8
1409 BAR1=1
1410 BAR1LegacyIO=false
1411 BAR1Size=4
1412 BAR2=1
1413 BAR2LegacyIO=false
1414 BAR2Size=8
1415 BAR3=1
1416 BAR3LegacyIO=false
1417 BAR3Size=4
1418 BAR4=1
1419 BAR4LegacyIO=false
1420 BAR4Size=16
1421 BAR5=1
1422 BAR5LegacyIO=false
1423 BAR5Size=0
1424 BIST=0
1425 CacheLineSize=0
1426 CapabilityPtr=0
1427 CardbusCIS=0
1428 ClassCode=1
1429 Command=0
1430 DeviceID=28945
1431 ExpansionROM=0
1432 HeaderType=0
1433 InterruptLine=2
1434 InterruptPin=2
1435 LatencyTimer=0
1436 LegacyIOBase=0
1437 MSICAPBaseOffset=0
1438 MSICAPCapId=0
1439 MSICAPMaskBits=0
1440 MSICAPMsgAddr=0
1441 MSICAPMsgCtrl=0
1442 MSICAPMsgData=0
1443 MSICAPMsgUpperAddr=0
1444 MSICAPNextCapability=0
1445 MSICAPPendingBits=0
1446 MSIXCAPBaseOffset=0
1447 MSIXCAPCapId=0
1448 MSIXCAPNextCapability=0
1449 MSIXMsgCtrl=0
1450 MSIXPbaOffset=0
1451 MSIXTableOffset=0
1452 MaximumLatency=0
1453 MinimumGrant=0
1454 PMCAPBaseOffset=0
1455 PMCAPCapId=0
1456 PMCAPCapabilities=0
1457 PMCAPCtrlStatus=0
1458 PMCAPNextCapability=0
1459 PXCAPBaseOffset=0
1460 PXCAPCapId=0
1461 PXCAPCapabilities=0
1462 PXCAPDevCap2=0
1463 PXCAPDevCapabilities=0
1464 PXCAPDevCtrl=0
1465 PXCAPDevCtrl2=0
1466 PXCAPDevStatus=0
1467 PXCAPLinkCap=0
1468 PXCAPLinkCtrl=0
1469 PXCAPLinkStatus=0
1470 PXCAPNextCapability=0
1471 ProgIF=133
1472 Revision=0
1473 Status=640
1474 SubClassCode=1
1475 SubsystemID=0
1476 SubsystemVendorID=0
1477 VendorID=32902
1478 clk_domain=system.clk_domain
1479 config_latency=20000
1480 ctrl_offset=0
1481 default_p_state=UNDEFINED
1482 disks=system.cf0
1483 eventq_index=0
1484 host=system.realview.pci_host
1485 io_shift=0
1486 p_state_clk_gate_bins=20
1487 p_state_clk_gate_max=1000000000000
1488 p_state_clk_gate_min=1000
1489 pci_bus=0
1490 pci_dev=1
1491 pci_func=0
1492 pio_latency=30000
1493 power_model=Null
1494 system=system
1495 dma=system.iobus.slave[3]
1496 pio=system.iobus.master[23]
1497
1498 [system.realview.kmi0]
1499 type=Pl050
1500 amba_id=1314896
1501 clk_domain=system.clk_domain
1502 default_p_state=UNDEFINED
1503 eventq_index=0
1504 gic=system.realview.gic
1505 int_delay=1000000
1506 int_num=44
1507 is_mouse=false
1508 p_state_clk_gate_bins=20
1509 p_state_clk_gate_max=1000000000000
1510 p_state_clk_gate_min=1000
1511 pio_addr=470155264
1512 pio_latency=100000
1513 power_model=Null
1514 system=system
1515 vnc=system.vncserver
1516 pio=system.iobus.master[7]
1517
1518 [system.realview.kmi1]
1519 type=Pl050
1520 amba_id=1314896
1521 clk_domain=system.clk_domain
1522 default_p_state=UNDEFINED
1523 eventq_index=0
1524 gic=system.realview.gic
1525 int_delay=1000000
1526 int_num=45
1527 is_mouse=true
1528 p_state_clk_gate_bins=20
1529 p_state_clk_gate_max=1000000000000
1530 p_state_clk_gate_min=1000
1531 pio_addr=470220800
1532 pio_latency=100000
1533 power_model=Null
1534 system=system
1535 vnc=system.vncserver
1536 pio=system.iobus.master[8]
1537
1538 [system.realview.l2x0_fake]
1539 type=IsaFake
1540 clk_domain=system.clk_domain
1541 default_p_state=UNDEFINED
1542 eventq_index=0
1543 fake_mem=false
1544 p_state_clk_gate_bins=20
1545 p_state_clk_gate_max=1000000000000
1546 p_state_clk_gate_min=1000
1547 pio_addr=739246080
1548 pio_latency=100000
1549 pio_size=4095
1550 power_model=Null
1551 ret_bad_addr=false
1552 ret_data16=65535
1553 ret_data32=4294967295
1554 ret_data64=18446744073709551615
1555 ret_data8=255
1556 system=system
1557 update_data=false
1558 warn_access=
1559 pio=system.iobus.master[12]
1560
1561 [system.realview.lan_fake]
1562 type=IsaFake
1563 clk_domain=system.clk_domain
1564 default_p_state=UNDEFINED
1565 eventq_index=0
1566 fake_mem=false
1567 p_state_clk_gate_bins=20
1568 p_state_clk_gate_max=1000000000000
1569 p_state_clk_gate_min=1000
1570 pio_addr=436207616
1571 pio_latency=100000
1572 pio_size=65535
1573 power_model=Null
1574 ret_bad_addr=false
1575 ret_data16=65535
1576 ret_data32=4294967295
1577 ret_data64=18446744073709551615
1578 ret_data8=255
1579 system=system
1580 update_data=false
1581 warn_access=
1582 pio=system.iobus.master[19]
1583
1584 [system.realview.local_cpu_timer]
1585 type=CpuLocalTimer
1586 clk_domain=system.clk_domain
1587 default_p_state=UNDEFINED
1588 eventq_index=0
1589 gic=system.realview.gic
1590 int_num_timer=29
1591 int_num_watchdog=30
1592 p_state_clk_gate_bins=20
1593 p_state_clk_gate_max=1000000000000
1594 p_state_clk_gate_min=1000
1595 pio_addr=738721792
1596 pio_latency=100000
1597 power_model=Null
1598 system=system
1599 pio=system.membus.master[4]
1600
1601 [system.realview.mcc]
1602 type=SubSystem
1603 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1604 eventq_index=0
1605 thermal_domain=Null
1606
1607 [system.realview.mcc.osc_clcd]
1608 type=RealViewOsc
1609 dcc=0
1610 device=1
1611 eventq_index=0
1612 freq=42105
1613 parent=system.realview.realview_io
1614 position=0
1615 site=0
1616 voltage_domain=system.voltage_domain
1617
1618 [system.realview.mcc.osc_mcc]
1619 type=RealViewOsc
1620 dcc=0
1621 device=0
1622 eventq_index=0
1623 freq=20000
1624 parent=system.realview.realview_io
1625 position=0
1626 site=0
1627 voltage_domain=system.voltage_domain
1628
1629 [system.realview.mcc.osc_peripheral]
1630 type=RealViewOsc
1631 dcc=0
1632 device=2
1633 eventq_index=0
1634 freq=41667
1635 parent=system.realview.realview_io
1636 position=0
1637 site=0
1638 voltage_domain=system.voltage_domain
1639
1640 [system.realview.mcc.osc_system_bus]
1641 type=RealViewOsc
1642 dcc=0
1643 device=4
1644 eventq_index=0
1645 freq=41667
1646 parent=system.realview.realview_io
1647 position=0
1648 site=0
1649 voltage_domain=system.voltage_domain
1650
1651 [system.realview.mcc.temp_crtl]
1652 type=RealViewTemperatureSensor
1653 dcc=0
1654 device=0
1655 eventq_index=0
1656 parent=system.realview.realview_io
1657 position=0
1658 site=0
1659 system=system
1660
1661 [system.realview.mmc_fake]
1662 type=AmbaFake
1663 amba_id=0
1664 clk_domain=system.clk_domain
1665 default_p_state=UNDEFINED
1666 eventq_index=0
1667 ignore_access=false
1668 p_state_clk_gate_bins=20
1669 p_state_clk_gate_max=1000000000000
1670 p_state_clk_gate_min=1000
1671 pio_addr=470089728
1672 pio_latency=100000
1673 power_model=Null
1674 system=system
1675 pio=system.iobus.master[21]
1676
1677 [system.realview.nvmem]
1678 type=SimpleMemory
1679 bandwidth=73.000000
1680 clk_domain=system.clk_domain
1681 conf_table_reported=false
1682 default_p_state=UNDEFINED
1683 eventq_index=0
1684 in_addr_map=true
1685 kvm_map=true
1686 latency=30000
1687 latency_var=0
1688 null=false
1689 p_state_clk_gate_bins=20
1690 p_state_clk_gate_max=1000000000000
1691 p_state_clk_gate_min=1000
1692 power_model=Null
1693 range=0:67108863:0:0:0:0
1694 port=system.membus.master[1]
1695
1696 [system.realview.pci_host]
1697 type=GenericPciHost
1698 clk_domain=system.clk_domain
1699 conf_base=805306368
1700 conf_device_bits=12
1701 conf_size=268435456
1702 default_p_state=UNDEFINED
1703 eventq_index=0
1704 p_state_clk_gate_bins=20
1705 p_state_clk_gate_max=1000000000000
1706 p_state_clk_gate_min=1000
1707 pci_dma_base=0
1708 pci_mem_base=0
1709 pci_pio_base=788529152
1710 platform=system.realview
1711 power_model=Null
1712 system=system
1713 pio=system.iobus.master[2]
1714
1715 [system.realview.realview_io]
1716 type=RealViewCtrl
1717 clk_domain=system.clk_domain
1718 default_p_state=UNDEFINED
1719 eventq_index=0
1720 idreg=35979264
1721 p_state_clk_gate_bins=20
1722 p_state_clk_gate_max=1000000000000
1723 p_state_clk_gate_min=1000
1724 pio_addr=469827584
1725 pio_latency=100000
1726 power_model=Null
1727 proc_id0=335544320
1728 proc_id1=335544320
1729 system=system
1730 pio=system.iobus.master[1]
1731
1732 [system.realview.rtc]
1733 type=PL031
1734 amba_id=3412017
1735 clk_domain=system.clk_domain
1736 default_p_state=UNDEFINED
1737 eventq_index=0
1738 gic=system.realview.gic
1739 int_delay=100000
1740 int_num=36
1741 p_state_clk_gate_bins=20
1742 p_state_clk_gate_max=1000000000000
1743 p_state_clk_gate_min=1000
1744 pio_addr=471269376
1745 pio_latency=100000
1746 power_model=Null
1747 system=system
1748 time=Thu Jan  1 00:00:00 2009
1749 pio=system.iobus.master[10]
1750
1751 [system.realview.sp810_fake]
1752 type=AmbaFake
1753 amba_id=0
1754 clk_domain=system.clk_domain
1755 default_p_state=UNDEFINED
1756 eventq_index=0
1757 ignore_access=true
1758 p_state_clk_gate_bins=20
1759 p_state_clk_gate_max=1000000000000
1760 p_state_clk_gate_min=1000
1761 pio_addr=469893120
1762 pio_latency=100000
1763 power_model=Null
1764 system=system
1765 pio=system.iobus.master[16]
1766
1767 [system.realview.timer0]
1768 type=Sp804
1769 amba_id=1316868
1770 clk_domain=system.clk_domain
1771 clock0=1000000
1772 clock1=1000000
1773 default_p_state=UNDEFINED
1774 eventq_index=0
1775 gic=system.realview.gic
1776 int_num0=34
1777 int_num1=34
1778 p_state_clk_gate_bins=20
1779 p_state_clk_gate_max=1000000000000
1780 p_state_clk_gate_min=1000
1781 pio_addr=470876160
1782 pio_latency=100000
1783 power_model=Null
1784 system=system
1785 pio=system.iobus.master[3]
1786
1787 [system.realview.timer1]
1788 type=Sp804
1789 amba_id=1316868
1790 clk_domain=system.clk_domain
1791 clock0=1000000
1792 clock1=1000000
1793 default_p_state=UNDEFINED
1794 eventq_index=0
1795 gic=system.realview.gic
1796 int_num0=35
1797 int_num1=35
1798 p_state_clk_gate_bins=20
1799 p_state_clk_gate_max=1000000000000
1800 p_state_clk_gate_min=1000
1801 pio_addr=470941696
1802 pio_latency=100000
1803 power_model=Null
1804 system=system
1805 pio=system.iobus.master[4]
1806
1807 [system.realview.uart]
1808 type=Pl011
1809 clk_domain=system.clk_domain
1810 default_p_state=UNDEFINED
1811 end_on_eot=false
1812 eventq_index=0
1813 gic=system.realview.gic
1814 int_delay=100000
1815 int_num=37
1816 p_state_clk_gate_bins=20
1817 p_state_clk_gate_max=1000000000000
1818 p_state_clk_gate_min=1000
1819 pio_addr=470351872
1820 pio_latency=100000
1821 platform=system.realview
1822 power_model=Null
1823 system=system
1824 terminal=system.terminal
1825 pio=system.iobus.master[0]
1826
1827 [system.realview.uart1_fake]
1828 type=AmbaFake
1829 amba_id=0
1830 clk_domain=system.clk_domain
1831 default_p_state=UNDEFINED
1832 eventq_index=0
1833 ignore_access=false
1834 p_state_clk_gate_bins=20
1835 p_state_clk_gate_max=1000000000000
1836 p_state_clk_gate_min=1000
1837 pio_addr=470417408
1838 pio_latency=100000
1839 power_model=Null
1840 system=system
1841 pio=system.iobus.master[13]
1842
1843 [system.realview.uart2_fake]
1844 type=AmbaFake
1845 amba_id=0
1846 clk_domain=system.clk_domain
1847 default_p_state=UNDEFINED
1848 eventq_index=0
1849 ignore_access=false
1850 p_state_clk_gate_bins=20
1851 p_state_clk_gate_max=1000000000000
1852 p_state_clk_gate_min=1000
1853 pio_addr=470482944
1854 pio_latency=100000
1855 power_model=Null
1856 system=system
1857 pio=system.iobus.master[14]
1858
1859 [system.realview.uart3_fake]
1860 type=AmbaFake
1861 amba_id=0
1862 clk_domain=system.clk_domain
1863 default_p_state=UNDEFINED
1864 eventq_index=0
1865 ignore_access=false
1866 p_state_clk_gate_bins=20
1867 p_state_clk_gate_max=1000000000000
1868 p_state_clk_gate_min=1000
1869 pio_addr=470548480
1870 pio_latency=100000
1871 power_model=Null
1872 system=system
1873 pio=system.iobus.master[15]
1874
1875 [system.realview.usb_fake]
1876 type=IsaFake
1877 clk_domain=system.clk_domain
1878 default_p_state=UNDEFINED
1879 eventq_index=0
1880 fake_mem=false
1881 p_state_clk_gate_bins=20
1882 p_state_clk_gate_max=1000000000000
1883 p_state_clk_gate_min=1000
1884 pio_addr=452984832
1885 pio_latency=100000
1886 pio_size=131071
1887 power_model=Null
1888 ret_bad_addr=false
1889 ret_data16=65535
1890 ret_data32=4294967295
1891 ret_data64=18446744073709551615
1892 ret_data8=255
1893 system=system
1894 update_data=false
1895 warn_access=
1896 pio=system.iobus.master[20]
1897
1898 [system.realview.vgic]
1899 type=VGic
1900 clk_domain=system.clk_domain
1901 default_p_state=UNDEFINED
1902 eventq_index=0
1903 gic=system.realview.gic
1904 hv_addr=738213888
1905 p_state_clk_gate_bins=20
1906 p_state_clk_gate_max=1000000000000
1907 p_state_clk_gate_min=1000
1908 pio_delay=10000
1909 platform=system.realview
1910 power_model=Null
1911 ppint=25
1912 system=system
1913 vcpu_addr=738222080
1914 pio=system.membus.master[3]
1915
1916 [system.realview.vram]
1917 type=SimpleMemory
1918 bandwidth=73.000000
1919 clk_domain=system.clk_domain
1920 conf_table_reported=false
1921 default_p_state=UNDEFINED
1922 eventq_index=0
1923 in_addr_map=true
1924 kvm_map=true
1925 latency=30000
1926 latency_var=0
1927 null=false
1928 p_state_clk_gate_bins=20
1929 p_state_clk_gate_max=1000000000000
1930 p_state_clk_gate_min=1000
1931 power_model=Null
1932 range=402653184:436207615:0:0:0:0
1933 port=system.iobus.master[11]
1934
1935 [system.realview.watchdog_fake]
1936 type=AmbaFake
1937 amba_id=0
1938 clk_domain=system.clk_domain
1939 default_p_state=UNDEFINED
1940 eventq_index=0
1941 ignore_access=false
1942 p_state_clk_gate_bins=20
1943 p_state_clk_gate_max=1000000000000
1944 p_state_clk_gate_min=1000
1945 pio_addr=470745088
1946 pio_latency=100000
1947 power_model=Null
1948 system=system
1949 pio=system.iobus.master[17]
1950
1951 [system.terminal]
1952 type=Terminal
1953 eventq_index=0
1954 intr_control=system.intrctrl
1955 number=0
1956 output=true
1957 port=3456
1958
1959 [system.vncserver]
1960 type=VncServer
1961 eventq_index=0
1962 frame_capture=false
1963 number=0
1964 port=5900
1965
1966 [system.voltage_domain]
1967 type=VoltageDomain
1968 eventq_index=0
1969 voltage=1.000000
1970