tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM64
  38 mem_mode=atomic
  39 mem_ranges=2147483648:2415919103
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu0]
 114 type=AtomicSimpleCPU
 115 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=Null
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 default_p_state=UNDEFINED
 121 do_checkpoint_insts=true
 122 do_quiesce=true
 123 do_statistics_insts=true
 124 dstage2_mmu=system.cpu0.dstage2_mmu
 125 dtb=system.cpu0.dtb
 126 eventq_index=0
 127 fastmem=false
 128 function_trace=false
 129 function_trace_start=0
 130 interrupts=system.cpu0.interrupts
 131 isa=system.cpu0.isa
 132 istage2_mmu=system.cpu0.istage2_mmu
 133 itb=system.cpu0.itb
 134 max_insts_all_threads=0
 135 max_insts_any_thread=0
 136 max_loads_all_threads=0
 137 max_loads_any_thread=0
 138 numThreads=1
 139 p_state_clk_gate_bins=20
 140 p_state_clk_gate_max=1000000000000
 141 p_state_clk_gate_min=1000
 142 power_model=Null
 143 profile=0
 144 progress_interval=0
 145 simpoint_start_insts=
 146 simulate_data_stalls=false
 147 simulate_inst_stalls=false
 148 socket_id=0
 149 switched_out=false
 150 system=system
 151 tracer=system.cpu0.tracer
 152 width=1
 153 workload=
 154 dcache_port=system.cpu0.dcache.cpu_side
 155 icache_port=system.cpu0.icache.cpu_side
 156
 157 [system.cpu0.dcache]
 158 type=Cache
 159 children=tags
 160 addr_ranges=0:18446744073709551615
 161 assoc=2
 162 clk_domain=system.cpu_clk_domain
 163 clusivity=mostly_incl
 164 default_p_state=UNDEFINED
 165 demand_mshr_reserve=1
 166 eventq_index=0
 167 hit_latency=2
 168 is_read_only=false
 169 max_miss_count=0
 170 mshrs=6
 171 p_state_clk_gate_bins=20
 172 p_state_clk_gate_max=1000000000000
 173 p_state_clk_gate_min=1000
 174 power_model=Null
 175 prefetch_on_access=false
 176 prefetcher=Null
 177 response_latency=2
 178 sequential_access=false
 179 size=32768
 180 system=system
 181 tags=system.cpu0.dcache.tags
 182 tgts_per_mshr=8
 183 write_buffers=16
 184 writeback_clean=true
 185 cpu_side=system.cpu0.dcache_port
 186 mem_side=system.cpu0.toL2Bus.slave[1]
 187
 188 [system.cpu0.dcache.tags]
 189 type=LRU
 190 assoc=2
 191 block_size=64
 192 clk_domain=system.cpu_clk_domain
 193 default_p_state=UNDEFINED
 194 eventq_index=0
 195 hit_latency=2
 196 p_state_clk_gate_bins=20
 197 p_state_clk_gate_max=1000000000000
 198 p_state_clk_gate_min=1000
 199 power_model=Null
 200 sequential_access=false
 201 size=32768
 202
 203 [system.cpu0.dstage2_mmu]
 204 type=ArmStage2MMU
 205 children=stage2_tlb
 206 eventq_index=0
 207 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 208 sys=system
 209 tlb=system.cpu0.dtb
 210
 211 [system.cpu0.dstage2_mmu.stage2_tlb]
 212 type=ArmTLB
 213 children=walker
 214 eventq_index=0
 215 is_stage2=true
 216 size=32
 217 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 218
 219 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 220 type=ArmTableWalker
 221 clk_domain=system.cpu_clk_domain
 222 default_p_state=UNDEFINED
 223 eventq_index=0
 224 is_stage2=true
 225 num_squash_per_cycle=2
 226 p_state_clk_gate_bins=20
 227 p_state_clk_gate_max=1000000000000
 228 p_state_clk_gate_min=1000
 229 power_model=Null
 230 sys=system
 231
 232 [system.cpu0.dtb]
 233 type=ArmTLB
 234 children=walker
 235 eventq_index=0
 236 is_stage2=false
 237 size=64
 238 walker=system.cpu0.dtb.walker
 239
 240 [system.cpu0.dtb.walker]
 241 type=ArmTableWalker
 242 clk_domain=system.cpu_clk_domain
 243 default_p_state=UNDEFINED
 244 eventq_index=0
 245 is_stage2=false
 246 num_squash_per_cycle=2
 247 p_state_clk_gate_bins=20
 248 p_state_clk_gate_max=1000000000000
 249 p_state_clk_gate_min=1000
 250 power_model=Null
 251 sys=system
 252 port=system.cpu0.toL2Bus.slave[3]
 253
 254 [system.cpu0.icache]
 255 type=Cache
 256 children=tags
 257 addr_ranges=0:18446744073709551615
 258 assoc=2
 259 clk_domain=system.cpu_clk_domain
 260 clusivity=mostly_incl
 261 default_p_state=UNDEFINED
 262 demand_mshr_reserve=1
 263 eventq_index=0
 264 hit_latency=1
 265 is_read_only=true
 266 max_miss_count=0
 267 mshrs=2
 268 p_state_clk_gate_bins=20
 269 p_state_clk_gate_max=1000000000000
 270 p_state_clk_gate_min=1000
 271 power_model=Null
 272 prefetch_on_access=false
 273 prefetcher=Null
 274 response_latency=1
 275 sequential_access=false
 276 size=32768
 277 system=system
 278 tags=system.cpu0.icache.tags
 279 tgts_per_mshr=8
 280 write_buffers=8
 281 writeback_clean=true
 282 cpu_side=system.cpu0.icache_port
 283 mem_side=system.cpu0.toL2Bus.slave[0]
 284
 285 [system.cpu0.icache.tags]
 286 type=LRU
 287 assoc=2
 288 block_size=64
 289 clk_domain=system.cpu_clk_domain
 290 default_p_state=UNDEFINED
 291 eventq_index=0
 292 hit_latency=1
 293 p_state_clk_gate_bins=20
 294 p_state_clk_gate_max=1000000000000
 295 p_state_clk_gate_min=1000
 296 power_model=Null
 297 sequential_access=false
 298 size=32768
 299
 300 [system.cpu0.interrupts]
 301 type=ArmInterrupts
 302 eventq_index=0
 303
 304 [system.cpu0.isa]
 305 type=ArmISA
 306 decoderFlavour=Generic
 307 eventq_index=0
 308 fpsid=1090793632
 309 id_aa64afr0_el1=0
 310 id_aa64afr1_el1=0
 311 id_aa64dfr0_el1=1052678
 312 id_aa64dfr1_el1=0
 313 id_aa64isar0_el1=0
 314 id_aa64isar1_el1=0
 315 id_aa64mmfr0_el1=15728642
 316 id_aa64mmfr1_el1=0
 317 id_aa64pfr0_el1=17
 318 id_aa64pfr1_el1=0
 319 id_isar0=34607377
 320 id_isar1=34677009
 321 id_isar2=555950401
 322 id_isar3=17899825
 323 id_isar4=268501314
 324 id_isar5=0
 325 id_mmfr0=270536963
 326 id_mmfr1=0
 327 id_mmfr2=19070976
 328 id_mmfr3=34611729
 329 id_pfr0=49
 330 id_pfr1=4113
 331 midr=1091551472
 332 pmu=Null
 333 system=system
 334
 335 [system.cpu0.istage2_mmu]
 336 type=ArmStage2MMU
 337 children=stage2_tlb
 338 eventq_index=0
 339 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 340 sys=system
 341 tlb=system.cpu0.itb
 342
 343 [system.cpu0.istage2_mmu.stage2_tlb]
 344 type=ArmTLB
 345 children=walker
 346 eventq_index=0
 347 is_stage2=true
 348 size=32
 349 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 350
 351 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 352 type=ArmTableWalker
 353 clk_domain=system.cpu_clk_domain
 354 default_p_state=UNDEFINED
 355 eventq_index=0
 356 is_stage2=true
 357 num_squash_per_cycle=2
 358 p_state_clk_gate_bins=20
 359 p_state_clk_gate_max=1000000000000
 360 p_state_clk_gate_min=1000
 361 power_model=Null
 362 sys=system
 363
 364 [system.cpu0.itb]
 365 type=ArmTLB
 366 children=walker
 367 eventq_index=0
 368 is_stage2=false
 369 size=64
 370 walker=system.cpu0.itb.walker
 371
 372 [system.cpu0.itb.walker]
 373 type=ArmTableWalker
 374 clk_domain=system.cpu_clk_domain
 375 default_p_state=UNDEFINED
 376 eventq_index=0
 377 is_stage2=false
 378 num_squash_per_cycle=2
 379 p_state_clk_gate_bins=20
 380 p_state_clk_gate_max=1000000000000
 381 p_state_clk_gate_min=1000
 382 power_model=Null
 383 sys=system
 384 port=system.cpu0.toL2Bus.slave[2]
 385
 386 [system.cpu0.l2cache]
 387 type=Cache
 388 children=prefetcher tags
 389 addr_ranges=0:18446744073709551615
 390 assoc=16
 391 clk_domain=system.cpu_clk_domain
 392 clusivity=mostly_excl
 393 default_p_state=UNDEFINED
 394 demand_mshr_reserve=1
 395 eventq_index=0
 396 hit_latency=12
 397 is_read_only=false
 398 max_miss_count=0
 399 mshrs=16
 400 p_state_clk_gate_bins=20
 401 p_state_clk_gate_max=1000000000000
 402 p_state_clk_gate_min=1000
 403 power_model=Null
 404 prefetch_on_access=true
 405 prefetcher=system.cpu0.l2cache.prefetcher
 406 response_latency=12
 407 sequential_access=false
 408 size=1048576
 409 system=system
 410 tags=system.cpu0.l2cache.tags
 411 tgts_per_mshr=8
 412 write_buffers=8
 413 writeback_clean=false
 414 cpu_side=system.cpu0.toL2Bus.master[0]
 415 mem_side=system.toL2Bus.slave[0]
 416
 417 [system.cpu0.l2cache.prefetcher]
 418 type=StridePrefetcher
 419 cache_snoop=false
 420 clk_domain=system.cpu_clk_domain
 421 default_p_state=UNDEFINED
 422 degree=8
 423 eventq_index=0
 424 latency=1
 425 max_conf=7
 426 min_conf=0
 427 on_data=true
 428 on_inst=true
 429 on_miss=false
 430 on_read=true
 431 on_write=true
 432 p_state_clk_gate_bins=20
 433 p_state_clk_gate_max=1000000000000
 434 p_state_clk_gate_min=1000
 435 power_model=Null
 436 queue_filter=true
 437 queue_size=32
 438 queue_squash=true
 439 start_conf=4
 440 sys=system
 441 table_assoc=4
 442 table_sets=16
 443 tag_prefetch=true
 444 thresh_conf=4
 445 use_master_id=true
 446
 447 [system.cpu0.l2cache.tags]
 448 type=RandomRepl
 449 assoc=16
 450 block_size=64
 451 clk_domain=system.cpu_clk_domain
 452 default_p_state=UNDEFINED
 453 eventq_index=0
 454 hit_latency=12
 455 p_state_clk_gate_bins=20
 456 p_state_clk_gate_max=1000000000000
 457 p_state_clk_gate_min=1000
 458 power_model=Null
 459 sequential_access=false
 460 size=1048576
 461
 462 [system.cpu0.toL2Bus]
 463 type=CoherentXBar
 464 children=snoop_filter
 465 clk_domain=system.cpu_clk_domain
 466 default_p_state=UNDEFINED
 467 eventq_index=0
 468 forward_latency=0
 469 frontend_latency=1
 470 p_state_clk_gate_bins=20
 471 p_state_clk_gate_max=1000000000000
 472 p_state_clk_gate_min=1000
 473 point_of_coherency=false
 474 power_model=Null
 475 response_latency=1
 476 snoop_filter=system.cpu0.toL2Bus.snoop_filter
 477 snoop_response_latency=1
 478 system=system
 479 use_default_range=false
 480 width=32
 481 master=system.cpu0.l2cache.cpu_side
 482 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 483
 484 [system.cpu0.toL2Bus.snoop_filter]
 485 type=SnoopFilter
 486 eventq_index=0
 487 lookup_latency=0
 488 max_capacity=8388608
 489 system=system
 490
 491 [system.cpu0.tracer]
 492 type=ExeTracer
 493 eventq_index=0
 494
 495 [system.cpu1]
 496 type=AtomicSimpleCPU
 497 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 498 branchPred=Null
 499 checker=Null
 500 clk_domain=system.cpu_clk_domain
 501 cpu_id=1
 502 default_p_state=UNDEFINED
 503 do_checkpoint_insts=true
 504 do_quiesce=true
 505 do_statistics_insts=true
 506 dstage2_mmu=system.cpu1.dstage2_mmu
 507 dtb=system.cpu1.dtb
 508 eventq_index=0
 509 fastmem=false
 510 function_trace=false
 511 function_trace_start=0
 512 interrupts=system.cpu1.interrupts
 513 isa=system.cpu1.isa
 514 istage2_mmu=system.cpu1.istage2_mmu
 515 itb=system.cpu1.itb
 516 max_insts_all_threads=0
 517 max_insts_any_thread=0
 518 max_loads_all_threads=0
 519 max_loads_any_thread=0
 520 numThreads=1
 521 p_state_clk_gate_bins=20
 522 p_state_clk_gate_max=1000000000000
 523 p_state_clk_gate_min=1000
 524 power_model=Null
 525 profile=0
 526 progress_interval=0
 527 simpoint_start_insts=
 528 simulate_data_stalls=false
 529 simulate_inst_stalls=false
 530 socket_id=0
 531 switched_out=false
 532 system=system
 533 tracer=system.cpu1.tracer
 534 width=1
 535 workload=
 536 dcache_port=system.cpu1.dcache.cpu_side
 537 icache_port=system.cpu1.icache.cpu_side
 538
 539 [system.cpu1.dcache]
 540 type=Cache
 541 children=tags
 542 addr_ranges=0:18446744073709551615
 543 assoc=2
 544 clk_domain=system.cpu_clk_domain
 545 clusivity=mostly_incl
 546 default_p_state=UNDEFINED
 547 demand_mshr_reserve=1
 548 eventq_index=0
 549 hit_latency=2
 550 is_read_only=false
 551 max_miss_count=0
 552 mshrs=6
 553 p_state_clk_gate_bins=20
 554 p_state_clk_gate_max=1000000000000
 555 p_state_clk_gate_min=1000
 556 power_model=Null
 557 prefetch_on_access=false
 558 prefetcher=Null
 559 response_latency=2
 560 sequential_access=false
 561 size=32768
 562 system=system
 563 tags=system.cpu1.dcache.tags
 564 tgts_per_mshr=8
 565 write_buffers=16
 566 writeback_clean=true
 567 cpu_side=system.cpu1.dcache_port
 568 mem_side=system.cpu1.toL2Bus.slave[1]
 569
 570 [system.cpu1.dcache.tags]
 571 type=LRU
 572 assoc=2
 573 block_size=64
 574 clk_domain=system.cpu_clk_domain
 575 default_p_state=UNDEFINED
 576 eventq_index=0
 577 hit_latency=2
 578 p_state_clk_gate_bins=20
 579 p_state_clk_gate_max=1000000000000
 580 p_state_clk_gate_min=1000
 581 power_model=Null
 582 sequential_access=false
 583 size=32768
 584
 585 [system.cpu1.dstage2_mmu]
 586 type=ArmStage2MMU
 587 children=stage2_tlb
 588 eventq_index=0
 589 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
 590 sys=system
 591 tlb=system.cpu1.dtb
 592
 593 [system.cpu1.dstage2_mmu.stage2_tlb]
 594 type=ArmTLB
 595 children=walker
 596 eventq_index=0
 597 is_stage2=true
 598 size=32
 599 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
 600
 601 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
 602 type=ArmTableWalker
 603 clk_domain=system.cpu_clk_domain
 604 default_p_state=UNDEFINED
 605 eventq_index=0
 606 is_stage2=true
 607 num_squash_per_cycle=2
 608 p_state_clk_gate_bins=20
 609 p_state_clk_gate_max=1000000000000
 610 p_state_clk_gate_min=1000
 611 power_model=Null
 612 sys=system
 613
 614 [system.cpu1.dtb]
 615 type=ArmTLB
 616 children=walker
 617 eventq_index=0
 618 is_stage2=false
 619 size=64
 620 walker=system.cpu1.dtb.walker
 621
 622 [system.cpu1.dtb.walker]
 623 type=ArmTableWalker
 624 clk_domain=system.cpu_clk_domain
 625 default_p_state=UNDEFINED
 626 eventq_index=0
 627 is_stage2=false
 628 num_squash_per_cycle=2
 629 p_state_clk_gate_bins=20
 630 p_state_clk_gate_max=1000000000000
 631 p_state_clk_gate_min=1000
 632 power_model=Null
 633 sys=system
 634 port=system.cpu1.toL2Bus.slave[3]
 635
 636 [system.cpu1.icache]
 637 type=Cache
 638 children=tags
 639 addr_ranges=0:18446744073709551615
 640 assoc=2
 641 clk_domain=system.cpu_clk_domain
 642 clusivity=mostly_incl
 643 default_p_state=UNDEFINED
 644 demand_mshr_reserve=1
 645 eventq_index=0
 646 hit_latency=1
 647 is_read_only=true
 648 max_miss_count=0
 649 mshrs=2
 650 p_state_clk_gate_bins=20
 651 p_state_clk_gate_max=1000000000000
 652 p_state_clk_gate_min=1000
 653 power_model=Null
 654 prefetch_on_access=false
 655 prefetcher=Null
 656 response_latency=1
 657 sequential_access=false
 658 size=32768
 659 system=system
 660 tags=system.cpu1.icache.tags
 661 tgts_per_mshr=8
 662 write_buffers=8
 663 writeback_clean=true
 664 cpu_side=system.cpu1.icache_port
 665 mem_side=system.cpu1.toL2Bus.slave[0]
 666
 667 [system.cpu1.icache.tags]
 668 type=LRU
 669 assoc=2
 670 block_size=64
 671 clk_domain=system.cpu_clk_domain
 672 default_p_state=UNDEFINED
 673 eventq_index=0
 674 hit_latency=1
 675 p_state_clk_gate_bins=20
 676 p_state_clk_gate_max=1000000000000
 677 p_state_clk_gate_min=1000
 678 power_model=Null
 679 sequential_access=false
 680 size=32768
 681
 682 [system.cpu1.interrupts]
 683 type=ArmInterrupts
 684 eventq_index=0
 685
 686 [system.cpu1.isa]
 687 type=ArmISA
 688 decoderFlavour=Generic
 689 eventq_index=0
 690 fpsid=1090793632
 691 id_aa64afr0_el1=0
 692 id_aa64afr1_el1=0
 693 id_aa64dfr0_el1=1052678
 694 id_aa64dfr1_el1=0
 695 id_aa64isar0_el1=0
 696 id_aa64isar1_el1=0
 697 id_aa64mmfr0_el1=15728642
 698 id_aa64mmfr1_el1=0
 699 id_aa64pfr0_el1=17
 700 id_aa64pfr1_el1=0
 701 id_isar0=34607377
 702 id_isar1=34677009
 703 id_isar2=555950401
 704 id_isar3=17899825
 705 id_isar4=268501314
 706 id_isar5=0
 707 id_mmfr0=270536963
 708 id_mmfr1=0
 709 id_mmfr2=19070976
 710 id_mmfr3=34611729
 711 id_pfr0=49
 712 id_pfr1=4113
 713 midr=1091551472
 714 pmu=Null
 715 system=system
 716
 717 [system.cpu1.istage2_mmu]
 718 type=ArmStage2MMU
 719 children=stage2_tlb
 720 eventq_index=0
 721 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
 722 sys=system
 723 tlb=system.cpu1.itb
 724
 725 [system.cpu1.istage2_mmu.stage2_tlb]
 726 type=ArmTLB
 727 children=walker
 728 eventq_index=0
 729 is_stage2=true
 730 size=32
 731 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
 732
 733 [system.cpu1.istage2_mmu.stage2_tlb.walker]
 734 type=ArmTableWalker
 735 clk_domain=system.cpu_clk_domain
 736 default_p_state=UNDEFINED
 737 eventq_index=0
 738 is_stage2=true
 739 num_squash_per_cycle=2
 740 p_state_clk_gate_bins=20
 741 p_state_clk_gate_max=1000000000000
 742 p_state_clk_gate_min=1000
 743 power_model=Null
 744 sys=system
 745
 746 [system.cpu1.itb]
 747 type=ArmTLB
 748 children=walker
 749 eventq_index=0
 750 is_stage2=false
 751 size=64
 752 walker=system.cpu1.itb.walker
 753
 754 [system.cpu1.itb.walker]
 755 type=ArmTableWalker
 756 clk_domain=system.cpu_clk_domain
 757 default_p_state=UNDEFINED
 758 eventq_index=0
 759 is_stage2=false
 760 num_squash_per_cycle=2
 761 p_state_clk_gate_bins=20
 762 p_state_clk_gate_max=1000000000000
 763 p_state_clk_gate_min=1000
 764 power_model=Null
 765 sys=system
 766 port=system.cpu1.toL2Bus.slave[2]
 767
 768 [system.cpu1.l2cache]
 769 type=Cache
 770 children=prefetcher tags
 771 addr_ranges=0:18446744073709551615
 772 assoc=16
 773 clk_domain=system.cpu_clk_domain
 774 clusivity=mostly_excl
 775 default_p_state=UNDEFINED
 776 demand_mshr_reserve=1
 777 eventq_index=0
 778 hit_latency=12
 779 is_read_only=false
 780 max_miss_count=0
 781 mshrs=16
 782 p_state_clk_gate_bins=20
 783 p_state_clk_gate_max=1000000000000
 784 p_state_clk_gate_min=1000
 785 power_model=Null
 786 prefetch_on_access=true
 787 prefetcher=system.cpu1.l2cache.prefetcher
 788 response_latency=12
 789 sequential_access=false
 790 size=1048576
 791 system=system
 792 tags=system.cpu1.l2cache.tags
 793 tgts_per_mshr=8
 794 write_buffers=8
 795 writeback_clean=false
 796 cpu_side=system.cpu1.toL2Bus.master[0]
 797 mem_side=system.toL2Bus.slave[1]
 798
 799 [system.cpu1.l2cache.prefetcher]
 800 type=StridePrefetcher
 801 cache_snoop=false
 802 clk_domain=system.cpu_clk_domain
 803 default_p_state=UNDEFINED
 804 degree=8
 805 eventq_index=0
 806 latency=1
 807 max_conf=7
 808 min_conf=0
 809 on_data=true
 810 on_inst=true
 811 on_miss=false
 812 on_read=true
 813 on_write=true
 814 p_state_clk_gate_bins=20
 815 p_state_clk_gate_max=1000000000000
 816 p_state_clk_gate_min=1000
 817 power_model=Null
 818 queue_filter=true
 819 queue_size=32
 820 queue_squash=true
 821 start_conf=4
 822 sys=system
 823 table_assoc=4
 824 table_sets=16
 825 tag_prefetch=true
 826 thresh_conf=4
 827 use_master_id=true
 828
 829 [system.cpu1.l2cache.tags]
 830 type=RandomRepl
 831 assoc=16
 832 block_size=64
 833 clk_domain=system.cpu_clk_domain
 834 default_p_state=UNDEFINED
 835 eventq_index=0
 836 hit_latency=12
 837 p_state_clk_gate_bins=20
 838 p_state_clk_gate_max=1000000000000
 839 p_state_clk_gate_min=1000
 840 power_model=Null
 841 sequential_access=false
 842 size=1048576
 843
 844 [system.cpu1.toL2Bus]
 845 type=CoherentXBar
 846 children=snoop_filter
 847 clk_domain=system.cpu_clk_domain
 848 default_p_state=UNDEFINED
 849 eventq_index=0
 850 forward_latency=0
 851 frontend_latency=1
 852 p_state_clk_gate_bins=20
 853 p_state_clk_gate_max=1000000000000
 854 p_state_clk_gate_min=1000
 855 point_of_coherency=false
 856 power_model=Null
 857 response_latency=1
 858 snoop_filter=system.cpu1.toL2Bus.snoop_filter
 859 snoop_response_latency=1
 860 system=system
 861 use_default_range=false
 862 width=32
 863 master=system.cpu1.l2cache.cpu_side
 864 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 865
 866 [system.cpu1.toL2Bus.snoop_filter]
 867 type=SnoopFilter
 868 eventq_index=0
 869 lookup_latency=0
 870 max_capacity=8388608
 871 system=system
 872
 873 [system.cpu1.tracer]
 874 type=ExeTracer
 875 eventq_index=0
 876
 877 [system.cpu_clk_domain]
 878 type=SrcClockDomain
 879 clock=500
 880 domain_id=-1
 881 eventq_index=0
 882 init_perf_level=0
 883 voltage_domain=system.voltage_domain
 884
 885 [system.dvfs_handler]
 886 type=DVFSHandler
 887 domains=
 888 enable=false
 889 eventq_index=0
 890 sys_clk_domain=system.clk_domain
 891 transition_latency=100000000
 892
 893 [system.intrctrl]
 894 type=IntrControl
 895 eventq_index=0
 896 sys=system
 897
 898 [system.iobus]
 899 type=NoncoherentXBar
 900 clk_domain=system.clk_domain
 901 default_p_state=UNDEFINED
 902 eventq_index=0
 903 forward_latency=1
 904 frontend_latency=2
 905 p_state_clk_gate_bins=20
 906 p_state_clk_gate_max=1000000000000
 907 p_state_clk_gate_min=1000
 908 power_model=Null
 909 response_latency=2
 910 use_default_range=false
 911 width=16
 912 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 913 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 914
 915 [system.iocache]
 916 type=Cache
 917 children=tags
 918 addr_ranges=2147483648:2415919103
 919 assoc=8
 920 clk_domain=system.clk_domain
 921 clusivity=mostly_incl
 922 default_p_state=UNDEFINED
 923 demand_mshr_reserve=1
 924 eventq_index=0
 925 hit_latency=50
 926 is_read_only=false
 927 max_miss_count=0
 928 mshrs=20
 929 p_state_clk_gate_bins=20
 930 p_state_clk_gate_max=1000000000000
 931 p_state_clk_gate_min=1000
 932 power_model=Null
 933 prefetch_on_access=false
 934 prefetcher=Null
 935 response_latency=50
 936 sequential_access=false
 937 size=1024
 938 system=system
 939 tags=system.iocache.tags
 940 tgts_per_mshr=12
 941 write_buffers=8
 942 writeback_clean=false
 943 cpu_side=system.iobus.master[25]
 944 mem_side=system.membus.slave[3]
 945
 946 [system.iocache.tags]
 947 type=LRU
 948 assoc=8
 949 block_size=64
 950 clk_domain=system.clk_domain
 951 default_p_state=UNDEFINED
 952 eventq_index=0
 953 hit_latency=50
 954 p_state_clk_gate_bins=20
 955 p_state_clk_gate_max=1000000000000
 956 p_state_clk_gate_min=1000
 957 power_model=Null
 958 sequential_access=false
 959 size=1024
 960
 961 [system.l2c]
 962 type=Cache
 963 children=tags
 964 addr_ranges=0:18446744073709551615
 965 assoc=8
 966 clk_domain=system.cpu_clk_domain
 967 clusivity=mostly_incl
 968 default_p_state=UNDEFINED
 969 demand_mshr_reserve=1
 970 eventq_index=0
 971 hit_latency=20
 972 is_read_only=false
 973 max_miss_count=0
 974 mshrs=20
 975 p_state_clk_gate_bins=20
 976 p_state_clk_gate_max=1000000000000
 977 p_state_clk_gate_min=1000
 978 power_model=Null
 979 prefetch_on_access=false
 980 prefetcher=Null
 981 response_latency=20
 982 sequential_access=false
 983 size=4194304
 984 system=system
 985 tags=system.l2c.tags
 986 tgts_per_mshr=12
 987 write_buffers=8
 988 writeback_clean=false
 989 cpu_side=system.toL2Bus.master[0]
 990 mem_side=system.membus.slave[2]
 991
 992 [system.l2c.tags]
 993 type=LRU
 994 assoc=8
 995 block_size=64
 996 clk_domain=system.cpu_clk_domain
 997 default_p_state=UNDEFINED
 998 eventq_index=0
 999 hit_latency=20
1000 p_state_clk_gate_bins=20
1001 p_state_clk_gate_max=1000000000000
1002 p_state_clk_gate_min=1000
1003 power_model=Null
1004 sequential_access=false
1005 size=4194304
1006
1007 [system.membus]
1008 type=CoherentXBar
1009 children=badaddr_responder snoop_filter
1010 clk_domain=system.clk_domain
1011 default_p_state=UNDEFINED
1012 eventq_index=0
1013 forward_latency=4
1014 frontend_latency=3
1015 p_state_clk_gate_bins=20
1016 p_state_clk_gate_max=1000000000000
1017 p_state_clk_gate_min=1000
1018 point_of_coherency=true
1019 power_model=Null
1020 response_latency=2
1021 snoop_filter=system.membus.snoop_filter
1022 snoop_response_latency=4
1023 system=system
1024 use_default_range=false
1025 width=16
1026 default=system.membus.badaddr_responder.pio
1027 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1028 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1029
1030 [system.membus.badaddr_responder]
1031 type=IsaFake
1032 clk_domain=system.clk_domain
1033 default_p_state=UNDEFINED
1034 eventq_index=0
1035 fake_mem=false
1036 p_state_clk_gate_bins=20
1037 p_state_clk_gate_max=1000000000000
1038 p_state_clk_gate_min=1000
1039 pio_addr=0
1040 pio_latency=100000
1041 pio_size=8
1042 power_model=Null
1043 ret_bad_addr=true
1044 ret_data16=65535
1045 ret_data32=4294967295
1046 ret_data64=18446744073709551615
1047 ret_data8=255
1048 system=system
1049 update_data=false
1050 warn_access=warn
1051 pio=system.membus.default
1052
1053 [system.membus.snoop_filter]
1054 type=SnoopFilter
1055 eventq_index=0
1056 lookup_latency=1
1057 max_capacity=8388608
1058 system=system
1059
1060 [system.physmem]
1061 type=SimpleMemory
1062 bandwidth=73.000000
1063 clk_domain=system.clk_domain
1064 conf_table_reported=true
1065 default_p_state=UNDEFINED
1066 eventq_index=0
1067 in_addr_map=true
1068 latency=30000
1069 latency_var=0
1070 null=false
1071 p_state_clk_gate_bins=20
1072 p_state_clk_gate_max=1000000000000
1073 p_state_clk_gate_min=1000
1074 power_model=Null
1075 range=2147483648:2415919103
1076 port=system.membus.master[5]
1077
1078 [system.realview]
1079 type=RealView
1080 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1081 eventq_index=0
1082 intrctrl=system.intrctrl
1083 system=system
1084
1085 [system.realview.aaci_fake]
1086 type=AmbaFake
1087 amba_id=0
1088 clk_domain=system.clk_domain
1089 default_p_state=UNDEFINED
1090 eventq_index=0
1091 ignore_access=false
1092 p_state_clk_gate_bins=20
1093 p_state_clk_gate_max=1000000000000
1094 p_state_clk_gate_min=1000
1095 pio_addr=470024192
1096 pio_latency=100000
1097 power_model=Null
1098 system=system
1099 pio=system.iobus.master[18]
1100
1101 [system.realview.cf_ctrl]
1102 type=IdeController
1103 BAR0=471465984
1104 BAR0LegacyIO=true
1105 BAR0Size=256
1106 BAR1=471466240
1107 BAR1LegacyIO=true
1108 BAR1Size=4096
1109 BAR2=1
1110 BAR2LegacyIO=false
1111 BAR2Size=8
1112 BAR3=1
1113 BAR3LegacyIO=false
1114 BAR3Size=4
1115 BAR4=1
1116 BAR4LegacyIO=false
1117 BAR4Size=16
1118 BAR5=1
1119 BAR5LegacyIO=false
1120 BAR5Size=0
1121 BIST=0
1122 CacheLineSize=0
1123 CapabilityPtr=0
1124 CardbusCIS=0
1125 ClassCode=1
1126 Command=1
1127 DeviceID=28945
1128 ExpansionROM=0
1129 HeaderType=0
1130 InterruptLine=31
1131 InterruptPin=1
1132 LatencyTimer=0
1133 LegacyIOBase=0
1134 MSICAPBaseOffset=0
1135 MSICAPCapId=0
1136 MSICAPMaskBits=0
1137 MSICAPMsgAddr=0
1138 MSICAPMsgCtrl=0
1139 MSICAPMsgData=0
1140 MSICAPMsgUpperAddr=0
1141 MSICAPNextCapability=0
1142 MSICAPPendingBits=0
1143 MSIXCAPBaseOffset=0
1144 MSIXCAPCapId=0
1145 MSIXCAPNextCapability=0
1146 MSIXMsgCtrl=0
1147 MSIXPbaOffset=0
1148 MSIXTableOffset=0
1149 MaximumLatency=0
1150 MinimumGrant=0
1151 PMCAPBaseOffset=0
1152 PMCAPCapId=0
1153 PMCAPCapabilities=0
1154 PMCAPCtrlStatus=0
1155 PMCAPNextCapability=0
1156 PXCAPBaseOffset=0
1157 PXCAPCapId=0
1158 PXCAPCapabilities=0
1159 PXCAPDevCap2=0
1160 PXCAPDevCapabilities=0
1161 PXCAPDevCtrl=0
1162 PXCAPDevCtrl2=0
1163 PXCAPDevStatus=0
1164 PXCAPLinkCap=0
1165 PXCAPLinkCtrl=0
1166 PXCAPLinkStatus=0
1167 PXCAPNextCapability=0
1168 ProgIF=133
1169 Revision=0
1170 Status=640
1171 SubClassCode=1
1172 SubsystemID=0
1173 SubsystemVendorID=0
1174 VendorID=32902
1175 clk_domain=system.clk_domain
1176 config_latency=20000
1177 ctrl_offset=2
1178 default_p_state=UNDEFINED
1179 disks=
1180 eventq_index=0
1181 host=system.realview.pci_host
1182 io_shift=2
1183 p_state_clk_gate_bins=20
1184 p_state_clk_gate_max=1000000000000
1185 p_state_clk_gate_min=1000
1186 pci_bus=2
1187 pci_dev=0
1188 pci_func=0
1189 pio_latency=30000
1190 power_model=Null
1191 system=system
1192 dma=system.iobus.slave[2]
1193 pio=system.iobus.master[9]
1194
1195 [system.realview.clcd]
1196 type=Pl111
1197 amba_id=1315089
1198 clk_domain=system.clk_domain
1199 default_p_state=UNDEFINED
1200 enable_capture=true
1201 eventq_index=0
1202 gic=system.realview.gic
1203 int_num=46
1204 p_state_clk_gate_bins=20
1205 p_state_clk_gate_max=1000000000000
1206 p_state_clk_gate_min=1000
1207 pio_addr=471793664
1208 pio_latency=10000
1209 pixel_clock=41667
1210 power_model=Null
1211 system=system
1212 vnc=system.vncserver
1213 dma=system.iobus.slave[1]
1214 pio=system.iobus.master[5]
1215
1216 [system.realview.dcc]
1217 type=SubSystem
1218 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1219 eventq_index=0
1220 thermal_domain=Null
1221
1222 [system.realview.dcc.osc_cpu]
1223 type=RealViewOsc
1224 dcc=0
1225 device=0
1226 eventq_index=0
1227 freq=16667
1228 parent=system.realview.realview_io
1229 position=0
1230 site=1
1231 voltage_domain=system.voltage_domain
1232
1233 [system.realview.dcc.osc_ddr]
1234 type=RealViewOsc
1235 dcc=0
1236 device=8
1237 eventq_index=0
1238 freq=25000
1239 parent=system.realview.realview_io
1240 position=0
1241 site=1
1242 voltage_domain=system.voltage_domain
1243
1244 [system.realview.dcc.osc_hsbm]
1245 type=RealViewOsc
1246 dcc=0
1247 device=4
1248 eventq_index=0
1249 freq=25000
1250 parent=system.realview.realview_io
1251 position=0
1252 site=1
1253 voltage_domain=system.voltage_domain
1254
1255 [system.realview.dcc.osc_pxl]
1256 type=RealViewOsc
1257 dcc=0
1258 device=5
1259 eventq_index=0
1260 freq=42105
1261 parent=system.realview.realview_io
1262 position=0
1263 site=1
1264 voltage_domain=system.voltage_domain
1265
1266 [system.realview.dcc.osc_smb]
1267 type=RealViewOsc
1268 dcc=0
1269 device=6
1270 eventq_index=0
1271 freq=20000
1272 parent=system.realview.realview_io
1273 position=0
1274 site=1
1275 voltage_domain=system.voltage_domain
1276
1277 [system.realview.dcc.osc_sys]
1278 type=RealViewOsc
1279 dcc=0
1280 device=7
1281 eventq_index=0
1282 freq=16667
1283 parent=system.realview.realview_io
1284 position=0
1285 site=1
1286 voltage_domain=system.voltage_domain
1287
1288 [system.realview.energy_ctrl]
1289 type=EnergyCtrl
1290 clk_domain=system.clk_domain
1291 default_p_state=UNDEFINED
1292 dvfs_handler=system.dvfs_handler
1293 eventq_index=0
1294 p_state_clk_gate_bins=20
1295 p_state_clk_gate_max=1000000000000
1296 p_state_clk_gate_min=1000
1297 pio_addr=470286336
1298 pio_latency=100000
1299 power_model=Null
1300 system=system
1301 pio=system.iobus.master[22]
1302
1303 [system.realview.ethernet]
1304 type=IGbE
1305 BAR0=0
1306 BAR0LegacyIO=false
1307 BAR0Size=131072
1308 BAR1=0
1309 BAR1LegacyIO=false
1310 BAR1Size=0
1311 BAR2=0
1312 BAR2LegacyIO=false
1313 BAR2Size=0
1314 BAR3=0
1315 BAR3LegacyIO=false
1316 BAR3Size=0
1317 BAR4=0
1318 BAR4LegacyIO=false
1319 BAR4Size=0
1320 BAR5=0
1321 BAR5LegacyIO=false
1322 BAR5Size=0
1323 BIST=0
1324 CacheLineSize=0
1325 CapabilityPtr=0
1326 CardbusCIS=0
1327 ClassCode=2
1328 Command=0
1329 DeviceID=4213
1330 ExpansionROM=0
1331 HeaderType=0
1332 InterruptLine=1
1333 InterruptPin=1
1334 LatencyTimer=0
1335 LegacyIOBase=0
1336 MSICAPBaseOffset=0
1337 MSICAPCapId=0
1338 MSICAPMaskBits=0
1339 MSICAPMsgAddr=0
1340 MSICAPMsgCtrl=0
1341 MSICAPMsgData=0
1342 MSICAPMsgUpperAddr=0
1343 MSICAPNextCapability=0
1344 MSICAPPendingBits=0
1345 MSIXCAPBaseOffset=0
1346 MSIXCAPCapId=0
1347 MSIXCAPNextCapability=0
1348 MSIXMsgCtrl=0
1349 MSIXPbaOffset=0
1350 MSIXTableOffset=0
1351 MaximumLatency=0
1352 MinimumGrant=255
1353 PMCAPBaseOffset=0
1354 PMCAPCapId=0
1355 PMCAPCapabilities=0
1356 PMCAPCtrlStatus=0
1357 PMCAPNextCapability=0
1358 PXCAPBaseOffset=0
1359 PXCAPCapId=0
1360 PXCAPCapabilities=0
1361 PXCAPDevCap2=0
1362 PXCAPDevCapabilities=0
1363 PXCAPDevCtrl=0
1364 PXCAPDevCtrl2=0
1365 PXCAPDevStatus=0
1366 PXCAPLinkCap=0
1367 PXCAPLinkCtrl=0
1368 PXCAPLinkStatus=0
1369 PXCAPNextCapability=0
1370 ProgIF=0
1371 Revision=0
1372 Status=0
1373 SubClassCode=0
1374 SubsystemID=4104
1375 SubsystemVendorID=32902
1376 VendorID=32902
1377 clk_domain=system.clk_domain
1378 config_latency=20000
1379 default_p_state=UNDEFINED
1380 eventq_index=0
1381 fetch_comp_delay=10000
1382 fetch_delay=10000
1383 hardware_address=00:90:00:00:00:01
1384 host=system.realview.pci_host
1385 p_state_clk_gate_bins=20
1386 p_state_clk_gate_max=1000000000000
1387 p_state_clk_gate_min=1000
1388 pci_bus=0
1389 pci_dev=0
1390 pci_func=0
1391 phy_epid=896
1392 phy_pid=680
1393 pio_latency=30000
1394 power_model=Null
1395 rx_desc_cache_size=64
1396 rx_fifo_size=393216
1397 rx_write_delay=0
1398 system=system
1399 tx_desc_cache_size=64
1400 tx_fifo_size=393216
1401 tx_read_delay=0
1402 wb_comp_delay=10000
1403 wb_delay=10000
1404 dma=system.iobus.slave[4]
1405 pio=system.iobus.master[24]
1406
1407 [system.realview.generic_timer]
1408 type=GenericTimer
1409 eventq_index=0
1410 gic=system.realview.gic
1411 int_phys=29
1412 int_virt=27
1413 system=system
1414
1415 [system.realview.gic]
1416 type=Pl390
1417 clk_domain=system.clk_domain
1418 cpu_addr=738205696
1419 cpu_pio_delay=10000
1420 default_p_state=UNDEFINED
1421 dist_addr=738201600
1422 dist_pio_delay=10000
1423 eventq_index=0
1424 gem5_extensions=true
1425 int_latency=10000
1426 it_lines=128
1427 p_state_clk_gate_bins=20
1428 p_state_clk_gate_max=1000000000000
1429 p_state_clk_gate_min=1000
1430 platform=system.realview
1431 power_model=Null
1432 system=system
1433 pio=system.membus.master[2]
1434
1435 [system.realview.hdlcd]
1436 type=HDLcd
1437 amba_id=1314816
1438 clk_domain=system.clk_domain
1439 default_p_state=UNDEFINED
1440 enable_capture=true
1441 eventq_index=0
1442 gic=system.realview.gic
1443 int_num=117
1444 p_state_clk_gate_bins=20
1445 p_state_clk_gate_max=1000000000000
1446 p_state_clk_gate_min=1000
1447 pio_addr=721420288
1448 pio_latency=10000
1449 pixel_buffer_size=2048
1450 pixel_chunk=32
1451 power_model=Null
1452 pxl_clk=system.realview.dcc.osc_pxl
1453 system=system
1454 vnc=system.vncserver
1455 workaround_dma_line_count=true
1456 workaround_swap_rb=true
1457 dma=system.membus.slave[0]
1458 pio=system.iobus.master[6]
1459
1460 [system.realview.ide]
1461 type=IdeController
1462 BAR0=1
1463 BAR0LegacyIO=false
1464 BAR0Size=8
1465 BAR1=1
1466 BAR1LegacyIO=false
1467 BAR1Size=4
1468 BAR2=1
1469 BAR2LegacyIO=false
1470 BAR2Size=8
1471 BAR3=1
1472 BAR3LegacyIO=false
1473 BAR3Size=4
1474 BAR4=1
1475 BAR4LegacyIO=false
1476 BAR4Size=16
1477 BAR5=1
1478 BAR5LegacyIO=false
1479 BAR5Size=0
1480 BIST=0
1481 CacheLineSize=0
1482 CapabilityPtr=0
1483 CardbusCIS=0
1484 ClassCode=1
1485 Command=0
1486 DeviceID=28945
1487 ExpansionROM=0
1488 HeaderType=0
1489 InterruptLine=2
1490 InterruptPin=2
1491 LatencyTimer=0
1492 LegacyIOBase=0
1493 MSICAPBaseOffset=0
1494 MSICAPCapId=0
1495 MSICAPMaskBits=0
1496 MSICAPMsgAddr=0
1497 MSICAPMsgCtrl=0
1498 MSICAPMsgData=0
1499 MSICAPMsgUpperAddr=0
1500 MSICAPNextCapability=0
1501 MSICAPPendingBits=0
1502 MSIXCAPBaseOffset=0
1503 MSIXCAPCapId=0
1504 MSIXCAPNextCapability=0
1505 MSIXMsgCtrl=0
1506 MSIXPbaOffset=0
1507 MSIXTableOffset=0
1508 MaximumLatency=0
1509 MinimumGrant=0
1510 PMCAPBaseOffset=0
1511 PMCAPCapId=0
1512 PMCAPCapabilities=0
1513 PMCAPCtrlStatus=0
1514 PMCAPNextCapability=0
1515 PXCAPBaseOffset=0
1516 PXCAPCapId=0
1517 PXCAPCapabilities=0
1518 PXCAPDevCap2=0
1519 PXCAPDevCapabilities=0
1520 PXCAPDevCtrl=0
1521 PXCAPDevCtrl2=0
1522 PXCAPDevStatus=0
1523 PXCAPLinkCap=0
1524 PXCAPLinkCtrl=0
1525 PXCAPLinkStatus=0
1526 PXCAPNextCapability=0
1527 ProgIF=133
1528 Revision=0
1529 Status=640
1530 SubClassCode=1
1531 SubsystemID=0
1532 SubsystemVendorID=0
1533 VendorID=32902
1534 clk_domain=system.clk_domain
1535 config_latency=20000
1536 ctrl_offset=0
1537 default_p_state=UNDEFINED
1538 disks=system.cf0
1539 eventq_index=0
1540 host=system.realview.pci_host
1541 io_shift=0
1542 p_state_clk_gate_bins=20
1543 p_state_clk_gate_max=1000000000000
1544 p_state_clk_gate_min=1000
1545 pci_bus=0
1546 pci_dev=1
1547 pci_func=0
1548 pio_latency=30000
1549 power_model=Null
1550 system=system
1551 dma=system.iobus.slave[3]
1552 pio=system.iobus.master[23]
1553
1554 [system.realview.kmi0]
1555 type=Pl050
1556 amba_id=1314896
1557 clk_domain=system.clk_domain
1558 default_p_state=UNDEFINED
1559 eventq_index=0
1560 gic=system.realview.gic
1561 int_delay=1000000
1562 int_num=44
1563 is_mouse=false
1564 p_state_clk_gate_bins=20
1565 p_state_clk_gate_max=1000000000000
1566 p_state_clk_gate_min=1000
1567 pio_addr=470155264
1568 pio_latency=100000
1569 power_model=Null
1570 system=system
1571 vnc=system.vncserver
1572 pio=system.iobus.master[7]
1573
1574 [system.realview.kmi1]
1575 type=Pl050
1576 amba_id=1314896
1577 clk_domain=system.clk_domain
1578 default_p_state=UNDEFINED
1579 eventq_index=0
1580 gic=system.realview.gic
1581 int_delay=1000000
1582 int_num=45
1583 is_mouse=true
1584 p_state_clk_gate_bins=20
1585 p_state_clk_gate_max=1000000000000
1586 p_state_clk_gate_min=1000
1587 pio_addr=470220800
1588 pio_latency=100000
1589 power_model=Null
1590 system=system
1591 vnc=system.vncserver
1592 pio=system.iobus.master[8]
1593
1594 [system.realview.l2x0_fake]
1595 type=IsaFake
1596 clk_domain=system.clk_domain
1597 default_p_state=UNDEFINED
1598 eventq_index=0
1599 fake_mem=false
1600 p_state_clk_gate_bins=20
1601 p_state_clk_gate_max=1000000000000
1602 p_state_clk_gate_min=1000
1603 pio_addr=739246080
1604 pio_latency=100000
1605 pio_size=4095
1606 power_model=Null
1607 ret_bad_addr=false
1608 ret_data16=65535
1609 ret_data32=4294967295
1610 ret_data64=18446744073709551615
1611 ret_data8=255
1612 system=system
1613 update_data=false
1614 warn_access=
1615 pio=system.iobus.master[12]
1616
1617 [system.realview.lan_fake]
1618 type=IsaFake
1619 clk_domain=system.clk_domain
1620 default_p_state=UNDEFINED
1621 eventq_index=0
1622 fake_mem=false
1623 p_state_clk_gate_bins=20
1624 p_state_clk_gate_max=1000000000000
1625 p_state_clk_gate_min=1000
1626 pio_addr=436207616
1627 pio_latency=100000
1628 pio_size=65535
1629 power_model=Null
1630 ret_bad_addr=false
1631 ret_data16=65535
1632 ret_data32=4294967295
1633 ret_data64=18446744073709551615
1634 ret_data8=255
1635 system=system
1636 update_data=false
1637 warn_access=
1638 pio=system.iobus.master[19]
1639
1640 [system.realview.local_cpu_timer]
1641 type=CpuLocalTimer
1642 clk_domain=system.clk_domain
1643 default_p_state=UNDEFINED
1644 eventq_index=0
1645 gic=system.realview.gic
1646 int_num_timer=29
1647 int_num_watchdog=30
1648 p_state_clk_gate_bins=20
1649 p_state_clk_gate_max=1000000000000
1650 p_state_clk_gate_min=1000
1651 pio_addr=738721792
1652 pio_latency=100000
1653 power_model=Null
1654 system=system
1655 pio=system.membus.master[4]
1656
1657 [system.realview.mcc]
1658 type=SubSystem
1659 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1660 eventq_index=0
1661 thermal_domain=Null
1662
1663 [system.realview.mcc.osc_clcd]
1664 type=RealViewOsc
1665 dcc=0
1666 device=1
1667 eventq_index=0
1668 freq=42105
1669 parent=system.realview.realview_io
1670 position=0
1671 site=0
1672 voltage_domain=system.voltage_domain
1673
1674 [system.realview.mcc.osc_mcc]
1675 type=RealViewOsc
1676 dcc=0
1677 device=0
1678 eventq_index=0
1679 freq=20000
1680 parent=system.realview.realview_io
1681 position=0
1682 site=0
1683 voltage_domain=system.voltage_domain
1684
1685 [system.realview.mcc.osc_peripheral]
1686 type=RealViewOsc
1687 dcc=0
1688 device=2
1689 eventq_index=0
1690 freq=41667
1691 parent=system.realview.realview_io
1692 position=0
1693 site=0
1694 voltage_domain=system.voltage_domain
1695
1696 [system.realview.mcc.osc_system_bus]
1697 type=RealViewOsc
1698 dcc=0
1699 device=4
1700 eventq_index=0
1701 freq=41667
1702 parent=system.realview.realview_io
1703 position=0
1704 site=0
1705 voltage_domain=system.voltage_domain
1706
1707 [system.realview.mcc.temp_crtl]
1708 type=RealViewTemperatureSensor
1709 dcc=0
1710 device=0
1711 eventq_index=0
1712 parent=system.realview.realview_io
1713 position=0
1714 site=0
1715 system=system
1716
1717 [system.realview.mmc_fake]
1718 type=AmbaFake
1719 amba_id=0
1720 clk_domain=system.clk_domain
1721 default_p_state=UNDEFINED
1722 eventq_index=0
1723 ignore_access=false
1724 p_state_clk_gate_bins=20
1725 p_state_clk_gate_max=1000000000000
1726 p_state_clk_gate_min=1000
1727 pio_addr=470089728
1728 pio_latency=100000
1729 power_model=Null
1730 system=system
1731 pio=system.iobus.master[21]
1732
1733 [system.realview.nvmem]
1734 type=SimpleMemory
1735 bandwidth=73.000000
1736 clk_domain=system.clk_domain
1737 conf_table_reported=true
1738 default_p_state=UNDEFINED
1739 eventq_index=0
1740 in_addr_map=true
1741 latency=30000
1742 latency_var=0
1743 null=false
1744 p_state_clk_gate_bins=20
1745 p_state_clk_gate_max=1000000000000
1746 p_state_clk_gate_min=1000
1747 power_model=Null
1748 range=0:67108863
1749 port=system.membus.master[1]
1750
1751 [system.realview.pci_host]
1752 type=GenericPciHost
1753 clk_domain=system.clk_domain
1754 conf_base=805306368
1755 conf_device_bits=12
1756 conf_size=268435456
1757 default_p_state=UNDEFINED
1758 eventq_index=0
1759 p_state_clk_gate_bins=20
1760 p_state_clk_gate_max=1000000000000
1761 p_state_clk_gate_min=1000
1762 pci_dma_base=0
1763 pci_mem_base=0
1764 pci_pio_base=788529152
1765 platform=system.realview
1766 power_model=Null
1767 system=system
1768 pio=system.iobus.master[2]
1769
1770 [system.realview.realview_io]
1771 type=RealViewCtrl
1772 clk_domain=system.clk_domain
1773 default_p_state=UNDEFINED
1774 eventq_index=0
1775 idreg=35979264
1776 p_state_clk_gate_bins=20
1777 p_state_clk_gate_max=1000000000000
1778 p_state_clk_gate_min=1000
1779 pio_addr=469827584
1780 pio_latency=100000
1781 power_model=Null
1782 proc_id0=335544320
1783 proc_id1=335544320
1784 system=system
1785 pio=system.iobus.master[1]
1786
1787 [system.realview.rtc]
1788 type=PL031
1789 amba_id=3412017
1790 clk_domain=system.clk_domain
1791 default_p_state=UNDEFINED
1792 eventq_index=0
1793 gic=system.realview.gic
1794 int_delay=100000
1795 int_num=36
1796 p_state_clk_gate_bins=20
1797 p_state_clk_gate_max=1000000000000
1798 p_state_clk_gate_min=1000
1799 pio_addr=471269376
1800 pio_latency=100000
1801 power_model=Null
1802 system=system
1803 time=Thu Jan  1 00:00:00 2009
1804 pio=system.iobus.master[10]
1805
1806 [system.realview.sp810_fake]
1807 type=AmbaFake
1808 amba_id=0
1809 clk_domain=system.clk_domain
1810 default_p_state=UNDEFINED
1811 eventq_index=0
1812 ignore_access=true
1813 p_state_clk_gate_bins=20
1814 p_state_clk_gate_max=1000000000000
1815 p_state_clk_gate_min=1000
1816 pio_addr=469893120
1817 pio_latency=100000
1818 power_model=Null
1819 system=system
1820 pio=system.iobus.master[16]
1821
1822 [system.realview.timer0]
1823 type=Sp804
1824 amba_id=1316868
1825 clk_domain=system.clk_domain
1826 clock0=1000000
1827 clock1=1000000
1828 default_p_state=UNDEFINED
1829 eventq_index=0
1830 gic=system.realview.gic
1831 int_num0=34
1832 int_num1=34
1833 p_state_clk_gate_bins=20
1834 p_state_clk_gate_max=1000000000000
1835 p_state_clk_gate_min=1000
1836 pio_addr=470876160
1837 pio_latency=100000
1838 power_model=Null
1839 system=system
1840 pio=system.iobus.master[3]
1841
1842 [system.realview.timer1]
1843 type=Sp804
1844 amba_id=1316868
1845 clk_domain=system.clk_domain
1846 clock0=1000000
1847 clock1=1000000
1848 default_p_state=UNDEFINED
1849 eventq_index=0
1850 gic=system.realview.gic
1851 int_num0=35
1852 int_num1=35
1853 p_state_clk_gate_bins=20
1854 p_state_clk_gate_max=1000000000000
1855 p_state_clk_gate_min=1000
1856 pio_addr=470941696
1857 pio_latency=100000
1858 power_model=Null
1859 system=system
1860 pio=system.iobus.master[4]
1861
1862 [system.realview.uart]
1863 type=Pl011
1864 clk_domain=system.clk_domain
1865 default_p_state=UNDEFINED
1866 end_on_eot=false
1867 eventq_index=0
1868 gic=system.realview.gic
1869 int_delay=100000
1870 int_num=37
1871 p_state_clk_gate_bins=20
1872 p_state_clk_gate_max=1000000000000
1873 p_state_clk_gate_min=1000
1874 pio_addr=470351872
1875 pio_latency=100000
1876 platform=system.realview
1877 power_model=Null
1878 system=system
1879 terminal=system.terminal
1880 pio=system.iobus.master[0]
1881
1882 [system.realview.uart1_fake]
1883 type=AmbaFake
1884 amba_id=0
1885 clk_domain=system.clk_domain
1886 default_p_state=UNDEFINED
1887 eventq_index=0
1888 ignore_access=false
1889 p_state_clk_gate_bins=20
1890 p_state_clk_gate_max=1000000000000
1891 p_state_clk_gate_min=1000
1892 pio_addr=470417408
1893 pio_latency=100000
1894 power_model=Null
1895 system=system
1896 pio=system.iobus.master[13]
1897
1898 [system.realview.uart2_fake]
1899 type=AmbaFake
1900 amba_id=0
1901 clk_domain=system.clk_domain
1902 default_p_state=UNDEFINED
1903 eventq_index=0
1904 ignore_access=false
1905 p_state_clk_gate_bins=20
1906 p_state_clk_gate_max=1000000000000
1907 p_state_clk_gate_min=1000
1908 pio_addr=470482944
1909 pio_latency=100000
1910 power_model=Null
1911 system=system
1912 pio=system.iobus.master[14]
1913
1914 [system.realview.uart3_fake]
1915 type=AmbaFake
1916 amba_id=0
1917 clk_domain=system.clk_domain
1918 default_p_state=UNDEFINED
1919 eventq_index=0
1920 ignore_access=false
1921 p_state_clk_gate_bins=20
1922 p_state_clk_gate_max=1000000000000
1923 p_state_clk_gate_min=1000
1924 pio_addr=470548480
1925 pio_latency=100000
1926 power_model=Null
1927 system=system
1928 pio=system.iobus.master[15]
1929
1930 [system.realview.usb_fake]
1931 type=IsaFake
1932 clk_domain=system.clk_domain
1933 default_p_state=UNDEFINED
1934 eventq_index=0
1935 fake_mem=false
1936 p_state_clk_gate_bins=20
1937 p_state_clk_gate_max=1000000000000
1938 p_state_clk_gate_min=1000
1939 pio_addr=452984832
1940 pio_latency=100000
1941 pio_size=131071
1942 power_model=Null
1943 ret_bad_addr=false
1944 ret_data16=65535
1945 ret_data32=4294967295
1946 ret_data64=18446744073709551615
1947 ret_data8=255
1948 system=system
1949 update_data=false
1950 warn_access=
1951 pio=system.iobus.master[20]
1952
1953 [system.realview.vgic]
1954 type=VGic
1955 clk_domain=system.clk_domain
1956 default_p_state=UNDEFINED
1957 eventq_index=0
1958 gic=system.realview.gic
1959 hv_addr=738213888
1960 p_state_clk_gate_bins=20
1961 p_state_clk_gate_max=1000000000000
1962 p_state_clk_gate_min=1000
1963 pio_delay=10000
1964 platform=system.realview
1965 power_model=Null
1966 ppint=25
1967 system=system
1968 vcpu_addr=738222080
1969 pio=system.membus.master[3]
1970
1971 [system.realview.vram]
1972 type=SimpleMemory
1973 bandwidth=73.000000
1974 clk_domain=system.clk_domain
1975 conf_table_reported=false
1976 default_p_state=UNDEFINED
1977 eventq_index=0
1978 in_addr_map=true
1979 latency=30000
1980 latency_var=0
1981 null=false
1982 p_state_clk_gate_bins=20
1983 p_state_clk_gate_max=1000000000000
1984 p_state_clk_gate_min=1000
1985 power_model=Null
1986 range=402653184:436207615
1987 port=system.iobus.master[11]
1988
1989 [system.realview.watchdog_fake]
1990 type=AmbaFake
1991 amba_id=0
1992 clk_domain=system.clk_domain
1993 default_p_state=UNDEFINED
1994 eventq_index=0
1995 ignore_access=false
1996 p_state_clk_gate_bins=20
1997 p_state_clk_gate_max=1000000000000
1998 p_state_clk_gate_min=1000
1999 pio_addr=470745088
2000 pio_latency=100000
2001 power_model=Null
2002 system=system
2003 pio=system.iobus.master[17]
2004
2005 [system.terminal]
2006 type=Terminal
2007 eventq_index=0
2008 intr_control=system.intrctrl
2009 number=0
2010 output=true
2011 port=3456
2012
2013 [system.toL2Bus]
2014 type=CoherentXBar
2015 children=snoop_filter
2016 clk_domain=system.cpu_clk_domain
2017 default_p_state=UNDEFINED
2018 eventq_index=0
2019 forward_latency=0
2020 frontend_latency=1
2021 p_state_clk_gate_bins=20
2022 p_state_clk_gate_max=1000000000000
2023 p_state_clk_gate_min=1000
2024 point_of_coherency=false
2025 power_model=Null
2026 response_latency=1
2027 snoop_filter=system.toL2Bus.snoop_filter
2028 snoop_response_latency=1
2029 system=system
2030 use_default_range=false
2031 width=32
2032 master=system.l2c.cpu_side
2033 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
2034
2035 [system.toL2Bus.snoop_filter]
2036 type=SnoopFilter
2037 eventq_index=0
2038 lookup_latency=0
2039 max_capacity=8388608
2040 system=system
2041
2042 [system.vncserver]
2043 type=VncServer
2044 eventq_index=0
2045 frame_capture=false
2046 number=0
2047 port=5900
2048
2049 [system.voltage_domain]
2050 type=VoltageDomain
2051 eventq_index=0
2052 voltage=1.000000
2053