tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM64
  38 mem_mode=atomic
  39 mem_ranges=2147483648:2415919103
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=AtomicSimpleCPU
 115 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=Null
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 default_p_state=UNDEFINED
 121 do_checkpoint_insts=true
 122 do_quiesce=true
 123 do_statistics_insts=true
 124 dstage2_mmu=system.cpu.dstage2_mmu
 125 dtb=system.cpu.dtb
 126 eventq_index=0
 127 fastmem=false
 128 function_trace=false
 129 function_trace_start=0
 130 interrupts=system.cpu.interrupts
 131 isa=system.cpu.isa
 132 istage2_mmu=system.cpu.istage2_mmu
 133 itb=system.cpu.itb
 134 max_insts_all_threads=0
 135 max_insts_any_thread=0
 136 max_loads_all_threads=0
 137 max_loads_any_thread=0
 138 numThreads=1
 139 p_state_clk_gate_bins=20
 140 p_state_clk_gate_max=1000000000000
 141 p_state_clk_gate_min=1000
 142 power_model=Null
 143 profile=0
 144 progress_interval=0
 145 simpoint_start_insts=
 146 simulate_data_stalls=false
 147 simulate_inst_stalls=false
 148 socket_id=0
 149 switched_out=false
 150 system=system
 151 tracer=system.cpu.tracer
 152 width=1
 153 workload=
 154 dcache_port=system.cpu.dcache.cpu_side
 155 icache_port=system.cpu.icache.cpu_side
 156
 157 [system.cpu.dcache]
 158 type=Cache
 159 children=tags
 160 addr_ranges=0:18446744073709551615
 161 assoc=4
 162 clk_domain=system.cpu_clk_domain
 163 clusivity=mostly_incl
 164 default_p_state=UNDEFINED
 165 demand_mshr_reserve=1
 166 eventq_index=0
 167 hit_latency=2
 168 is_read_only=false
 169 max_miss_count=0
 170 mshrs=4
 171 p_state_clk_gate_bins=20
 172 p_state_clk_gate_max=1000000000000
 173 p_state_clk_gate_min=1000
 174 power_model=Null
 175 prefetch_on_access=false
 176 prefetcher=Null
 177 response_latency=2
 178 sequential_access=false
 179 size=32768
 180 system=system
 181 tags=system.cpu.dcache.tags
 182 tgts_per_mshr=20
 183 write_buffers=8
 184 writeback_clean=false
 185 cpu_side=system.cpu.dcache_port
 186 mem_side=system.cpu.toL2Bus.slave[1]
 187
 188 [system.cpu.dcache.tags]
 189 type=LRU
 190 assoc=4
 191 block_size=64
 192 clk_domain=system.cpu_clk_domain
 193 default_p_state=UNDEFINED
 194 eventq_index=0
 195 hit_latency=2
 196 p_state_clk_gate_bins=20
 197 p_state_clk_gate_max=1000000000000
 198 p_state_clk_gate_min=1000
 199 power_model=Null
 200 sequential_access=false
 201 size=32768
 202
 203 [system.cpu.dstage2_mmu]
 204 type=ArmStage2MMU
 205 children=stage2_tlb
 206 eventq_index=0
 207 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 208 sys=system
 209 tlb=system.cpu.dtb
 210
 211 [system.cpu.dstage2_mmu.stage2_tlb]
 212 type=ArmTLB
 213 children=walker
 214 eventq_index=0
 215 is_stage2=true
 216 size=32
 217 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 218
 219 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 220 type=ArmTableWalker
 221 clk_domain=system.cpu_clk_domain
 222 default_p_state=UNDEFINED
 223 eventq_index=0
 224 is_stage2=true
 225 num_squash_per_cycle=2
 226 p_state_clk_gate_bins=20
 227 p_state_clk_gate_max=1000000000000
 228 p_state_clk_gate_min=1000
 229 power_model=Null
 230 sys=system
 231
 232 [system.cpu.dtb]
 233 type=ArmTLB
 234 children=walker
 235 eventq_index=0
 236 is_stage2=false
 237 size=64
 238 walker=system.cpu.dtb.walker
 239
 240 [system.cpu.dtb.walker]
 241 type=ArmTableWalker
 242 clk_domain=system.cpu_clk_domain
 243 default_p_state=UNDEFINED
 244 eventq_index=0
 245 is_stage2=false
 246 num_squash_per_cycle=2
 247 p_state_clk_gate_bins=20
 248 p_state_clk_gate_max=1000000000000
 249 p_state_clk_gate_min=1000
 250 power_model=Null
 251 sys=system
 252 port=system.cpu.toL2Bus.slave[3]
 253
 254 [system.cpu.icache]
 255 type=Cache
 256 children=tags
 257 addr_ranges=0:18446744073709551615
 258 assoc=1
 259 clk_domain=system.cpu_clk_domain
 260 clusivity=mostly_incl
 261 default_p_state=UNDEFINED
 262 demand_mshr_reserve=1
 263 eventq_index=0
 264 hit_latency=2
 265 is_read_only=true
 266 max_miss_count=0
 267 mshrs=4
 268 p_state_clk_gate_bins=20
 269 p_state_clk_gate_max=1000000000000
 270 p_state_clk_gate_min=1000
 271 power_model=Null
 272 prefetch_on_access=false
 273 prefetcher=Null
 274 response_latency=2
 275 sequential_access=false
 276 size=32768
 277 system=system
 278 tags=system.cpu.icache.tags
 279 tgts_per_mshr=20
 280 write_buffers=8
 281 writeback_clean=true
 282 cpu_side=system.cpu.icache_port
 283 mem_side=system.cpu.toL2Bus.slave[0]
 284
 285 [system.cpu.icache.tags]
 286 type=LRU
 287 assoc=1
 288 block_size=64
 289 clk_domain=system.cpu_clk_domain
 290 default_p_state=UNDEFINED
 291 eventq_index=0
 292 hit_latency=2
 293 p_state_clk_gate_bins=20
 294 p_state_clk_gate_max=1000000000000
 295 p_state_clk_gate_min=1000
 296 power_model=Null
 297 sequential_access=false
 298 size=32768
 299
 300 [system.cpu.interrupts]
 301 type=ArmInterrupts
 302 eventq_index=0
 303
 304 [system.cpu.isa]
 305 type=ArmISA
 306 decoderFlavour=Generic
 307 eventq_index=0
 308 fpsid=1090793632
 309 id_aa64afr0_el1=0
 310 id_aa64afr1_el1=0
 311 id_aa64dfr0_el1=1052678
 312 id_aa64dfr1_el1=0
 313 id_aa64isar0_el1=0
 314 id_aa64isar1_el1=0
 315 id_aa64mmfr0_el1=15728642
 316 id_aa64mmfr1_el1=0
 317 id_aa64pfr0_el1=17
 318 id_aa64pfr1_el1=0
 319 id_isar0=34607377
 320 id_isar1=34677009
 321 id_isar2=555950401
 322 id_isar3=17899825
 323 id_isar4=268501314
 324 id_isar5=0
 325 id_mmfr0=270536963
 326 id_mmfr1=0
 327 id_mmfr2=19070976
 328 id_mmfr3=34611729
 329 id_pfr0=49
 330 id_pfr1=4113
 331 midr=1091551472
 332 pmu=Null
 333 system=system
 334
 335 [system.cpu.istage2_mmu]
 336 type=ArmStage2MMU
 337 children=stage2_tlb
 338 eventq_index=0
 339 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 340 sys=system
 341 tlb=system.cpu.itb
 342
 343 [system.cpu.istage2_mmu.stage2_tlb]
 344 type=ArmTLB
 345 children=walker
 346 eventq_index=0
 347 is_stage2=true
 348 size=32
 349 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 350
 351 [system.cpu.istage2_mmu.stage2_tlb.walker]
 352 type=ArmTableWalker
 353 clk_domain=system.cpu_clk_domain
 354 default_p_state=UNDEFINED
 355 eventq_index=0
 356 is_stage2=true
 357 num_squash_per_cycle=2
 358 p_state_clk_gate_bins=20
 359 p_state_clk_gate_max=1000000000000
 360 p_state_clk_gate_min=1000
 361 power_model=Null
 362 sys=system
 363
 364 [system.cpu.itb]
 365 type=ArmTLB
 366 children=walker
 367 eventq_index=0
 368 is_stage2=false
 369 size=64
 370 walker=system.cpu.itb.walker
 371
 372 [system.cpu.itb.walker]
 373 type=ArmTableWalker
 374 clk_domain=system.cpu_clk_domain
 375 default_p_state=UNDEFINED
 376 eventq_index=0
 377 is_stage2=false
 378 num_squash_per_cycle=2
 379 p_state_clk_gate_bins=20
 380 p_state_clk_gate_max=1000000000000
 381 p_state_clk_gate_min=1000
 382 power_model=Null
 383 sys=system
 384 port=system.cpu.toL2Bus.slave[2]
 385
 386 [system.cpu.l2cache]
 387 type=Cache
 388 children=tags
 389 addr_ranges=0:18446744073709551615
 390 assoc=8
 391 clk_domain=system.cpu_clk_domain
 392 clusivity=mostly_incl
 393 default_p_state=UNDEFINED
 394 demand_mshr_reserve=1
 395 eventq_index=0
 396 hit_latency=20
 397 is_read_only=false
 398 max_miss_count=0
 399 mshrs=20
 400 p_state_clk_gate_bins=20
 401 p_state_clk_gate_max=1000000000000
 402 p_state_clk_gate_min=1000
 403 power_model=Null
 404 prefetch_on_access=false
 405 prefetcher=Null
 406 response_latency=20
 407 sequential_access=false
 408 size=4194304
 409 system=system
 410 tags=system.cpu.l2cache.tags
 411 tgts_per_mshr=12
 412 write_buffers=8
 413 writeback_clean=false
 414 cpu_side=system.cpu.toL2Bus.master[0]
 415 mem_side=system.membus.slave[2]
 416
 417 [system.cpu.l2cache.tags]
 418 type=LRU
 419 assoc=8
 420 block_size=64
 421 clk_domain=system.cpu_clk_domain
 422 default_p_state=UNDEFINED
 423 eventq_index=0
 424 hit_latency=20
 425 p_state_clk_gate_bins=20
 426 p_state_clk_gate_max=1000000000000
 427 p_state_clk_gate_min=1000
 428 power_model=Null
 429 sequential_access=false
 430 size=4194304
 431
 432 [system.cpu.toL2Bus]
 433 type=CoherentXBar
 434 children=snoop_filter
 435 clk_domain=system.cpu_clk_domain
 436 default_p_state=UNDEFINED
 437 eventq_index=0
 438 forward_latency=0
 439 frontend_latency=1
 440 p_state_clk_gate_bins=20
 441 p_state_clk_gate_max=1000000000000
 442 p_state_clk_gate_min=1000
 443 point_of_coherency=false
 444 power_model=Null
 445 response_latency=1
 446 snoop_filter=system.cpu.toL2Bus.snoop_filter
 447 snoop_response_latency=1
 448 system=system
 449 use_default_range=false
 450 width=32
 451 master=system.cpu.l2cache.cpu_side
 452 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 453
 454 [system.cpu.toL2Bus.snoop_filter]
 455 type=SnoopFilter
 456 eventq_index=0
 457 lookup_latency=0
 458 max_capacity=8388608
 459 system=system
 460
 461 [system.cpu.tracer]
 462 type=ExeTracer
 463 eventq_index=0
 464
 465 [system.cpu_clk_domain]
 466 type=SrcClockDomain
 467 clock=500
 468 domain_id=-1
 469 eventq_index=0
 470 init_perf_level=0
 471 voltage_domain=system.voltage_domain
 472
 473 [system.dvfs_handler]
 474 type=DVFSHandler
 475 domains=
 476 enable=false
 477 eventq_index=0
 478 sys_clk_domain=system.clk_domain
 479 transition_latency=100000000
 480
 481 [system.intrctrl]
 482 type=IntrControl
 483 eventq_index=0
 484 sys=system
 485
 486 [system.iobus]
 487 type=NoncoherentXBar
 488 clk_domain=system.clk_domain
 489 default_p_state=UNDEFINED
 490 eventq_index=0
 491 forward_latency=1
 492 frontend_latency=2
 493 p_state_clk_gate_bins=20
 494 p_state_clk_gate_max=1000000000000
 495 p_state_clk_gate_min=1000
 496 power_model=Null
 497 response_latency=2
 498 use_default_range=false
 499 width=16
 500 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 501 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 502
 503 [system.iocache]
 504 type=Cache
 505 children=tags
 506 addr_ranges=2147483648:2415919103
 507 assoc=8
 508 clk_domain=system.clk_domain
 509 clusivity=mostly_incl
 510 default_p_state=UNDEFINED
 511 demand_mshr_reserve=1
 512 eventq_index=0
 513 hit_latency=50
 514 is_read_only=false
 515 max_miss_count=0
 516 mshrs=20
 517 p_state_clk_gate_bins=20
 518 p_state_clk_gate_max=1000000000000
 519 p_state_clk_gate_min=1000
 520 power_model=Null
 521 prefetch_on_access=false
 522 prefetcher=Null
 523 response_latency=50
 524 sequential_access=false
 525 size=1024
 526 system=system
 527 tags=system.iocache.tags
 528 tgts_per_mshr=12
 529 write_buffers=8
 530 writeback_clean=false
 531 cpu_side=system.iobus.master[25]
 532 mem_side=system.membus.slave[3]
 533
 534 [system.iocache.tags]
 535 type=LRU
 536 assoc=8
 537 block_size=64
 538 clk_domain=system.clk_domain
 539 default_p_state=UNDEFINED
 540 eventq_index=0
 541 hit_latency=50
 542 p_state_clk_gate_bins=20
 543 p_state_clk_gate_max=1000000000000
 544 p_state_clk_gate_min=1000
 545 power_model=Null
 546 sequential_access=false
 547 size=1024
 548
 549 [system.membus]
 550 type=CoherentXBar
 551 children=badaddr_responder
 552 clk_domain=system.clk_domain
 553 default_p_state=UNDEFINED
 554 eventq_index=0
 555 forward_latency=4
 556 frontend_latency=3
 557 p_state_clk_gate_bins=20
 558 p_state_clk_gate_max=1000000000000
 559 p_state_clk_gate_min=1000
 560 point_of_coherency=true
 561 power_model=Null
 562 response_latency=2
 563 snoop_filter=Null
 564 snoop_response_latency=4
 565 system=system
 566 use_default_range=false
 567 width=16
 568 default=system.membus.badaddr_responder.pio
 569 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 570 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 571
 572 [system.membus.badaddr_responder]
 573 type=IsaFake
 574 clk_domain=system.clk_domain
 575 default_p_state=UNDEFINED
 576 eventq_index=0
 577 fake_mem=false
 578 p_state_clk_gate_bins=20
 579 p_state_clk_gate_max=1000000000000
 580 p_state_clk_gate_min=1000
 581 pio_addr=0
 582 pio_latency=100000
 583 pio_size=8
 584 power_model=Null
 585 ret_bad_addr=true
 586 ret_data16=65535
 587 ret_data32=4294967295
 588 ret_data64=18446744073709551615
 589 ret_data8=255
 590 system=system
 591 update_data=false
 592 warn_access=warn
 593 pio=system.membus.default
 594
 595 [system.physmem]
 596 type=SimpleMemory
 597 bandwidth=73.000000
 598 clk_domain=system.clk_domain
 599 conf_table_reported=true
 600 default_p_state=UNDEFINED
 601 eventq_index=0
 602 in_addr_map=true
 603 latency=30000
 604 latency_var=0
 605 null=false
 606 p_state_clk_gate_bins=20
 607 p_state_clk_gate_max=1000000000000
 608 p_state_clk_gate_min=1000
 609 power_model=Null
 610 range=2147483648:2415919103
 611 port=system.membus.master[5]
 612
 613 [system.realview]
 614 type=RealView
 615 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 616 eventq_index=0
 617 intrctrl=system.intrctrl
 618 system=system
 619
 620 [system.realview.aaci_fake]
 621 type=AmbaFake
 622 amba_id=0
 623 clk_domain=system.clk_domain
 624 default_p_state=UNDEFINED
 625 eventq_index=0
 626 ignore_access=false
 627 p_state_clk_gate_bins=20
 628 p_state_clk_gate_max=1000000000000
 629 p_state_clk_gate_min=1000
 630 pio_addr=470024192
 631 pio_latency=100000
 632 power_model=Null
 633 system=system
 634 pio=system.iobus.master[18]
 635
 636 [system.realview.cf_ctrl]
 637 type=IdeController
 638 BAR0=471465984
 639 BAR0LegacyIO=true
 640 BAR0Size=256
 641 BAR1=471466240
 642 BAR1LegacyIO=true
 643 BAR1Size=4096
 644 BAR2=1
 645 BAR2LegacyIO=false
 646 BAR2Size=8
 647 BAR3=1
 648 BAR3LegacyIO=false
 649 BAR3Size=4
 650 BAR4=1
 651 BAR4LegacyIO=false
 652 BAR4Size=16
 653 BAR5=1
 654 BAR5LegacyIO=false
 655 BAR5Size=0
 656 BIST=0
 657 CacheLineSize=0
 658 CapabilityPtr=0
 659 CardbusCIS=0
 660 ClassCode=1
 661 Command=1
 662 DeviceID=28945
 663 ExpansionROM=0
 664 HeaderType=0
 665 InterruptLine=31
 666 InterruptPin=1
 667 LatencyTimer=0
 668 LegacyIOBase=0
 669 MSICAPBaseOffset=0
 670 MSICAPCapId=0
 671 MSICAPMaskBits=0
 672 MSICAPMsgAddr=0
 673 MSICAPMsgCtrl=0
 674 MSICAPMsgData=0
 675 MSICAPMsgUpperAddr=0
 676 MSICAPNextCapability=0
 677 MSICAPPendingBits=0
 678 MSIXCAPBaseOffset=0
 679 MSIXCAPCapId=0
 680 MSIXCAPNextCapability=0
 681 MSIXMsgCtrl=0
 682 MSIXPbaOffset=0
 683 MSIXTableOffset=0
 684 MaximumLatency=0
 685 MinimumGrant=0
 686 PMCAPBaseOffset=0
 687 PMCAPCapId=0
 688 PMCAPCapabilities=0
 689 PMCAPCtrlStatus=0
 690 PMCAPNextCapability=0
 691 PXCAPBaseOffset=0
 692 PXCAPCapId=0
 693 PXCAPCapabilities=0
 694 PXCAPDevCap2=0
 695 PXCAPDevCapabilities=0
 696 PXCAPDevCtrl=0
 697 PXCAPDevCtrl2=0
 698 PXCAPDevStatus=0
 699 PXCAPLinkCap=0
 700 PXCAPLinkCtrl=0
 701 PXCAPLinkStatus=0
 702 PXCAPNextCapability=0
 703 ProgIF=133
 704 Revision=0
 705 Status=640
 706 SubClassCode=1
 707 SubsystemID=0
 708 SubsystemVendorID=0
 709 VendorID=32902
 710 clk_domain=system.clk_domain
 711 config_latency=20000
 712 ctrl_offset=2
 713 default_p_state=UNDEFINED
 714 disks=
 715 eventq_index=0
 716 host=system.realview.pci_host
 717 io_shift=2
 718 p_state_clk_gate_bins=20
 719 p_state_clk_gate_max=1000000000000
 720 p_state_clk_gate_min=1000
 721 pci_bus=2
 722 pci_dev=0
 723 pci_func=0
 724 pio_latency=30000
 725 power_model=Null
 726 system=system
 727 dma=system.iobus.slave[2]
 728 pio=system.iobus.master[9]
 729
 730 [system.realview.clcd]
 731 type=Pl111
 732 amba_id=1315089
 733 clk_domain=system.clk_domain
 734 default_p_state=UNDEFINED
 735 enable_capture=true
 736 eventq_index=0
 737 gic=system.realview.gic
 738 int_num=46
 739 p_state_clk_gate_bins=20
 740 p_state_clk_gate_max=1000000000000
 741 p_state_clk_gate_min=1000
 742 pio_addr=471793664
 743 pio_latency=10000
 744 pixel_clock=41667
 745 power_model=Null
 746 system=system
 747 vnc=system.vncserver
 748 dma=system.iobus.slave[1]
 749 pio=system.iobus.master[5]
 750
 751 [system.realview.dcc]
 752 type=SubSystem
 753 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 754 eventq_index=0
 755 thermal_domain=Null
 756
 757 [system.realview.dcc.osc_cpu]
 758 type=RealViewOsc
 759 dcc=0
 760 device=0
 761 eventq_index=0
 762 freq=16667
 763 parent=system.realview.realview_io
 764 position=0
 765 site=1
 766 voltage_domain=system.voltage_domain
 767
 768 [system.realview.dcc.osc_ddr]
 769 type=RealViewOsc
 770 dcc=0
 771 device=8
 772 eventq_index=0
 773 freq=25000
 774 parent=system.realview.realview_io
 775 position=0
 776 site=1
 777 voltage_domain=system.voltage_domain
 778
 779 [system.realview.dcc.osc_hsbm]
 780 type=RealViewOsc
 781 dcc=0
 782 device=4
 783 eventq_index=0
 784 freq=25000
 785 parent=system.realview.realview_io
 786 position=0
 787 site=1
 788 voltage_domain=system.voltage_domain
 789
 790 [system.realview.dcc.osc_pxl]
 791 type=RealViewOsc
 792 dcc=0
 793 device=5
 794 eventq_index=0
 795 freq=42105
 796 parent=system.realview.realview_io
 797 position=0
 798 site=1
 799 voltage_domain=system.voltage_domain
 800
 801 [system.realview.dcc.osc_smb]
 802 type=RealViewOsc
 803 dcc=0
 804 device=6
 805 eventq_index=0
 806 freq=20000
 807 parent=system.realview.realview_io
 808 position=0
 809 site=1
 810 voltage_domain=system.voltage_domain
 811
 812 [system.realview.dcc.osc_sys]
 813 type=RealViewOsc
 814 dcc=0
 815 device=7
 816 eventq_index=0
 817 freq=16667
 818 parent=system.realview.realview_io
 819 position=0
 820 site=1
 821 voltage_domain=system.voltage_domain
 822
 823 [system.realview.energy_ctrl]
 824 type=EnergyCtrl
 825 clk_domain=system.clk_domain
 826 default_p_state=UNDEFINED
 827 dvfs_handler=system.dvfs_handler
 828 eventq_index=0
 829 p_state_clk_gate_bins=20
 830 p_state_clk_gate_max=1000000000000
 831 p_state_clk_gate_min=1000
 832 pio_addr=470286336
 833 pio_latency=100000
 834 power_model=Null
 835 system=system
 836 pio=system.iobus.master[22]
 837
 838 [system.realview.ethernet]
 839 type=IGbE
 840 BAR0=0
 841 BAR0LegacyIO=false
 842 BAR0Size=131072
 843 BAR1=0
 844 BAR1LegacyIO=false
 845 BAR1Size=0
 846 BAR2=0
 847 BAR2LegacyIO=false
 848 BAR2Size=0
 849 BAR3=0
 850 BAR3LegacyIO=false
 851 BAR3Size=0
 852 BAR4=0
 853 BAR4LegacyIO=false
 854 BAR4Size=0
 855 BAR5=0
 856 BAR5LegacyIO=false
 857 BAR5Size=0
 858 BIST=0
 859 CacheLineSize=0
 860 CapabilityPtr=0
 861 CardbusCIS=0
 862 ClassCode=2
 863 Command=0
 864 DeviceID=4213
 865 ExpansionROM=0
 866 HeaderType=0
 867 InterruptLine=1
 868 InterruptPin=1
 869 LatencyTimer=0
 870 LegacyIOBase=0
 871 MSICAPBaseOffset=0
 872 MSICAPCapId=0
 873 MSICAPMaskBits=0
 874 MSICAPMsgAddr=0
 875 MSICAPMsgCtrl=0
 876 MSICAPMsgData=0
 877 MSICAPMsgUpperAddr=0
 878 MSICAPNextCapability=0
 879 MSICAPPendingBits=0
 880 MSIXCAPBaseOffset=0
 881 MSIXCAPCapId=0
 882 MSIXCAPNextCapability=0
 883 MSIXMsgCtrl=0
 884 MSIXPbaOffset=0
 885 MSIXTableOffset=0
 886 MaximumLatency=0
 887 MinimumGrant=255
 888 PMCAPBaseOffset=0
 889 PMCAPCapId=0
 890 PMCAPCapabilities=0
 891 PMCAPCtrlStatus=0
 892 PMCAPNextCapability=0
 893 PXCAPBaseOffset=0
 894 PXCAPCapId=0
 895 PXCAPCapabilities=0
 896 PXCAPDevCap2=0
 897 PXCAPDevCapabilities=0
 898 PXCAPDevCtrl=0
 899 PXCAPDevCtrl2=0
 900 PXCAPDevStatus=0
 901 PXCAPLinkCap=0
 902 PXCAPLinkCtrl=0
 903 PXCAPLinkStatus=0
 904 PXCAPNextCapability=0
 905 ProgIF=0
 906 Revision=0
 907 Status=0
 908 SubClassCode=0
 909 SubsystemID=4104
 910 SubsystemVendorID=32902
 911 VendorID=32902
 912 clk_domain=system.clk_domain
 913 config_latency=20000
 914 default_p_state=UNDEFINED
 915 eventq_index=0
 916 fetch_comp_delay=10000
 917 fetch_delay=10000
 918 hardware_address=00:90:00:00:00:01
 919 host=system.realview.pci_host
 920 p_state_clk_gate_bins=20
 921 p_state_clk_gate_max=1000000000000
 922 p_state_clk_gate_min=1000
 923 pci_bus=0
 924 pci_dev=0
 925 pci_func=0
 926 phy_epid=896
 927 phy_pid=680
 928 pio_latency=30000
 929 power_model=Null
 930 rx_desc_cache_size=64
 931 rx_fifo_size=393216
 932 rx_write_delay=0
 933 system=system
 934 tx_desc_cache_size=64
 935 tx_fifo_size=393216
 936 tx_read_delay=0
 937 wb_comp_delay=10000
 938 wb_delay=10000
 939 dma=system.iobus.slave[4]
 940 pio=system.iobus.master[24]
 941
 942 [system.realview.generic_timer]
 943 type=GenericTimer
 944 eventq_index=0
 945 gic=system.realview.gic
 946 int_phys=29
 947 int_virt=27
 948 system=system
 949
 950 [system.realview.gic]
 951 type=Pl390
 952 clk_domain=system.clk_domain
 953 cpu_addr=738205696
 954 cpu_pio_delay=10000
 955 default_p_state=UNDEFINED
 956 dist_addr=738201600
 957 dist_pio_delay=10000
 958 eventq_index=0
 959 gem5_extensions=true
 960 int_latency=10000
 961 it_lines=128
 962 p_state_clk_gate_bins=20
 963 p_state_clk_gate_max=1000000000000
 964 p_state_clk_gate_min=1000
 965 platform=system.realview
 966 power_model=Null
 967 system=system
 968 pio=system.membus.master[2]
 969
 970 [system.realview.hdlcd]
 971 type=HDLcd
 972 amba_id=1314816
 973 clk_domain=system.clk_domain
 974 default_p_state=UNDEFINED
 975 enable_capture=true
 976 eventq_index=0
 977 gic=system.realview.gic
 978 int_num=117
 979 p_state_clk_gate_bins=20
 980 p_state_clk_gate_max=1000000000000
 981 p_state_clk_gate_min=1000
 982 pio_addr=721420288
 983 pio_latency=10000
 984 pixel_buffer_size=2048
 985 pixel_chunk=32
 986 power_model=Null
 987 pxl_clk=system.realview.dcc.osc_pxl
 988 system=system
 989 vnc=system.vncserver
 990 workaround_dma_line_count=true
 991 workaround_swap_rb=true
 992 dma=system.membus.slave[0]
 993 pio=system.iobus.master[6]
 994
 995 [system.realview.ide]
 996 type=IdeController
 997 BAR0=1
 998 BAR0LegacyIO=false
 999 BAR0Size=8
1000 BAR1=1
1001 BAR1LegacyIO=false
1002 BAR1Size=4
1003 BAR2=1
1004 BAR2LegacyIO=false
1005 BAR2Size=8
1006 BAR3=1
1007 BAR3LegacyIO=false
1008 BAR3Size=4
1009 BAR4=1
1010 BAR4LegacyIO=false
1011 BAR4Size=16
1012 BAR5=1
1013 BAR5LegacyIO=false
1014 BAR5Size=0
1015 BIST=0
1016 CacheLineSize=0
1017 CapabilityPtr=0
1018 CardbusCIS=0
1019 ClassCode=1
1020 Command=0
1021 DeviceID=28945
1022 ExpansionROM=0
1023 HeaderType=0
1024 InterruptLine=2
1025 InterruptPin=2
1026 LatencyTimer=0
1027 LegacyIOBase=0
1028 MSICAPBaseOffset=0
1029 MSICAPCapId=0
1030 MSICAPMaskBits=0
1031 MSICAPMsgAddr=0
1032 MSICAPMsgCtrl=0
1033 MSICAPMsgData=0
1034 MSICAPMsgUpperAddr=0
1035 MSICAPNextCapability=0
1036 MSICAPPendingBits=0
1037 MSIXCAPBaseOffset=0
1038 MSIXCAPCapId=0
1039 MSIXCAPNextCapability=0
1040 MSIXMsgCtrl=0
1041 MSIXPbaOffset=0
1042 MSIXTableOffset=0
1043 MaximumLatency=0
1044 MinimumGrant=0
1045 PMCAPBaseOffset=0
1046 PMCAPCapId=0
1047 PMCAPCapabilities=0
1048 PMCAPCtrlStatus=0
1049 PMCAPNextCapability=0
1050 PXCAPBaseOffset=0
1051 PXCAPCapId=0
1052 PXCAPCapabilities=0
1053 PXCAPDevCap2=0
1054 PXCAPDevCapabilities=0
1055 PXCAPDevCtrl=0
1056 PXCAPDevCtrl2=0
1057 PXCAPDevStatus=0
1058 PXCAPLinkCap=0
1059 PXCAPLinkCtrl=0
1060 PXCAPLinkStatus=0
1061 PXCAPNextCapability=0
1062 ProgIF=133
1063 Revision=0
1064 Status=640
1065 SubClassCode=1
1066 SubsystemID=0
1067 SubsystemVendorID=0
1068 VendorID=32902
1069 clk_domain=system.clk_domain
1070 config_latency=20000
1071 ctrl_offset=0
1072 default_p_state=UNDEFINED
1073 disks=system.cf0
1074 eventq_index=0
1075 host=system.realview.pci_host
1076 io_shift=0
1077 p_state_clk_gate_bins=20
1078 p_state_clk_gate_max=1000000000000
1079 p_state_clk_gate_min=1000
1080 pci_bus=0
1081 pci_dev=1
1082 pci_func=0
1083 pio_latency=30000
1084 power_model=Null
1085 system=system
1086 dma=system.iobus.slave[3]
1087 pio=system.iobus.master[23]
1088
1089 [system.realview.kmi0]
1090 type=Pl050
1091 amba_id=1314896
1092 clk_domain=system.clk_domain
1093 default_p_state=UNDEFINED
1094 eventq_index=0
1095 gic=system.realview.gic
1096 int_delay=1000000
1097 int_num=44
1098 is_mouse=false
1099 p_state_clk_gate_bins=20
1100 p_state_clk_gate_max=1000000000000
1101 p_state_clk_gate_min=1000
1102 pio_addr=470155264
1103 pio_latency=100000
1104 power_model=Null
1105 system=system
1106 vnc=system.vncserver
1107 pio=system.iobus.master[7]
1108
1109 [system.realview.kmi1]
1110 type=Pl050
1111 amba_id=1314896
1112 clk_domain=system.clk_domain
1113 default_p_state=UNDEFINED
1114 eventq_index=0
1115 gic=system.realview.gic
1116 int_delay=1000000
1117 int_num=45
1118 is_mouse=true
1119 p_state_clk_gate_bins=20
1120 p_state_clk_gate_max=1000000000000
1121 p_state_clk_gate_min=1000
1122 pio_addr=470220800
1123 pio_latency=100000
1124 power_model=Null
1125 system=system
1126 vnc=system.vncserver
1127 pio=system.iobus.master[8]
1128
1129 [system.realview.l2x0_fake]
1130 type=IsaFake
1131 clk_domain=system.clk_domain
1132 default_p_state=UNDEFINED
1133 eventq_index=0
1134 fake_mem=false
1135 p_state_clk_gate_bins=20
1136 p_state_clk_gate_max=1000000000000
1137 p_state_clk_gate_min=1000
1138 pio_addr=739246080
1139 pio_latency=100000
1140 pio_size=4095
1141 power_model=Null
1142 ret_bad_addr=false
1143 ret_data16=65535
1144 ret_data32=4294967295
1145 ret_data64=18446744073709551615
1146 ret_data8=255
1147 system=system
1148 update_data=false
1149 warn_access=
1150 pio=system.iobus.master[12]
1151
1152 [system.realview.lan_fake]
1153 type=IsaFake
1154 clk_domain=system.clk_domain
1155 default_p_state=UNDEFINED
1156 eventq_index=0
1157 fake_mem=false
1158 p_state_clk_gate_bins=20
1159 p_state_clk_gate_max=1000000000000
1160 p_state_clk_gate_min=1000
1161 pio_addr=436207616
1162 pio_latency=100000
1163 pio_size=65535
1164 power_model=Null
1165 ret_bad_addr=false
1166 ret_data16=65535
1167 ret_data32=4294967295
1168 ret_data64=18446744073709551615
1169 ret_data8=255
1170 system=system
1171 update_data=false
1172 warn_access=
1173 pio=system.iobus.master[19]
1174
1175 [system.realview.local_cpu_timer]
1176 type=CpuLocalTimer
1177 clk_domain=system.clk_domain
1178 default_p_state=UNDEFINED
1179 eventq_index=0
1180 gic=system.realview.gic
1181 int_num_timer=29
1182 int_num_watchdog=30
1183 p_state_clk_gate_bins=20
1184 p_state_clk_gate_max=1000000000000
1185 p_state_clk_gate_min=1000
1186 pio_addr=738721792
1187 pio_latency=100000
1188 power_model=Null
1189 system=system
1190 pio=system.membus.master[4]
1191
1192 [system.realview.mcc]
1193 type=SubSystem
1194 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1195 eventq_index=0
1196 thermal_domain=Null
1197
1198 [system.realview.mcc.osc_clcd]
1199 type=RealViewOsc
1200 dcc=0
1201 device=1
1202 eventq_index=0
1203 freq=42105
1204 parent=system.realview.realview_io
1205 position=0
1206 site=0
1207 voltage_domain=system.voltage_domain
1208
1209 [system.realview.mcc.osc_mcc]
1210 type=RealViewOsc
1211 dcc=0
1212 device=0
1213 eventq_index=0
1214 freq=20000
1215 parent=system.realview.realview_io
1216 position=0
1217 site=0
1218 voltage_domain=system.voltage_domain
1219
1220 [system.realview.mcc.osc_peripheral]
1221 type=RealViewOsc
1222 dcc=0
1223 device=2
1224 eventq_index=0
1225 freq=41667
1226 parent=system.realview.realview_io
1227 position=0
1228 site=0
1229 voltage_domain=system.voltage_domain
1230
1231 [system.realview.mcc.osc_system_bus]
1232 type=RealViewOsc
1233 dcc=0
1234 device=4
1235 eventq_index=0
1236 freq=41667
1237 parent=system.realview.realview_io
1238 position=0
1239 site=0
1240 voltage_domain=system.voltage_domain
1241
1242 [system.realview.mcc.temp_crtl]
1243 type=RealViewTemperatureSensor
1244 dcc=0
1245 device=0
1246 eventq_index=0
1247 parent=system.realview.realview_io
1248 position=0
1249 site=0
1250 system=system
1251
1252 [system.realview.mmc_fake]
1253 type=AmbaFake
1254 amba_id=0
1255 clk_domain=system.clk_domain
1256 default_p_state=UNDEFINED
1257 eventq_index=0
1258 ignore_access=false
1259 p_state_clk_gate_bins=20
1260 p_state_clk_gate_max=1000000000000
1261 p_state_clk_gate_min=1000
1262 pio_addr=470089728
1263 pio_latency=100000
1264 power_model=Null
1265 system=system
1266 pio=system.iobus.master[21]
1267
1268 [system.realview.nvmem]
1269 type=SimpleMemory
1270 bandwidth=73.000000
1271 clk_domain=system.clk_domain
1272 conf_table_reported=true
1273 default_p_state=UNDEFINED
1274 eventq_index=0
1275 in_addr_map=true
1276 latency=30000
1277 latency_var=0
1278 null=false
1279 p_state_clk_gate_bins=20
1280 p_state_clk_gate_max=1000000000000
1281 p_state_clk_gate_min=1000
1282 power_model=Null
1283 range=0:67108863
1284 port=system.membus.master[1]
1285
1286 [system.realview.pci_host]
1287 type=GenericPciHost
1288 clk_domain=system.clk_domain
1289 conf_base=805306368
1290 conf_device_bits=12
1291 conf_size=268435456
1292 default_p_state=UNDEFINED
1293 eventq_index=0
1294 p_state_clk_gate_bins=20
1295 p_state_clk_gate_max=1000000000000
1296 p_state_clk_gate_min=1000
1297 pci_dma_base=0
1298 pci_mem_base=0
1299 pci_pio_base=788529152
1300 platform=system.realview
1301 power_model=Null
1302 system=system
1303 pio=system.iobus.master[2]
1304
1305 [system.realview.realview_io]
1306 type=RealViewCtrl
1307 clk_domain=system.clk_domain
1308 default_p_state=UNDEFINED
1309 eventq_index=0
1310 idreg=35979264
1311 p_state_clk_gate_bins=20
1312 p_state_clk_gate_max=1000000000000
1313 p_state_clk_gate_min=1000
1314 pio_addr=469827584
1315 pio_latency=100000
1316 power_model=Null
1317 proc_id0=335544320
1318 proc_id1=335544320
1319 system=system
1320 pio=system.iobus.master[1]
1321
1322 [system.realview.rtc]
1323 type=PL031
1324 amba_id=3412017
1325 clk_domain=system.clk_domain
1326 default_p_state=UNDEFINED
1327 eventq_index=0
1328 gic=system.realview.gic
1329 int_delay=100000
1330 int_num=36
1331 p_state_clk_gate_bins=20
1332 p_state_clk_gate_max=1000000000000
1333 p_state_clk_gate_min=1000
1334 pio_addr=471269376
1335 pio_latency=100000
1336 power_model=Null
1337 system=system
1338 time=Thu Jan  1 00:00:00 2009
1339 pio=system.iobus.master[10]
1340
1341 [system.realview.sp810_fake]
1342 type=AmbaFake
1343 amba_id=0
1344 clk_domain=system.clk_domain
1345 default_p_state=UNDEFINED
1346 eventq_index=0
1347 ignore_access=true
1348 p_state_clk_gate_bins=20
1349 p_state_clk_gate_max=1000000000000
1350 p_state_clk_gate_min=1000
1351 pio_addr=469893120
1352 pio_latency=100000
1353 power_model=Null
1354 system=system
1355 pio=system.iobus.master[16]
1356
1357 [system.realview.timer0]
1358 type=Sp804
1359 amba_id=1316868
1360 clk_domain=system.clk_domain
1361 clock0=1000000
1362 clock1=1000000
1363 default_p_state=UNDEFINED
1364 eventq_index=0
1365 gic=system.realview.gic
1366 int_num0=34
1367 int_num1=34
1368 p_state_clk_gate_bins=20
1369 p_state_clk_gate_max=1000000000000
1370 p_state_clk_gate_min=1000
1371 pio_addr=470876160
1372 pio_latency=100000
1373 power_model=Null
1374 system=system
1375 pio=system.iobus.master[3]
1376
1377 [system.realview.timer1]
1378 type=Sp804
1379 amba_id=1316868
1380 clk_domain=system.clk_domain
1381 clock0=1000000
1382 clock1=1000000
1383 default_p_state=UNDEFINED
1384 eventq_index=0
1385 gic=system.realview.gic
1386 int_num0=35
1387 int_num1=35
1388 p_state_clk_gate_bins=20
1389 p_state_clk_gate_max=1000000000000
1390 p_state_clk_gate_min=1000
1391 pio_addr=470941696
1392 pio_latency=100000
1393 power_model=Null
1394 system=system
1395 pio=system.iobus.master[4]
1396
1397 [system.realview.uart]
1398 type=Pl011
1399 clk_domain=system.clk_domain
1400 default_p_state=UNDEFINED
1401 end_on_eot=false
1402 eventq_index=0
1403 gic=system.realview.gic
1404 int_delay=100000
1405 int_num=37
1406 p_state_clk_gate_bins=20
1407 p_state_clk_gate_max=1000000000000
1408 p_state_clk_gate_min=1000
1409 pio_addr=470351872
1410 pio_latency=100000
1411 platform=system.realview
1412 power_model=Null
1413 system=system
1414 terminal=system.terminal
1415 pio=system.iobus.master[0]
1416
1417 [system.realview.uart1_fake]
1418 type=AmbaFake
1419 amba_id=0
1420 clk_domain=system.clk_domain
1421 default_p_state=UNDEFINED
1422 eventq_index=0
1423 ignore_access=false
1424 p_state_clk_gate_bins=20
1425 p_state_clk_gate_max=1000000000000
1426 p_state_clk_gate_min=1000
1427 pio_addr=470417408
1428 pio_latency=100000
1429 power_model=Null
1430 system=system
1431 pio=system.iobus.master[13]
1432
1433 [system.realview.uart2_fake]
1434 type=AmbaFake
1435 amba_id=0
1436 clk_domain=system.clk_domain
1437 default_p_state=UNDEFINED
1438 eventq_index=0
1439 ignore_access=false
1440 p_state_clk_gate_bins=20
1441 p_state_clk_gate_max=1000000000000
1442 p_state_clk_gate_min=1000
1443 pio_addr=470482944
1444 pio_latency=100000
1445 power_model=Null
1446 system=system
1447 pio=system.iobus.master[14]
1448
1449 [system.realview.uart3_fake]
1450 type=AmbaFake
1451 amba_id=0
1452 clk_domain=system.clk_domain
1453 default_p_state=UNDEFINED
1454 eventq_index=0
1455 ignore_access=false
1456 p_state_clk_gate_bins=20
1457 p_state_clk_gate_max=1000000000000
1458 p_state_clk_gate_min=1000
1459 pio_addr=470548480
1460 pio_latency=100000
1461 power_model=Null
1462 system=system
1463 pio=system.iobus.master[15]
1464
1465 [system.realview.usb_fake]
1466 type=IsaFake
1467 clk_domain=system.clk_domain
1468 default_p_state=UNDEFINED
1469 eventq_index=0
1470 fake_mem=false
1471 p_state_clk_gate_bins=20
1472 p_state_clk_gate_max=1000000000000
1473 p_state_clk_gate_min=1000
1474 pio_addr=452984832
1475 pio_latency=100000
1476 pio_size=131071
1477 power_model=Null
1478 ret_bad_addr=false
1479 ret_data16=65535
1480 ret_data32=4294967295
1481 ret_data64=18446744073709551615
1482 ret_data8=255
1483 system=system
1484 update_data=false
1485 warn_access=
1486 pio=system.iobus.master[20]
1487
1488 [system.realview.vgic]
1489 type=VGic
1490 clk_domain=system.clk_domain
1491 default_p_state=UNDEFINED
1492 eventq_index=0
1493 gic=system.realview.gic
1494 hv_addr=738213888
1495 p_state_clk_gate_bins=20
1496 p_state_clk_gate_max=1000000000000
1497 p_state_clk_gate_min=1000
1498 pio_delay=10000
1499 platform=system.realview
1500 power_model=Null
1501 ppint=25
1502 system=system
1503 vcpu_addr=738222080
1504 pio=system.membus.master[3]
1505
1506 [system.realview.vram]
1507 type=SimpleMemory
1508 bandwidth=73.000000
1509 clk_domain=system.clk_domain
1510 conf_table_reported=false
1511 default_p_state=UNDEFINED
1512 eventq_index=0
1513 in_addr_map=true
1514 latency=30000
1515 latency_var=0
1516 null=false
1517 p_state_clk_gate_bins=20
1518 p_state_clk_gate_max=1000000000000
1519 p_state_clk_gate_min=1000
1520 power_model=Null
1521 range=402653184:436207615
1522 port=system.iobus.master[11]
1523
1524 [system.realview.watchdog_fake]
1525 type=AmbaFake
1526 amba_id=0
1527 clk_domain=system.clk_domain
1528 default_p_state=UNDEFINED
1529 eventq_index=0
1530 ignore_access=false
1531 p_state_clk_gate_bins=20
1532 p_state_clk_gate_max=1000000000000
1533 p_state_clk_gate_min=1000
1534 pio_addr=470745088
1535 pio_latency=100000
1536 power_model=Null
1537 system=system
1538 pio=system.iobus.master[17]
1539
1540 [system.terminal]
1541 type=Terminal
1542 eventq_index=0
1543 intr_control=system.intrctrl
1544 number=0
1545 output=true
1546 port=3456
1547
1548 [system.vncserver]
1549 type=VncServer
1550 eventq_index=0
1551 frame_capture=false
1552 number=0
1553 port=5900
1554
1555 [system.voltage_domain]
1556 type=VoltageDomain
1557 eventq_index=0
1558 voltage=1.000000
1559