2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.148086 # Number of seconds simulated
4 sim_ticks 148086239000 # Number of ticks simulated
5 final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1300672 # Simulator instruction rate (inst/s)
8 host_tick_rate 2111359212 # Simulator tick rate (ticks/s)
9 host_mem_usage 351948 # Number of bytes of host memory used
10 host_seconds 70.14 # Real time elapsed on the host
11 sim_insts 91226321 # Number of instructions simulated
12 system.physmem.bytes_read 986112 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 2048 # Number of bytes written to this memory
15 system.physmem.num_reads 15408 # Number of read requests responded to by this memory
16 system.physmem.num_writes 32 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s)
22 system.cpu.dtb.inst_hits 0 # ITB inst hits
23 system.cpu.dtb.inst_misses 0 # ITB inst misses
24 system.cpu.dtb.read_hits 0 # DTB read hits
25 system.cpu.dtb.read_misses 0 # DTB read misses
26 system.cpu.dtb.write_hits 0 # DTB write hits
27 system.cpu.dtb.write_misses 0 # DTB write misses
28 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
29 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
30 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
31 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
32 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
33 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
34 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
35 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
36 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
37 system.cpu.dtb.read_accesses 0 # DTB read accesses
38 system.cpu.dtb.write_accesses 0 # DTB write accesses
39 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
40 system.cpu.dtb.hits 0 # DTB hits
41 system.cpu.dtb.misses 0 # DTB misses
42 system.cpu.dtb.accesses 0 # DTB accesses
43 system.cpu.itb.inst_hits 0 # ITB inst hits
44 system.cpu.itb.inst_misses 0 # ITB inst misses
45 system.cpu.itb.read_hits 0 # DTB read hits
46 system.cpu.itb.read_misses 0 # DTB read misses
47 system.cpu.itb.write_hits 0 # DTB write hits
48 system.cpu.itb.write_misses 0 # DTB write misses
49 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
50 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
51 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
52 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
53 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
54 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
55 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
56 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
57 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
58 system.cpu.itb.read_accesses 0 # DTB read accesses
59 system.cpu.itb.write_accesses 0 # DTB write accesses
60 system.cpu.itb.inst_accesses 0 # ITB inst accesses
61 system.cpu.itb.hits 0 # DTB hits
62 system.cpu.itb.misses 0 # DTB misses
63 system.cpu.itb.accesses 0 # DTB accesses
64 system.cpu.workload.num_syscalls 442 # Number of system calls
65 system.cpu.numCycles 296172478 # number of cpu cycles simulated
66 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
67 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
68 system.cpu.num_insts 91226321 # Number of instructions executed
69 system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
70 system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
71 system.cpu.num_func_calls 96832 # number of times a function call or return occured
72 system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
73 system.cpu.num_int_insts 72525682 # number of integer instructions
74 system.cpu.num_fp_insts 48 # number of float instructions
75 system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
76 system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
77 system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
78 system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
79 system.cpu.num_mem_refs 27318811 # number of memory refs
80 system.cpu.num_load_insts 22573967 # Number of load instructions
81 system.cpu.num_store_insts 4744844 # Number of store instructions
82 system.cpu.num_idle_cycles 0 # Number of idle cycles
83 system.cpu.num_busy_cycles 296172478 # Number of busy cycles
84 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
85 system.cpu.idle_fraction 0 # Percentage of idle cycles
86 system.cpu.icache.replacements 2 # number of replacements
87 system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
88 system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
89 system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
90 system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
91 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
92 system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
93 system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
94 system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
95 system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits
96 system.cpu.icache.overall_hits 107830181 # number of overall hits
97 system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
98 system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
99 system.cpu.icache.overall_misses 599 # number of overall misses
100 system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
101 system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
102 system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
103 system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
104 system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses
105 system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
106 system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
107 system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
108 system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
109 system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
110 system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
111 system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
112 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
113 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
114 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
115 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
116 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
117 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
118 system.cpu.icache.fast_writes 0 # number of fast writes performed
119 system.cpu.icache.cache_copies 0 # number of cache copies performed
120 system.cpu.icache.writebacks 0 # number of writebacks
121 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
122 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
123 system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
124 system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
125 system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
126 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
127 system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
128 system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
129 system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
130 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
131 system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
132 system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
133 system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
134 system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
135 system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
136 system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
137 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
138 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
139 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
140 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
141 system.cpu.dcache.replacements 942702 # number of replacements
142 system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
143 system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
144 system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
145 system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
146 system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
147 system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
148 system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
149 system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
150 system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
151 system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits
152 system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
153 system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
154 system.cpu.dcache.overall_hits 26337591 # number of overall hits
155 system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
156 system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
157 system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses
158 system.cpu.dcache.overall_misses 946798 # number of overall misses
159 system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
160 system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
161 system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
162 system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
163 system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
164 system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
165 system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
166 system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
167 system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
168 system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
169 system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
170 system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
171 system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
172 system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
173 system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
174 system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
175 system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
176 system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
177 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
178 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
179 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
180 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
181 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
182 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
183 system.cpu.dcache.fast_writes 0 # number of fast writes performed
184 system.cpu.dcache.cache_copies 0 # number of cache copies performed
185 system.cpu.dcache.writebacks 942309 # number of writebacks
186 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
187 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
188 system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses
189 system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
190 system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses
191 system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses
192 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
193 system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles
194 system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
195 system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles
196 system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles
197 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
198 system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses
199 system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses
200 system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses
201 system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses
202 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency
203 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
204 system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
205 system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
206 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
207 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
208 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
209 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
210 system.cpu.l2cache.replacements 634 # number of replacements
211 system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
212 system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
213 system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
214 system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
215 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216 system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
217 system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
218 system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
219 system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
220 system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits
221 system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits
222 system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits
223 system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits
224 system.cpu.l2cache.overall_hits 931989 # number of overall hits
225 system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses
226 system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses
227 system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
228 system.cpu.l2cache.overall_misses 15408 # number of overall misses
229 system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles
230 system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles
231 system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
232 system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
233 system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses)
234 system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses)
235 system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
236 system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
237 system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
238 system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
239 system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
240 system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
241 system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
242 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
243 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
244 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
245 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
246 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
247 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
248 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
249 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
250 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
251 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
252 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
253 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
254 system.cpu.l2cache.writebacks 32 # number of writebacks
255 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
256 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
257 system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
258 system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
259 system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
260 system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
261 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
262 system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
263 system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
264 system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
265 system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
266 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
267 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
268 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
269 system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses
270 system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
271 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
272 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
273 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
274 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
275 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
276 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
277 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
278 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
280 ---------- End Simulation Statistics ----------
projects / gem5.git / blob