tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=TimingSimpleCPU
  58 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  59 branchPred=Null
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 cpu_id=0
  63 default_p_state=UNDEFINED
  64 do_checkpoint_insts=true
  65 do_quiesce=true
  66 do_statistics_insts=true
  67 dtb=system.cpu.dtb
  68 eventq_index=0
  69 function_trace=false
  70 function_trace_start=0
  71 interrupts=system.cpu.interrupts
  72 isa=system.cpu.isa
  73 itb=system.cpu.itb
  74 max_insts_all_threads=0
  75 max_insts_any_thread=0
  76 max_loads_all_threads=0
  77 max_loads_any_thread=0
  78 numThreads=1
  79 p_state_clk_gate_bins=20
  80 p_state_clk_gate_max=1000000000000
  81 p_state_clk_gate_min=1000
  82 power_model=Null
  83 profile=0
  84 progress_interval=0
  85 simpoint_start_insts=
  86 socket_id=0
  87 switched_out=false
  88 syscallRetryLatency=10000
  89 system=system
  90 tracer=system.cpu.tracer
  91 workload=system.cpu.workload
  92 dcache_port=system.cpu.dcache.cpu_side
  93 icache_port=system.cpu.icache.cpu_side
  94
  95 [system.cpu.dcache]
  96 type=Cache
  97 children=tags
  98 addr_ranges=0:18446744073709551615:0:0:0:0
  99 assoc=2
 100 clk_domain=system.cpu_clk_domain
 101 clusivity=mostly_incl
 102 data_latency=2
 103 default_p_state=UNDEFINED
 104 demand_mshr_reserve=1
 105 eventq_index=0
 106 is_read_only=false
 107 max_miss_count=0
 108 mshrs=4
 109 p_state_clk_gate_bins=20
 110 p_state_clk_gate_max=1000000000000
 111 p_state_clk_gate_min=1000
 112 power_model=Null
 113 prefetch_on_access=false
 114 prefetcher=Null
 115 response_latency=2
 116 sequential_access=false
 117 size=262144
 118 system=system
 119 tag_latency=2
 120 tags=system.cpu.dcache.tags
 121 tgts_per_mshr=20
 122 write_buffers=8
 123 writeback_clean=false
 124 cpu_side=system.cpu.dcache_port
 125 mem_side=system.cpu.toL2Bus.slave[1]
 126
 127 [system.cpu.dcache.tags]
 128 type=LRU
 129 assoc=2
 130 block_size=64
 131 clk_domain=system.cpu_clk_domain
 132 data_latency=2
 133 default_p_state=UNDEFINED
 134 eventq_index=0
 135 p_state_clk_gate_bins=20
 136 p_state_clk_gate_max=1000000000000
 137 p_state_clk_gate_min=1000
 138 power_model=Null
 139 sequential_access=false
 140 size=262144
 141 tag_latency=2
 142
 143 [system.cpu.dtb]
 144 type=SparcTLB
 145 eventq_index=0
 146 size=64
 147
 148 [system.cpu.icache]
 149 type=Cache
 150 children=tags
 151 addr_ranges=0:18446744073709551615:0:0:0:0
 152 assoc=2
 153 clk_domain=system.cpu_clk_domain
 154 clusivity=mostly_incl
 155 data_latency=2
 156 default_p_state=UNDEFINED
 157 demand_mshr_reserve=1
 158 eventq_index=0
 159 is_read_only=true
 160 max_miss_count=0
 161 mshrs=4
 162 p_state_clk_gate_bins=20
 163 p_state_clk_gate_max=1000000000000
 164 p_state_clk_gate_min=1000
 165 power_model=Null
 166 prefetch_on_access=false
 167 prefetcher=Null
 168 response_latency=2
 169 sequential_access=false
 170 size=131072
 171 system=system
 172 tag_latency=2
 173 tags=system.cpu.icache.tags
 174 tgts_per_mshr=20
 175 write_buffers=8
 176 writeback_clean=true
 177 cpu_side=system.cpu.icache_port
 178 mem_side=system.cpu.toL2Bus.slave[0]
 179
 180 [system.cpu.icache.tags]
 181 type=LRU
 182 assoc=2
 183 block_size=64
 184 clk_domain=system.cpu_clk_domain
 185 data_latency=2
 186 default_p_state=UNDEFINED
 187 eventq_index=0
 188 p_state_clk_gate_bins=20
 189 p_state_clk_gate_max=1000000000000
 190 p_state_clk_gate_min=1000
 191 power_model=Null
 192 sequential_access=false
 193 size=131072
 194 tag_latency=2
 195
 196 [system.cpu.interrupts]
 197 type=SparcInterrupts
 198 eventq_index=0
 199
 200 [system.cpu.isa]
 201 type=SparcISA
 202 eventq_index=0
 203
 204 [system.cpu.itb]
 205 type=SparcTLB
 206 eventq_index=0
 207 size=64
 208
 209 [system.cpu.l2cache]
 210 type=Cache
 211 children=tags
 212 addr_ranges=0:18446744073709551615:0:0:0:0
 213 assoc=8
 214 clk_domain=system.cpu_clk_domain
 215 clusivity=mostly_incl
 216 data_latency=20
 217 default_p_state=UNDEFINED
 218 demand_mshr_reserve=1
 219 eventq_index=0
 220 is_read_only=false
 221 max_miss_count=0
 222 mshrs=20
 223 p_state_clk_gate_bins=20
 224 p_state_clk_gate_max=1000000000000
 225 p_state_clk_gate_min=1000
 226 power_model=Null
 227 prefetch_on_access=false
 228 prefetcher=Null
 229 response_latency=20
 230 sequential_access=false
 231 size=2097152
 232 system=system
 233 tag_latency=20
 234 tags=system.cpu.l2cache.tags
 235 tgts_per_mshr=12
 236 write_buffers=8
 237 writeback_clean=false
 238 cpu_side=system.cpu.toL2Bus.master[0]
 239 mem_side=system.membus.slave[1]
 240
 241 [system.cpu.l2cache.tags]
 242 type=LRU
 243 assoc=8
 244 block_size=64
 245 clk_domain=system.cpu_clk_domain
 246 data_latency=20
 247 default_p_state=UNDEFINED
 248 eventq_index=0
 249 p_state_clk_gate_bins=20
 250 p_state_clk_gate_max=1000000000000
 251 p_state_clk_gate_min=1000
 252 power_model=Null
 253 sequential_access=false
 254 size=2097152
 255 tag_latency=20
 256
 257 [system.cpu.toL2Bus]
 258 type=CoherentXBar
 259 children=snoop_filter
 260 clk_domain=system.cpu_clk_domain
 261 default_p_state=UNDEFINED
 262 eventq_index=0
 263 forward_latency=0
 264 frontend_latency=1
 265 p_state_clk_gate_bins=20
 266 p_state_clk_gate_max=1000000000000
 267 p_state_clk_gate_min=1000
 268 point_of_coherency=false
 269 power_model=Null
 270 response_latency=1
 271 snoop_filter=system.cpu.toL2Bus.snoop_filter
 272 snoop_response_latency=1
 273 system=system
 274 use_default_range=false
 275 width=32
 276 master=system.cpu.l2cache.cpu_side
 277 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 278
 279 [system.cpu.toL2Bus.snoop_filter]
 280 type=SnoopFilter
 281 eventq_index=0
 282 lookup_latency=0
 283 max_capacity=8388608
 284 system=system
 285
 286 [system.cpu.tracer]
 287 type=ExeTracer
 288 eventq_index=0
 289
 290 [system.cpu.workload]
 291 type=Process
 292 cmd=mcf mcf.in
 293 cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 294 drivers=
 295 egid=100
 296 env=
 297 errout=cerr
 298 euid=100
 299 eventq_index=0
 300 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf
 301 gid=100
 302 input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 303 kvmInSE=false
 304 maxStackSize=67108864
 305 output=cout
 306 pgid=100
 307 pid=100
 308 ppid=0
 309 simpoint=55300000000
 310 system=system
 311 uid=100
 312 useArchPT=false
 313
 314 [system.cpu_clk_domain]
 315 type=SrcClockDomain
 316 clock=500
 317 domain_id=-1
 318 eventq_index=0
 319 init_perf_level=0
 320 voltage_domain=system.voltage_domain
 321
 322 [system.dvfs_handler]
 323 type=DVFSHandler
 324 domains=
 325 enable=false
 326 eventq_index=0
 327 sys_clk_domain=system.clk_domain
 328 transition_latency=100000000
 329
 330 [system.membus]
 331 type=CoherentXBar
 332 children=snoop_filter
 333 clk_domain=system.clk_domain
 334 default_p_state=UNDEFINED
 335 eventq_index=0
 336 forward_latency=4
 337 frontend_latency=3
 338 p_state_clk_gate_bins=20
 339 p_state_clk_gate_max=1000000000000
 340 p_state_clk_gate_min=1000
 341 point_of_coherency=true
 342 power_model=Null
 343 response_latency=2
 344 snoop_filter=system.membus.snoop_filter
 345 snoop_response_latency=4
 346 system=system
 347 use_default_range=false
 348 width=16
 349 master=system.physmem.port
 350 slave=system.system_port system.cpu.l2cache.mem_side
 351
 352 [system.membus.snoop_filter]
 353 type=SnoopFilter
 354 eventq_index=0
 355 lookup_latency=1
 356 max_capacity=8388608
 357 system=system
 358
 359 [system.physmem]
 360 type=SimpleMemory
 361 bandwidth=73.000000
 362 clk_domain=system.clk_domain
 363 conf_table_reported=true
 364 default_p_state=UNDEFINED
 365 eventq_index=0
 366 in_addr_map=true
 367 kvm_map=true
 368 latency=30000
 369 latency_var=0
 370 null=false
 371 p_state_clk_gate_bins=20
 372 p_state_clk_gate_max=1000000000000
 373 p_state_clk_gate_min=1000
 374 power_model=Null
 375 range=0:268435455:0:0:0:0
 376 port=system.membus.master[0]
 377
 378 [system.voltage_domain]
 379 type=VoltageDomain
 380 eventq_index=0
 381 voltage=1.000000
 382