tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 kvm_vm=Null
  24 load_addr_mask=1099511627775
  25 load_offset=0
  26 mem_mode=timing
  27 mem_ranges=
  28 memories=system.physmem
  29 mmap_using_noreserve=false
  30 multi_thread=false
  31 num_work_ids=16
  32 p_state_clk_gate_bins=20
  33 p_state_clk_gate_max=1000000000000
  34 p_state_clk_gate_min=1000
  35 power_model=Null
  36 readfile=
  37 symbolfile=
  38 thermal_components=
  39 thermal_model=Null
  40 work_begin_ckpt_count=0
  41 work_begin_cpu_id_exit=-1
  42 work_begin_exit_count=0
  43 work_cpus_ckpt_count=0
  44 work_end_ckpt_count=0
  45 work_end_exit_count=0
  46 work_item_id=-1
  47 system_port=system.membus.slave[0]
  48
  49 [system.clk_domain]
  50 type=SrcClockDomain
  51 clock=1000
  52 domain_id=-1
  53 eventq_index=0
  54 init_perf_level=0
  55 voltage_domain=system.voltage_domain
  56
  57 [system.cpu]
  58 type=TimingSimpleCPU
  59 children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  60 branchPred=Null
  61 checker=Null
  62 clk_domain=system.cpu_clk_domain
  63 cpu_id=0
  64 default_p_state=UNDEFINED
  65 do_checkpoint_insts=true
  66 do_quiesce=true
  67 do_statistics_insts=true
  68 dtb=system.cpu.dtb
  69 eventq_index=0
  70 function_trace=false
  71 function_trace_start=0
  72 interrupts=system.cpu.interrupts
  73 isa=system.cpu.isa
  74 itb=system.cpu.itb
  75 max_insts_all_threads=0
  76 max_insts_any_thread=0
  77 max_loads_all_threads=0
  78 max_loads_any_thread=0
  79 numThreads=1
  80 p_state_clk_gate_bins=20
  81 p_state_clk_gate_max=1000000000000
  82 p_state_clk_gate_min=1000
  83 power_model=Null
  84 profile=0
  85 progress_interval=0
  86 simpoint_start_insts=
  87 socket_id=0
  88 switched_out=false
  89 syscallRetryLatency=10000
  90 system=system
  91 tracer=system.cpu.tracer
  92 workload=system.cpu.workload
  93 dcache_port=system.cpu.dcache.cpu_side
  94 icache_port=system.cpu.icache.cpu_side
  95
  96 [system.cpu.apic_clk_domain]
  97 type=DerivedClockDomain
  98 clk_divider=16
  99 clk_domain=system.cpu_clk_domain
 100 eventq_index=0
 101
 102 [system.cpu.dcache]
 103 type=Cache
 104 children=tags
 105 addr_ranges=0:18446744073709551615:0:0:0:0
 106 assoc=2
 107 clk_domain=system.cpu_clk_domain
 108 clusivity=mostly_incl
 109 data_latency=2
 110 default_p_state=UNDEFINED
 111 demand_mshr_reserve=1
 112 eventq_index=0
 113 is_read_only=false
 114 max_miss_count=0
 115 mshrs=4
 116 p_state_clk_gate_bins=20
 117 p_state_clk_gate_max=1000000000000
 118 p_state_clk_gate_min=1000
 119 power_model=Null
 120 prefetch_on_access=false
 121 prefetcher=Null
 122 response_latency=2
 123 sequential_access=false
 124 size=262144
 125 system=system
 126 tag_latency=2
 127 tags=system.cpu.dcache.tags
 128 tgts_per_mshr=20
 129 write_buffers=8
 130 writeback_clean=false
 131 cpu_side=system.cpu.dcache_port
 132 mem_side=system.cpu.toL2Bus.slave[1]
 133
 134 [system.cpu.dcache.tags]
 135 type=LRU
 136 assoc=2
 137 block_size=64
 138 clk_domain=system.cpu_clk_domain
 139 data_latency=2
 140 default_p_state=UNDEFINED
 141 eventq_index=0
 142 p_state_clk_gate_bins=20
 143 p_state_clk_gate_max=1000000000000
 144 p_state_clk_gate_min=1000
 145 power_model=Null
 146 sequential_access=false
 147 size=262144
 148 tag_latency=2
 149
 150 [system.cpu.dtb]
 151 type=X86TLB
 152 children=walker
 153 eventq_index=0
 154 size=64
 155 walker=system.cpu.dtb.walker
 156
 157 [system.cpu.dtb.walker]
 158 type=X86PagetableWalker
 159 clk_domain=system.cpu_clk_domain
 160 default_p_state=UNDEFINED
 161 eventq_index=0
 162 num_squash_per_cycle=4
 163 p_state_clk_gate_bins=20
 164 p_state_clk_gate_max=1000000000000
 165 p_state_clk_gate_min=1000
 166 power_model=Null
 167 system=system
 168 port=system.cpu.toL2Bus.slave[3]
 169
 170 [system.cpu.icache]
 171 type=Cache
 172 children=tags
 173 addr_ranges=0:18446744073709551615:0:0:0:0
 174 assoc=2
 175 clk_domain=system.cpu_clk_domain
 176 clusivity=mostly_incl
 177 data_latency=2
 178 default_p_state=UNDEFINED
 179 demand_mshr_reserve=1
 180 eventq_index=0
 181 is_read_only=true
 182 max_miss_count=0
 183 mshrs=4
 184 p_state_clk_gate_bins=20
 185 p_state_clk_gate_max=1000000000000
 186 p_state_clk_gate_min=1000
 187 power_model=Null
 188 prefetch_on_access=false
 189 prefetcher=Null
 190 response_latency=2
 191 sequential_access=false
 192 size=131072
 193 system=system
 194 tag_latency=2
 195 tags=system.cpu.icache.tags
 196 tgts_per_mshr=20
 197 write_buffers=8
 198 writeback_clean=true
 199 cpu_side=system.cpu.icache_port
 200 mem_side=system.cpu.toL2Bus.slave[0]
 201
 202 [system.cpu.icache.tags]
 203 type=LRU
 204 assoc=2
 205 block_size=64
 206 clk_domain=system.cpu_clk_domain
 207 data_latency=2
 208 default_p_state=UNDEFINED
 209 eventq_index=0
 210 p_state_clk_gate_bins=20
 211 p_state_clk_gate_max=1000000000000
 212 p_state_clk_gate_min=1000
 213 power_model=Null
 214 sequential_access=false
 215 size=131072
 216 tag_latency=2
 217
 218 [system.cpu.interrupts]
 219 type=X86LocalApic
 220 clk_domain=system.cpu.apic_clk_domain
 221 default_p_state=UNDEFINED
 222 eventq_index=0
 223 int_latency=1000
 224 p_state_clk_gate_bins=20
 225 p_state_clk_gate_max=1000000000000
 226 p_state_clk_gate_min=1000
 227 pio_addr=2305843009213693952
 228 pio_latency=100000
 229 power_model=Null
 230 system=system
 231 int_master=system.membus.slave[2]
 232 int_slave=system.membus.master[2]
 233 pio=system.membus.master[1]
 234
 235 [system.cpu.isa]
 236 type=X86ISA
 237 eventq_index=0
 238
 239 [system.cpu.itb]
 240 type=X86TLB
 241 children=walker
 242 eventq_index=0
 243 size=64
 244 walker=system.cpu.itb.walker
 245
 246 [system.cpu.itb.walker]
 247 type=X86PagetableWalker
 248 clk_domain=system.cpu_clk_domain
 249 default_p_state=UNDEFINED
 250 eventq_index=0
 251 num_squash_per_cycle=4
 252 p_state_clk_gate_bins=20
 253 p_state_clk_gate_max=1000000000000
 254 p_state_clk_gate_min=1000
 255 power_model=Null
 256 system=system
 257 port=system.cpu.toL2Bus.slave[2]
 258
 259 [system.cpu.l2cache]
 260 type=Cache
 261 children=tags
 262 addr_ranges=0:18446744073709551615:0:0:0:0
 263 assoc=8
 264 clk_domain=system.cpu_clk_domain
 265 clusivity=mostly_incl
 266 data_latency=20
 267 default_p_state=UNDEFINED
 268 demand_mshr_reserve=1
 269 eventq_index=0
 270 is_read_only=false
 271 max_miss_count=0
 272 mshrs=20
 273 p_state_clk_gate_bins=20
 274 p_state_clk_gate_max=1000000000000
 275 p_state_clk_gate_min=1000
 276 power_model=Null
 277 prefetch_on_access=false
 278 prefetcher=Null
 279 response_latency=20
 280 sequential_access=false
 281 size=2097152
 282 system=system
 283 tag_latency=20
 284 tags=system.cpu.l2cache.tags
 285 tgts_per_mshr=12
 286 write_buffers=8
 287 writeback_clean=false
 288 cpu_side=system.cpu.toL2Bus.master[0]
 289 mem_side=system.membus.slave[1]
 290
 291 [system.cpu.l2cache.tags]
 292 type=LRU
 293 assoc=8
 294 block_size=64
 295 clk_domain=system.cpu_clk_domain
 296 data_latency=20
 297 default_p_state=UNDEFINED
 298 eventq_index=0
 299 p_state_clk_gate_bins=20
 300 p_state_clk_gate_max=1000000000000
 301 p_state_clk_gate_min=1000
 302 power_model=Null
 303 sequential_access=false
 304 size=2097152
 305 tag_latency=20
 306
 307 [system.cpu.toL2Bus]
 308 type=CoherentXBar
 309 children=snoop_filter
 310 clk_domain=system.cpu_clk_domain
 311 default_p_state=UNDEFINED
 312 eventq_index=0
 313 forward_latency=0
 314 frontend_latency=1
 315 p_state_clk_gate_bins=20
 316 p_state_clk_gate_max=1000000000000
 317 p_state_clk_gate_min=1000
 318 point_of_coherency=false
 319 power_model=Null
 320 response_latency=1
 321 snoop_filter=system.cpu.toL2Bus.snoop_filter
 322 snoop_response_latency=1
 323 system=system
 324 use_default_range=false
 325 width=32
 326 master=system.cpu.l2cache.cpu_side
 327 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 328
 329 [system.cpu.toL2Bus.snoop_filter]
 330 type=SnoopFilter
 331 eventq_index=0
 332 lookup_latency=0
 333 max_capacity=8388608
 334 system=system
 335
 336 [system.cpu.tracer]
 337 type=ExeTracer
 338 eventq_index=0
 339
 340 [system.cpu.workload]
 341 type=Process
 342 cmd=mcf mcf.in
 343 cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 344 drivers=
 345 egid=100
 346 env=
 347 errout=cerr
 348 euid=100
 349 eventq_index=0
 350 executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
 351 gid=100
 352 input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 353 kvmInSE=false
 354 maxStackSize=67108864
 355 output=cout
 356 pgid=100
 357 pid=100
 358 ppid=0
 359 simpoint=55300000000
 360 system=system
 361 uid=100
 362 useArchPT=false
 363
 364 [system.cpu_clk_domain]
 365 type=SrcClockDomain
 366 clock=500
 367 domain_id=-1
 368 eventq_index=0
 369 init_perf_level=0
 370 voltage_domain=system.voltage_domain
 371
 372 [system.dvfs_handler]
 373 type=DVFSHandler
 374 domains=
 375 enable=false
 376 eventq_index=0
 377 sys_clk_domain=system.clk_domain
 378 transition_latency=100000000
 379
 380 [system.membus]
 381 type=CoherentXBar
 382 children=snoop_filter
 383 clk_domain=system.clk_domain
 384 default_p_state=UNDEFINED
 385 eventq_index=0
 386 forward_latency=4
 387 frontend_latency=3
 388 p_state_clk_gate_bins=20
 389 p_state_clk_gate_max=1000000000000
 390 p_state_clk_gate_min=1000
 391 point_of_coherency=true
 392 power_model=Null
 393 response_latency=2
 394 snoop_filter=system.membus.snoop_filter
 395 snoop_response_latency=4
 396 system=system
 397 use_default_range=false
 398 width=16
 399 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 400 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 401
 402 [system.membus.snoop_filter]
 403 type=SnoopFilter
 404 eventq_index=0
 405 lookup_latency=1
 406 max_capacity=8388608
 407 system=system
 408
 409 [system.physmem]
 410 type=SimpleMemory
 411 bandwidth=73.000000
 412 clk_domain=system.clk_domain
 413 conf_table_reported=true
 414 default_p_state=UNDEFINED
 415 eventq_index=0
 416 in_addr_map=true
 417 kvm_map=true
 418 latency=30000
 419 latency_var=0
 420 null=false
 421 p_state_clk_gate_bins=20
 422 p_state_clk_gate_max=1000000000000
 423 p_state_clk_gate_min=1000
 424 power_model=Null
 425 range=0:268435455:0:0:0:0
 426 port=system.membus.master[0]
 427
 428 [system.voltage_domain]
 429 type=VoltageDomain
 430 eventq_index=0
 431 voltage=1.000000
 432