2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.134277 # Number of seconds simulated
4 sim_ticks 134276988000 # Number of ticks simulated
5 final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1801981 # Simulator instruction rate (inst/s)
8 host_tick_rate 2738992827 # Simulator tick rate (ticks/s)
9 host_mem_usage 215584 # Number of bytes of host memory used
10 host_seconds 49.02 # Real time elapsed on the host
11 sim_insts 88340673 # Number of instructions simulated
12 system.physmem.bytes_read 11121920 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 7712384 # Number of bytes written to this memory
15 system.physmem.num_reads 173780 # Number of read requests responded to by this memory
16 system.physmem.num_writes 120506 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s)
22 system.cpu.dtb.fetch_hits 0 # ITB hits
23 system.cpu.dtb.fetch_misses 0 # ITB misses
24 system.cpu.dtb.fetch_acv 0 # ITB acv
25 system.cpu.dtb.fetch_accesses 0 # ITB accesses
26 system.cpu.dtb.read_hits 20276638 # DTB read hits
27 system.cpu.dtb.read_misses 90148 # DTB read misses
28 system.cpu.dtb.read_acv 0 # DTB read access violations
29 system.cpu.dtb.read_accesses 20366786 # DTB read accesses
30 system.cpu.dtb.write_hits 14613377 # DTB write hits
31 system.cpu.dtb.write_misses 7252 # DTB write misses
32 system.cpu.dtb.write_acv 0 # DTB write access violations
33 system.cpu.dtb.write_accesses 14620629 # DTB write accesses
34 system.cpu.dtb.data_hits 34890015 # DTB hits
35 system.cpu.dtb.data_misses 97400 # DTB misses
36 system.cpu.dtb.data_acv 0 # DTB access violations
37 system.cpu.dtb.data_accesses 34987415 # DTB accesses
38 system.cpu.itb.fetch_hits 88438074 # ITB hits
39 system.cpu.itb.fetch_misses 3934 # ITB misses
40 system.cpu.itb.fetch_acv 0 # ITB acv
41 system.cpu.itb.fetch_accesses 88442008 # ITB accesses
42 system.cpu.itb.read_hits 0 # DTB read hits
43 system.cpu.itb.read_misses 0 # DTB read misses
44 system.cpu.itb.read_acv 0 # DTB read access violations
45 system.cpu.itb.read_accesses 0 # DTB read accesses
46 system.cpu.itb.write_hits 0 # DTB write hits
47 system.cpu.itb.write_misses 0 # DTB write misses
48 system.cpu.itb.write_acv 0 # DTB write access violations
49 system.cpu.itb.write_accesses 0 # DTB write accesses
50 system.cpu.itb.data_hits 0 # DTB hits
51 system.cpu.itb.data_misses 0 # DTB misses
52 system.cpu.itb.data_acv 0 # DTB access violations
53 system.cpu.itb.data_accesses 0 # DTB accesses
54 system.cpu.workload.num_syscalls 4583 # Number of system calls
55 system.cpu.numCycles 268553976 # number of cpu cycles simulated
56 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
57 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
58 system.cpu.num_insts 88340673 # Number of instructions executed
59 system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
60 system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
61 system.cpu.num_func_calls 3321606 # number of times a function call or return occured
62 system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
63 system.cpu.num_int_insts 78039444 # number of integer instructions
64 system.cpu.num_fp_insts 267757 # number of float instructions
65 system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
66 system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
67 system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
68 system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
69 system.cpu.num_mem_refs 34987415 # number of memory refs
70 system.cpu.num_load_insts 20366786 # Number of load instructions
71 system.cpu.num_store_insts 14620629 # Number of store instructions
72 system.cpu.num_idle_cycles 0 # Number of idle cycles
73 system.cpu.num_busy_cycles 268553976 # Number of busy cycles
74 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
75 system.cpu.idle_fraction 0 # Percentage of idle cycles
76 system.cpu.icache.replacements 74391 # number of replacements
77 system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
78 system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
79 system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
80 system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
81 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
82 system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context
83 system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy
84 system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
85 system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
86 system.cpu.icache.overall_hits 88361638 # number of overall hits
87 system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
88 system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
89 system.cpu.icache.overall_misses 76436 # number of overall misses
90 system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles
91 system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles
92 system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles
93 system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
94 system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
95 system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
96 system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
97 system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
98 system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
99 system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency
100 system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency
101 system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency
102 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
103 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
104 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
105 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
106 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
107 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
108 system.cpu.icache.fast_writes 0 # number of fast writes performed
109 system.cpu.icache.cache_copies 0 # number of cache copies performed
110 system.cpu.icache.writebacks 0 # number of writebacks
111 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
112 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
113 system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
114 system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
115 system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
116 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
117 system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles
118 system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles
119 system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles
120 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
121 system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
122 system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
123 system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
124 system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency
125 system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
126 system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
127 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
128 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
129 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
130 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
131 system.cpu.dcache.replacements 200248 # number of replacements
132 system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
133 system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
134 system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
135 system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
136 system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
137 system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context
138 system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy
139 system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
140 system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
141 system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits
142 system.cpu.dcache.overall_hits 34685671 # number of overall hits
143 system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
144 system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
145 system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses
146 system.cpu.dcache.overall_misses 204344 # number of overall misses
147 system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles
148 system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles
149 system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles
150 system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles
151 system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
152 system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
153 system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
154 system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
155 system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
156 system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
157 system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
158 system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
159 system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency
160 system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency
161 system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency
162 system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency
163 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
164 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
165 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
166 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
167 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
168 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
169 system.cpu.dcache.fast_writes 0 # number of fast writes performed
170 system.cpu.dcache.cache_copies 0 # number of cache copies performed
171 system.cpu.dcache.writebacks 161222 # number of writebacks
172 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
173 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
174 system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
175 system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
176 system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
177 system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
178 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
179 system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles
180 system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles
181 system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles
182 system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles
183 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
184 system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
185 system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
186 system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
187 system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
188 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency
189 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency
190 system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
191 system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
192 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
193 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
194 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
195 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
196 system.cpu.l2cache.replacements 147405 # number of replacements
197 system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
198 system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
199 system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
200 system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
201 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
202 system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context
203 system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context
204 system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy
205 system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy
206 system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits
207 system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits
208 system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
209 system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits
210 system.cpu.l2cache.overall_hits 107000 # number of overall hits
211 system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses
212 system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
213 system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses
214 system.cpu.l2cache.overall_misses 173780 # number of overall misses
215 system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles
216 system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles
217 system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles
218 system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles
219 system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
220 system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses)
221 system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
222 system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
223 system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
224 system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses
225 system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
226 system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses
227 system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses
228 system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
229 system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
230 system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
231 system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
232 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
233 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
234 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
235 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
236 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
237 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
238 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
239 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
240 system.cpu.l2cache.writebacks 120506 # number of writebacks
241 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
242 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
243 system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses
244 system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
245 system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses
246 system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses
247 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
248 system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles
249 system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles
250 system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles
251 system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles
252 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
253 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses
254 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
255 system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses
256 system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses
257 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
258 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
259 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
260 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
261 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
262 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
263 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
264 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
266 ---------- End Simulation Statistics ----------
projects / gem5.git / blob