tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=MinorCPU
  58 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  59 branchPred=system.cpu.branchPred
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 cpu_id=0
  63 decodeCycleInput=true
  64 decodeInputBufferSize=3
  65 decodeInputWidth=2
  66 decodeToExecuteForwardDelay=1
  67 default_p_state=UNDEFINED
  68 do_checkpoint_insts=true
  69 do_quiesce=true
  70 do_statistics_insts=true
  71 dstage2_mmu=system.cpu.dstage2_mmu
  72 dtb=system.cpu.dtb
  73 enableIdling=true
  74 eventq_index=0
  75 executeAllowEarlyMemoryIssue=true
  76 executeBranchDelay=1
  77 executeCommitLimit=2
  78 executeCycleInput=true
  79 executeFuncUnits=system.cpu.executeFuncUnits
  80 executeInputBufferSize=7
  81 executeInputWidth=2
  82 executeIssueLimit=2
  83 executeLSQMaxStoreBufferStoresPerCycle=2
  84 executeLSQRequestsQueueSize=1
  85 executeLSQStoreBufferSize=5
  86 executeLSQTransfersQueueSize=2
  87 executeMaxAccessesInMemory=2
  88 executeMemoryCommitLimit=1
  89 executeMemoryIssueLimit=1
  90 executeMemoryWidth=0
  91 executeSetTraceTimeOnCommit=true
  92 executeSetTraceTimeOnIssue=false
  93 fetch1FetchLimit=1
  94 fetch1LineSnapWidth=0
  95 fetch1LineWidth=0
  96 fetch1ToFetch2BackwardDelay=1
  97 fetch1ToFetch2ForwardDelay=1
  98 fetch2CycleInput=true
  99 fetch2InputBufferSize=2
 100 fetch2ToDecodeForwardDelay=1
 101 function_trace=false
 102 function_trace_start=0
 103 interrupts=system.cpu.interrupts
 104 isa=system.cpu.isa
 105 istage2_mmu=system.cpu.istage2_mmu
 106 itb=system.cpu.itb
 107 max_insts_all_threads=0
 108 max_insts_any_thread=0
 109 max_loads_all_threads=0
 110 max_loads_any_thread=0
 111 numThreads=1
 112 p_state_clk_gate_bins=20
 113 p_state_clk_gate_max=1000000000000
 114 p_state_clk_gate_min=1000
 115 power_model=Null
 116 profile=0
 117 progress_interval=0
 118 simpoint_start_insts=
 119 socket_id=0
 120 switched_out=false
 121 system=system
 122 threadPolicy=RoundRobin
 123 tracer=system.cpu.tracer
 124 workload=system.cpu.workload
 125 dcache_port=system.cpu.dcache.cpu_side
 126 icache_port=system.cpu.icache.cpu_side
 127
 128 [system.cpu.branchPred]
 129 type=TournamentBP
 130 BTBEntries=4096
 131 BTBTagSize=16
 132 RASSize=16
 133 choiceCtrBits=2
 134 choicePredictorSize=8192
 135 eventq_index=0
 136 globalCtrBits=2
 137 globalPredictorSize=8192
 138 indirectHashGHR=true
 139 indirectHashTargets=true
 140 indirectPathLength=3
 141 indirectSets=256
 142 indirectTagSize=16
 143 indirectWays=2
 144 instShiftAmt=2
 145 localCtrBits=2
 146 localHistoryTableSize=2048
 147 localPredictorSize=2048
 148 numThreads=1
 149 useIndirect=true
 150
 151 [system.cpu.dcache]
 152 type=Cache
 153 children=tags
 154 addr_ranges=0:18446744073709551615:0:0:0:0
 155 assoc=2
 156 clk_domain=system.cpu_clk_domain
 157 clusivity=mostly_incl
 158 default_p_state=UNDEFINED
 159 demand_mshr_reserve=1
 160 eventq_index=0
 161 hit_latency=2
 162 is_read_only=false
 163 max_miss_count=0
 164 mshrs=4
 165 p_state_clk_gate_bins=20
 166 p_state_clk_gate_max=1000000000000
 167 p_state_clk_gate_min=1000
 168 power_model=Null
 169 prefetch_on_access=false
 170 prefetcher=Null
 171 response_latency=2
 172 sequential_access=false
 173 size=262144
 174 system=system
 175 tags=system.cpu.dcache.tags
 176 tgts_per_mshr=20
 177 write_buffers=8
 178 writeback_clean=false
 179 cpu_side=system.cpu.dcache_port
 180 mem_side=system.cpu.toL2Bus.slave[1]
 181
 182 [system.cpu.dcache.tags]
 183 type=LRU
 184 assoc=2
 185 block_size=64
 186 clk_domain=system.cpu_clk_domain
 187 default_p_state=UNDEFINED
 188 eventq_index=0
 189 hit_latency=2
 190 p_state_clk_gate_bins=20
 191 p_state_clk_gate_max=1000000000000
 192 p_state_clk_gate_min=1000
 193 power_model=Null
 194 sequential_access=false
 195 size=262144
 196
 197 [system.cpu.dstage2_mmu]
 198 type=ArmStage2MMU
 199 children=stage2_tlb
 200 eventq_index=0
 201 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 202 sys=system
 203 tlb=system.cpu.dtb
 204
 205 [system.cpu.dstage2_mmu.stage2_tlb]
 206 type=ArmTLB
 207 children=walker
 208 eventq_index=0
 209 is_stage2=true
 210 size=32
 211 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 212
 213 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 214 type=ArmTableWalker
 215 clk_domain=system.cpu_clk_domain
 216 default_p_state=UNDEFINED
 217 eventq_index=0
 218 is_stage2=true
 219 num_squash_per_cycle=2
 220 p_state_clk_gate_bins=20
 221 p_state_clk_gate_max=1000000000000
 222 p_state_clk_gate_min=1000
 223 power_model=Null
 224 sys=system
 225
 226 [system.cpu.dtb]
 227 type=ArmTLB
 228 children=walker
 229 eventq_index=0
 230 is_stage2=false
 231 size=64
 232 walker=system.cpu.dtb.walker
 233
 234 [system.cpu.dtb.walker]
 235 type=ArmTableWalker
 236 clk_domain=system.cpu_clk_domain
 237 default_p_state=UNDEFINED
 238 eventq_index=0
 239 is_stage2=false
 240 num_squash_per_cycle=2
 241 p_state_clk_gate_bins=20
 242 p_state_clk_gate_max=1000000000000
 243 p_state_clk_gate_min=1000
 244 power_model=Null
 245 sys=system
 246 port=system.cpu.toL2Bus.slave[3]
 247
 248 [system.cpu.executeFuncUnits]
 249 type=MinorFUPool
 250 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 251 eventq_index=0
 252 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 253
 254 [system.cpu.executeFuncUnits.funcUnits0]
 255 type=MinorFU
 256 children=opClasses timings
 257 cantForwardFromFUIndices=
 258 eventq_index=0
 259 issueLat=1
 260 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 261 opLat=3
 262 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 263
 264 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 265 type=MinorOpClassSet
 266 children=opClasses
 267 eventq_index=0
 268 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 269
 270 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 271 type=MinorOpClass
 272 eventq_index=0
 273 opClass=IntAlu
 274
 275 [system.cpu.executeFuncUnits.funcUnits0.timings]
 276 type=MinorFUTiming
 277 children=opClasses
 278 description=Int
 279 eventq_index=0
 280 extraAssumedLat=0
 281 extraCommitLat=0
 282 extraCommitLatExpr=Null
 283 mask=0
 284 match=0
 285 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 286 srcRegsRelativeLats=2
 287 suppress=false
 288
 289 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 290 type=MinorOpClassSet
 291 eventq_index=0
 292 opClasses=
 293
 294 [system.cpu.executeFuncUnits.funcUnits1]
 295 type=MinorFU
 296 children=opClasses timings
 297 cantForwardFromFUIndices=
 298 eventq_index=0
 299 issueLat=1
 300 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 301 opLat=3
 302 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 303
 304 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 305 type=MinorOpClassSet
 306 children=opClasses
 307 eventq_index=0
 308 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 309
 310 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 311 type=MinorOpClass
 312 eventq_index=0
 313 opClass=IntAlu
 314
 315 [system.cpu.executeFuncUnits.funcUnits1.timings]
 316 type=MinorFUTiming
 317 children=opClasses
 318 description=Int
 319 eventq_index=0
 320 extraAssumedLat=0
 321 extraCommitLat=0
 322 extraCommitLatExpr=Null
 323 mask=0
 324 match=0
 325 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 326 srcRegsRelativeLats=2
 327 suppress=false
 328
 329 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 330 type=MinorOpClassSet
 331 eventq_index=0
 332 opClasses=
 333
 334 [system.cpu.executeFuncUnits.funcUnits2]
 335 type=MinorFU
 336 children=opClasses timings
 337 cantForwardFromFUIndices=
 338 eventq_index=0
 339 issueLat=1
 340 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 341 opLat=3
 342 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 343
 344 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 345 type=MinorOpClassSet
 346 children=opClasses
 347 eventq_index=0
 348 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 349
 350 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 351 type=MinorOpClass
 352 eventq_index=0
 353 opClass=IntMult
 354
 355 [system.cpu.executeFuncUnits.funcUnits2.timings]
 356 type=MinorFUTiming
 357 children=opClasses
 358 description=Mul
 359 eventq_index=0
 360 extraAssumedLat=0
 361 extraCommitLat=0
 362 extraCommitLatExpr=Null
 363 mask=0
 364 match=0
 365 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 366 srcRegsRelativeLats=0
 367 suppress=false
 368
 369 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 370 type=MinorOpClassSet
 371 eventq_index=0
 372 opClasses=
 373
 374 [system.cpu.executeFuncUnits.funcUnits3]
 375 type=MinorFU
 376 children=opClasses
 377 cantForwardFromFUIndices=
 378 eventq_index=0
 379 issueLat=9
 380 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 381 opLat=9
 382 timings=
 383
 384 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 385 type=MinorOpClassSet
 386 children=opClasses
 387 eventq_index=0
 388 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 389
 390 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 391 type=MinorOpClass
 392 eventq_index=0
 393 opClass=IntDiv
 394
 395 [system.cpu.executeFuncUnits.funcUnits4]
 396 type=MinorFU
 397 children=opClasses timings
 398 cantForwardFromFUIndices=
 399 eventq_index=0
 400 issueLat=1
 401 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 402 opLat=6
 403 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 404
 405 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 406 type=MinorOpClassSet
 407 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 408 eventq_index=0
 409 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 410
 411 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 412 type=MinorOpClass
 413 eventq_index=0
 414 opClass=FloatAdd
 415
 416 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 417 type=MinorOpClass
 418 eventq_index=0
 419 opClass=FloatCmp
 420
 421 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 422 type=MinorOpClass
 423 eventq_index=0
 424 opClass=FloatCvt
 425
 426 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 427 type=MinorOpClass
 428 eventq_index=0
 429 opClass=FloatMult
 430
 431 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 432 type=MinorOpClass
 433 eventq_index=0
 434 opClass=FloatDiv
 435
 436 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 437 type=MinorOpClass
 438 eventq_index=0
 439 opClass=FloatSqrt
 440
 441 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 442 type=MinorOpClass
 443 eventq_index=0
 444 opClass=SimdAdd
 445
 446 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 447 type=MinorOpClass
 448 eventq_index=0
 449 opClass=SimdAddAcc
 450
 451 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 452 type=MinorOpClass
 453 eventq_index=0
 454 opClass=SimdAlu
 455
 456 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 457 type=MinorOpClass
 458 eventq_index=0
 459 opClass=SimdCmp
 460
 461 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 462 type=MinorOpClass
 463 eventq_index=0
 464 opClass=SimdCvt
 465
 466 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 467 type=MinorOpClass
 468 eventq_index=0
 469 opClass=SimdMisc
 470
 471 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 472 type=MinorOpClass
 473 eventq_index=0
 474 opClass=SimdMult
 475
 476 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 477 type=MinorOpClass
 478 eventq_index=0
 479 opClass=SimdMultAcc
 480
 481 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 482 type=MinorOpClass
 483 eventq_index=0
 484 opClass=SimdShift
 485
 486 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 487 type=MinorOpClass
 488 eventq_index=0
 489 opClass=SimdShiftAcc
 490
 491 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 492 type=MinorOpClass
 493 eventq_index=0
 494 opClass=SimdSqrt
 495
 496 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 497 type=MinorOpClass
 498 eventq_index=0
 499 opClass=SimdFloatAdd
 500
 501 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 502 type=MinorOpClass
 503 eventq_index=0
 504 opClass=SimdFloatAlu
 505
 506 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 507 type=MinorOpClass
 508 eventq_index=0
 509 opClass=SimdFloatCmp
 510
 511 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 512 type=MinorOpClass
 513 eventq_index=0
 514 opClass=SimdFloatCvt
 515
 516 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 517 type=MinorOpClass
 518 eventq_index=0
 519 opClass=SimdFloatDiv
 520
 521 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 522 type=MinorOpClass
 523 eventq_index=0
 524 opClass=SimdFloatMisc
 525
 526 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 527 type=MinorOpClass
 528 eventq_index=0
 529 opClass=SimdFloatMult
 530
 531 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 532 type=MinorOpClass
 533 eventq_index=0
 534 opClass=SimdFloatMultAcc
 535
 536 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 537 type=MinorOpClass
 538 eventq_index=0
 539 opClass=SimdFloatSqrt
 540
 541 [system.cpu.executeFuncUnits.funcUnits4.timings]
 542 type=MinorFUTiming
 543 children=opClasses
 544 description=FloatSimd
 545 eventq_index=0
 546 extraAssumedLat=0
 547 extraCommitLat=0
 548 extraCommitLatExpr=Null
 549 mask=0
 550 match=0
 551 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 552 srcRegsRelativeLats=2
 553 suppress=false
 554
 555 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 556 type=MinorOpClassSet
 557 eventq_index=0
 558 opClasses=
 559
 560 [system.cpu.executeFuncUnits.funcUnits5]
 561 type=MinorFU
 562 children=opClasses timings
 563 cantForwardFromFUIndices=
 564 eventq_index=0
 565 issueLat=1
 566 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 567 opLat=1
 568 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 569
 570 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 571 type=MinorOpClassSet
 572 children=opClasses0 opClasses1
 573 eventq_index=0
 574 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 575
 576 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 577 type=MinorOpClass
 578 eventq_index=0
 579 opClass=MemRead
 580
 581 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 582 type=MinorOpClass
 583 eventq_index=0
 584 opClass=MemWrite
 585
 586 [system.cpu.executeFuncUnits.funcUnits5.timings]
 587 type=MinorFUTiming
 588 children=opClasses
 589 description=Mem
 590 eventq_index=0
 591 extraAssumedLat=2
 592 extraCommitLat=0
 593 extraCommitLatExpr=Null
 594 mask=0
 595 match=0
 596 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 597 srcRegsRelativeLats=1
 598 suppress=false
 599
 600 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 601 type=MinorOpClassSet
 602 eventq_index=0
 603 opClasses=
 604
 605 [system.cpu.executeFuncUnits.funcUnits6]
 606 type=MinorFU
 607 children=opClasses
 608 cantForwardFromFUIndices=
 609 eventq_index=0
 610 issueLat=1
 611 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 612 opLat=1
 613 timings=
 614
 615 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 616 type=MinorOpClassSet
 617 children=opClasses0 opClasses1
 618 eventq_index=0
 619 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 620
 621 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 622 type=MinorOpClass
 623 eventq_index=0
 624 opClass=IprAccess
 625
 626 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 627 type=MinorOpClass
 628 eventq_index=0
 629 opClass=InstPrefetch
 630
 631 [system.cpu.icache]
 632 type=Cache
 633 children=tags
 634 addr_ranges=0:18446744073709551615:0:0:0:0
 635 assoc=2
 636 clk_domain=system.cpu_clk_domain
 637 clusivity=mostly_incl
 638 default_p_state=UNDEFINED
 639 demand_mshr_reserve=1
 640 eventq_index=0
 641 hit_latency=2
 642 is_read_only=true
 643 max_miss_count=0
 644 mshrs=4
 645 p_state_clk_gate_bins=20
 646 p_state_clk_gate_max=1000000000000
 647 p_state_clk_gate_min=1000
 648 power_model=Null
 649 prefetch_on_access=false
 650 prefetcher=Null
 651 response_latency=2
 652 sequential_access=false
 653 size=131072
 654 system=system
 655 tags=system.cpu.icache.tags
 656 tgts_per_mshr=20
 657 write_buffers=8
 658 writeback_clean=true
 659 cpu_side=system.cpu.icache_port
 660 mem_side=system.cpu.toL2Bus.slave[0]
 661
 662 [system.cpu.icache.tags]
 663 type=LRU
 664 assoc=2
 665 block_size=64
 666 clk_domain=system.cpu_clk_domain
 667 default_p_state=UNDEFINED
 668 eventq_index=0
 669 hit_latency=2
 670 p_state_clk_gate_bins=20
 671 p_state_clk_gate_max=1000000000000
 672 p_state_clk_gate_min=1000
 673 power_model=Null
 674 sequential_access=false
 675 size=131072
 676
 677 [system.cpu.interrupts]
 678 type=ArmInterrupts
 679 eventq_index=0
 680
 681 [system.cpu.isa]
 682 type=ArmISA
 683 decoderFlavour=Generic
 684 eventq_index=0
 685 fpsid=1090793632
 686 id_aa64afr0_el1=0
 687 id_aa64afr1_el1=0
 688 id_aa64dfr0_el1=1052678
 689 id_aa64dfr1_el1=0
 690 id_aa64isar0_el1=0
 691 id_aa64isar1_el1=0
 692 id_aa64mmfr0_el1=15728642
 693 id_aa64mmfr1_el1=0
 694 id_aa64pfr0_el1=34
 695 id_aa64pfr1_el1=0
 696 id_isar0=34607377
 697 id_isar1=34677009
 698 id_isar2=555950401
 699 id_isar3=17899825
 700 id_isar4=268501314
 701 id_isar5=0
 702 id_mmfr0=270536963
 703 id_mmfr1=0
 704 id_mmfr2=19070976
 705 id_mmfr3=34611729
 706 id_pfr0=49
 707 id_pfr1=4113
 708 midr=1091551472
 709 pmu=Null
 710 system=system
 711
 712 [system.cpu.istage2_mmu]
 713 type=ArmStage2MMU
 714 children=stage2_tlb
 715 eventq_index=0
 716 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 717 sys=system
 718 tlb=system.cpu.itb
 719
 720 [system.cpu.istage2_mmu.stage2_tlb]
 721 type=ArmTLB
 722 children=walker
 723 eventq_index=0
 724 is_stage2=true
 725 size=32
 726 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 727
 728 [system.cpu.istage2_mmu.stage2_tlb.walker]
 729 type=ArmTableWalker
 730 clk_domain=system.cpu_clk_domain
 731 default_p_state=UNDEFINED
 732 eventq_index=0
 733 is_stage2=true
 734 num_squash_per_cycle=2
 735 p_state_clk_gate_bins=20
 736 p_state_clk_gate_max=1000000000000
 737 p_state_clk_gate_min=1000
 738 power_model=Null
 739 sys=system
 740
 741 [system.cpu.itb]
 742 type=ArmTLB
 743 children=walker
 744 eventq_index=0
 745 is_stage2=false
 746 size=64
 747 walker=system.cpu.itb.walker
 748
 749 [system.cpu.itb.walker]
 750 type=ArmTableWalker
 751 clk_domain=system.cpu_clk_domain
 752 default_p_state=UNDEFINED
 753 eventq_index=0
 754 is_stage2=false
 755 num_squash_per_cycle=2
 756 p_state_clk_gate_bins=20
 757 p_state_clk_gate_max=1000000000000
 758 p_state_clk_gate_min=1000
 759 power_model=Null
 760 sys=system
 761 port=system.cpu.toL2Bus.slave[2]
 762
 763 [system.cpu.l2cache]
 764 type=Cache
 765 children=tags
 766 addr_ranges=0:18446744073709551615:0:0:0:0
 767 assoc=8
 768 clk_domain=system.cpu_clk_domain
 769 clusivity=mostly_incl
 770 default_p_state=UNDEFINED
 771 demand_mshr_reserve=1
 772 eventq_index=0
 773 hit_latency=20
 774 is_read_only=false
 775 max_miss_count=0
 776 mshrs=20
 777 p_state_clk_gate_bins=20
 778 p_state_clk_gate_max=1000000000000
 779 p_state_clk_gate_min=1000
 780 power_model=Null
 781 prefetch_on_access=false
 782 prefetcher=Null
 783 response_latency=20
 784 sequential_access=false
 785 size=2097152
 786 system=system
 787 tags=system.cpu.l2cache.tags
 788 tgts_per_mshr=12
 789 write_buffers=8
 790 writeback_clean=false
 791 cpu_side=system.cpu.toL2Bus.master[0]
 792 mem_side=system.membus.slave[1]
 793
 794 [system.cpu.l2cache.tags]
 795 type=LRU
 796 assoc=8
 797 block_size=64
 798 clk_domain=system.cpu_clk_domain
 799 default_p_state=UNDEFINED
 800 eventq_index=0
 801 hit_latency=20
 802 p_state_clk_gate_bins=20
 803 p_state_clk_gate_max=1000000000000
 804 p_state_clk_gate_min=1000
 805 power_model=Null
 806 sequential_access=false
 807 size=2097152
 808
 809 [system.cpu.toL2Bus]
 810 type=CoherentXBar
 811 children=snoop_filter
 812 clk_domain=system.cpu_clk_domain
 813 default_p_state=UNDEFINED
 814 eventq_index=0
 815 forward_latency=0
 816 frontend_latency=1
 817 p_state_clk_gate_bins=20
 818 p_state_clk_gate_max=1000000000000
 819 p_state_clk_gate_min=1000
 820 point_of_coherency=false
 821 power_model=Null
 822 response_latency=1
 823 snoop_filter=system.cpu.toL2Bus.snoop_filter
 824 snoop_response_latency=1
 825 system=system
 826 use_default_range=false
 827 width=32
 828 master=system.cpu.l2cache.cpu_side
 829 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 830
 831 [system.cpu.toL2Bus.snoop_filter]
 832 type=SnoopFilter
 833 eventq_index=0
 834 lookup_latency=0
 835 max_capacity=8388608
 836 system=system
 837
 838 [system.cpu.tracer]
 839 type=ExeTracer
 840 eventq_index=0
 841
 842 [system.cpu.workload]
 843 type=LiveProcess
 844 cmd=twolf smred
 845 cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
 846 drivers=
 847 egid=100
 848 env=
 849 errout=cerr
 850 euid=100
 851 eventq_index=0
 852 executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
 853 gid=100
 854 input=cin
 855 kvmInSE=false
 856 max_stack_size=67108864
 857 output=cout
 858 pid=100
 859 ppid=99
 860 simpoint=0
 861 system=system
 862 uid=100
 863 useArchPT=false
 864
 865 [system.cpu_clk_domain]
 866 type=SrcClockDomain
 867 clock=500
 868 domain_id=-1
 869 eventq_index=0
 870 init_perf_level=0
 871 voltage_domain=system.voltage_domain
 872
 873 [system.dvfs_handler]
 874 type=DVFSHandler
 875 domains=
 876 enable=false
 877 eventq_index=0
 878 sys_clk_domain=system.clk_domain
 879 transition_latency=100000000
 880
 881 [system.membus]
 882 type=CoherentXBar
 883 children=snoop_filter
 884 clk_domain=system.clk_domain
 885 default_p_state=UNDEFINED
 886 eventq_index=0
 887 forward_latency=4
 888 frontend_latency=3
 889 p_state_clk_gate_bins=20
 890 p_state_clk_gate_max=1000000000000
 891 p_state_clk_gate_min=1000
 892 point_of_coherency=true
 893 power_model=Null
 894 response_latency=2
 895 snoop_filter=system.membus.snoop_filter
 896 snoop_response_latency=4
 897 system=system
 898 use_default_range=false
 899 width=16
 900 master=system.physmem.port
 901 slave=system.system_port system.cpu.l2cache.mem_side
 902
 903 [system.membus.snoop_filter]
 904 type=SnoopFilter
 905 eventq_index=0
 906 lookup_latency=1
 907 max_capacity=8388608
 908 system=system
 909
 910 [system.physmem]
 911 type=DRAMCtrl
 912 IDD0=0.055000
 913 IDD02=0.000000
 914 IDD2N=0.032000
 915 IDD2N2=0.000000
 916 IDD2P0=0.000000
 917 IDD2P02=0.000000
 918 IDD2P1=0.032000
 919 IDD2P12=0.000000
 920 IDD3N=0.038000
 921 IDD3N2=0.000000
 922 IDD3P0=0.000000
 923 IDD3P02=0.000000
 924 IDD3P1=0.038000
 925 IDD3P12=0.000000
 926 IDD4R=0.157000
 927 IDD4R2=0.000000
 928 IDD4W=0.125000
 929 IDD4W2=0.000000
 930 IDD5=0.235000
 931 IDD52=0.000000
 932 IDD6=0.020000
 933 IDD62=0.000000
 934 VDD=1.500000
 935 VDD2=0.000000
 936 activation_limit=4
 937 addr_mapping=RoRaBaCoCh
 938 bank_groups_per_rank=0
 939 banks_per_rank=8
 940 burst_length=8
 941 channels=1
 942 clk_domain=system.clk_domain
 943 conf_table_reported=true
 944 default_p_state=UNDEFINED
 945 device_bus_width=8
 946 device_rowbuffer_size=1024
 947 device_size=536870912
 948 devices_per_rank=8
 949 dll=true
 950 eventq_index=0
 951 in_addr_map=true
 952 kvm_map=true
 953 max_accesses_per_row=16
 954 mem_sched_policy=frfcfs
 955 min_writes_per_switch=16
 956 null=false
 957 p_state_clk_gate_bins=20
 958 p_state_clk_gate_max=1000000000000
 959 p_state_clk_gate_min=1000
 960 page_policy=open_adaptive
 961 power_model=Null
 962 range=0:134217727:0:0:0:0
 963 ranks_per_channel=2
 964 read_buffer_size=32
 965 static_backend_latency=10000
 966 static_frontend_latency=10000
 967 tBURST=5000
 968 tCCD_L=0
 969 tCK=1250
 970 tCL=13750
 971 tCS=2500
 972 tRAS=35000
 973 tRCD=13750
 974 tREFI=7800000
 975 tRFC=260000
 976 tRP=13750
 977 tRRD=6000
 978 tRRD_L=0
 979 tRTP=7500
 980 tRTW=2500
 981 tWR=15000
 982 tWTR=7500
 983 tXAW=30000
 984 tXP=6000
 985 tXPDLL=0
 986 tXS=270000
 987 tXSDLL=0
 988 write_buffer_size=64
 989 write_high_thresh_perc=85
 990 write_low_thresh_perc=50
 991 port=system.membus.master[0]
 992
 993 [system.voltage_domain]
 994 type=VoltageDomain
 995 eventq_index=0
 996 voltage=1.000000
 997