tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats

   1
   2 ================ Begin RubySystem Configuration Print ================
   3
   4 Ruby Configuration
   5 ------------------
   6 protocol: MOSI_SMP_bcast
   7 compiled_at: 22:54:24, May  4 2009
   8 RUBY_DEBUG: false
   9 hostname: piton
  10 g_RANDOM_SEED: 1
  11 g_DEADLOCK_THRESHOLD: 500000
  12 RANDOMIZATION: false
  13 g_SYNTHETIC_DRIVER: false
  14 g_DETERMINISTIC_DRIVER: false
  15 g_FILTERING_ENABLED: false
  16 g_DISTRIBUTED_PERSISTENT_ENABLED: true
  17 g_DYNAMIC_TIMEOUT_ENABLED: true
  18 g_RETRY_THRESHOLD: 1
  19 g_FIXED_TIMEOUT_LATENCY: 300
  20 g_trace_warmup_length: 1000000
  21 g_bash_bandwidth_adaptive_threshold: 0.75
  22 g_tester_length: 0
  23 g_synthetic_locks: 2048
  24 g_deterministic_addrs: 1
  25 g_SpecifiedGenerator: DetermInvGenerator
  26 g_callback_counter: 0
  27 g_NUM_COMPLETIONS_BEFORE_PASS: 0
  28 g_NUM_SMT_THREADS: 1
  29 g_think_time: 5
  30 g_hold_time: 5
  31 g_wait_time: 5
  32 PROTOCOL_DEBUG_TRACE: true
  33 DEBUG_FILTER_STRING: none
  34 DEBUG_VERBOSITY_STRING: none
  35 DEBUG_START_TIME: 0
  36 DEBUG_OUTPUT_FILENAME: none
  37 SIMICS_RUBY_MULTIPLIER: 4
  38 OPAL_RUBY_MULTIPLIER: 1
  39 TRANSACTION_TRACE_ENABLED: false
  40 USER_MODE_DATA_ONLY: false
  41 PROFILE_HOT_LINES: false
  42 PROFILE_ALL_INSTRUCTIONS: false
  43 PRINT_INSTRUCTION_TRACE: false
  44 g_DEBUG_CYCLE: 0
  45 BLOCK_STC: false
  46 PERFECT_MEMORY_SYSTEM: false
  47 PERFECT_MEMORY_SYSTEM_LATENCY: 0
  48 DATA_BLOCK: false
  49 REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
  50 L1_CACHE_ASSOC: 4
  51 L1_CACHE_NUM_SETS_BITS: 8
  52 L2_CACHE_ASSOC: 4
  53 L2_CACHE_NUM_SETS_BITS: 16
  54 g_MEMORY_SIZE_BYTES: 4294967296
  55 g_DATA_BLOCK_BYTES: 64
  56 g_PAGE_SIZE_BYTES: 4096
  57 g_REPLACEMENT_POLICY: PSEDUO_LRU
  58 g_NUM_PROCESSORS: 4
  59 g_NUM_L2_BANKS: 4
  60 g_NUM_MEMORIES: 4
  61 g_PROCS_PER_CHIP: 1
  62 g_NUM_CHIPS: 4
  63 g_NUM_CHIP_BITS: 2
  64 g_MEMORY_SIZE_BITS: 32
  65 g_DATA_BLOCK_BITS: 6
  66 g_PAGE_SIZE_BITS: 12
  67 g_NUM_PROCESSORS_BITS: 2
  68 g_PROCS_PER_CHIP_BITS: 0
  69 g_NUM_L2_BANKS_BITS: 2
  70 g_NUM_L2_BANKS_PER_CHIP_BITS: 0
  71 g_NUM_L2_BANKS_PER_CHIP: 1
  72 g_NUM_MEMORIES_BITS: 2
  73 g_NUM_MEMORIES_PER_CHIP: 1
  74 g_MEMORY_MODULE_BITS: 24
  75 g_MEMORY_MODULE_BLOCKS: 16777216
  76 MAP_L2BANKS_TO_LOWEST_BITS: false
  77 DIRECTORY_CACHE_LATENCY: 6
  78 NULL_LATENCY: 1
  79 ISSUE_LATENCY: 2
  80 CACHE_RESPONSE_LATENCY: 12
  81 L2_RESPONSE_LATENCY: 6
  82 L2_TAG_LATENCY: 6
  83 L1_RESPONSE_LATENCY: 3
  84 MEMORY_RESPONSE_LATENCY_MINUS_2: 158
  85 DIRECTORY_LATENCY: 80
  86 NETWORK_LINK_LATENCY: 1
  87 COPY_HEAD_LATENCY: 4
  88 ON_CHIP_LINK_LATENCY: 1
  89 RECYCLE_LATENCY: 10
  90 L2_RECYCLE_LATENCY: 5
  91 TIMER_LATENCY: 10000
  92 TBE_RESPONSE_LATENCY: 1
  93 PERIODIC_TIMER_WAKEUPS: true
  94 PROFILE_EXCEPTIONS: false
  95 PROFILE_XACT: true
  96 PROFILE_NONXACT: false
  97 XACT_DEBUG: true
  98 XACT_DEBUG_LEVEL: 1
  99 XACT_MEMORY: false
 100 XACT_ENABLE_TOURMALINE: false
 101 XACT_NUM_CURRENT: 0
 102 XACT_LAST_UPDATE: 0
 103 XACT_ISOLATION_CHECK: false
 104 PERFECT_FILTER: true
 105 READ_WRITE_FILTER: Perfect_
 106 PERFECT_VIRTUAL_FILTER: true
 107 VIRTUAL_READ_WRITE_FILTER: Perfect_
 108 PERFECT_SUMMARY_FILTER: true
 109 SUMMARY_READ_WRITE_FILTER: Perfect_
 110 XACT_EAGER_CD: true
 111 XACT_LAZY_VM: false
 112 XACT_CONFLICT_RES: BASE
 113 XACT_VISUALIZER: false
 114 XACT_COMMIT_TOKEN_LATENCY: 0
 115 XACT_NO_BACKOFF: false
 116 XACT_LOG_BUFFER_SIZE: 0
 117 XACT_STORE_PREDICTOR_HISTORY: 256
 118 XACT_STORE_PREDICTOR_ENTRIES: 256
 119 XACT_STORE_PREDICTOR_THRESHOLD: 4
 120 XACT_FIRST_ACCESS_COST: 0
 121 XACT_FIRST_PAGE_ACCESS_COST: 0
 122 ENABLE_MAGIC_WAITING: false
 123 ENABLE_WATCHPOINT: false
 124 XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
 125 ATMTP_ENABLED: false
 126 ATMTP_ABORT_ON_NON_XACT_INST: false
 127 ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
 128 ATMTP_XACT_MAX_STORES: 32
 129 ATMTP_DEBUG_LEVEL: 0
 130 L1_REQUEST_LATENCY: 2
 131 L2_REQUEST_LATENCY: 4
 132 SINGLE_ACCESS_L2_BANKS: true
 133 SEQUENCER_TO_CONTROLLER_LATENCY: 4
 134 L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
 135 L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
 136 DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
 137 g_SEQUENCER_OUTSTANDING_REQUESTS: 16
 138 NUMBER_OF_TBES: 128
 139 NUMBER_OF_L1_TBES: 32
 140 NUMBER_OF_L2_TBES: 32
 141 FINITE_BUFFERING: false
 142 FINITE_BUFFER_SIZE: 3
 143 PROCESSOR_BUFFER_SIZE: 10
 144 PROTOCOL_BUFFER_SIZE: 32
 145 TSO: false
 146 g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
 147 g_CACHE_DESIGN: NUCA
 148 g_endpoint_bandwidth: 10000
 149 g_adaptive_routing: true
 150 NUMBER_OF_VIRTUAL_NETWORKS: 4
 151 FAN_OUT_DEGREE: 4
 152 g_PRINT_TOPOLOGY: true
 153 XACT_LENGTH: 0
 154 XACT_SIZE: 0
 155 ABORT_RETRY_TIME: 0
 156 g_GARNET_NETWORK: false
 157 g_DETAIL_NETWORK: false
 158 g_NETWORK_TESTING: false
 159 g_FLIT_SIZE: 16
 160 g_NUM_PIPE_STAGES: 4
 161 g_VCS_PER_CLASS: 4
 162 g_BUFFER_SIZE: 4
 163 MEM_BUS_CYCLE_MULTIPLIER: 10
 164 BANKS_PER_RANK: 8
 165 RANKS_PER_DIMM: 2
 166 DIMMS_PER_CHANNEL: 2
 167 BANK_BIT_0: 8
 168 RANK_BIT_0: 11
 169 DIMM_BIT_0: 12
 170 BANK_QUEUE_SIZE: 12
 171 BANK_BUSY_TIME: 11
 172 RANK_RANK_DELAY: 1
 173 READ_WRITE_DELAY: 2
 174 BASIC_BUS_BUSY_TIME: 2
 175 MEM_CTL_LATENCY: 12
 176 REFRESH_PERIOD: 1560
 177 TFAW: 0
 178 MEM_RANDOM_ARBITRATE: 0
 179 MEM_FIXED_DELAY: 0
 180
 181 Chip Config
 182 -----------
 183 Total_Chips: 4
 184
 185 L1Cache_TBEs numberPerChip: 1
 186 TBEs_per_TBETable: 128
 187
 188 L1Cache_L1IcacheMemory numberPerChip: 1
 189 Cache config: L1Cache_0_L1I
 190   cache_associativity: 4
 191   num_cache_sets_bits: 8
 192   num_cache_sets: 256
 193   cache_set_size_bytes: 16384
 194   cache_set_size_Kbytes: 16
 195   cache_set_size_Mbytes: 0.015625
 196   cache_size_bytes: 65536
 197   cache_size_Kbytes: 64
 198   cache_size_Mbytes: 0.0625
 199
 200 L1Cache_L1DcacheMemory numberPerChip: 1
 201 Cache config: L1Cache_0_L1D
 202   cache_associativity: 4
 203   num_cache_sets_bits: 8
 204   num_cache_sets: 256
 205   cache_set_size_bytes: 16384
 206   cache_set_size_Kbytes: 16
 207   cache_set_size_Mbytes: 0.015625
 208   cache_size_bytes: 65536
 209   cache_size_Kbytes: 64
 210   cache_size_Mbytes: 0.0625
 211
 212 L1Cache_L2cacheMemory numberPerChip: 1
 213 Cache config: L1Cache_0_L2
 214   cache_associativity: 4
 215   num_cache_sets_bits: 16
 216   num_cache_sets: 65536
 217   cache_set_size_bytes: 4194304
 218   cache_set_size_Kbytes: 4096
 219   cache_set_size_Mbytes: 4
 220   cache_size_bytes: 16777216
 221   cache_size_Kbytes: 16384
 222   cache_size_Mbytes: 16
 223
 224 L1Cache_mandatoryQueue numberPerChip: 1
 225
 226 L1Cache_sequencer numberPerChip: 1
 227 sequencer: Sequencer - SC
 228   max_outstanding_requests: 16
 229
 230 L1Cache_storeBuffer numberPerChip: 1
 231 Store buffer entries: 128 (Only valid if TSO is enabled)
 232
 233 Directory_directory numberPerChip: 1
 234 Memory config:
 235   memory_bits: 32
 236   memory_size_bytes: 4294967296
 237   memory_size_Kbytes: 4.1943e+06
 238   memory_size_Mbytes: 4096
 239   memory_size_Gbytes: 4
 240   module_bits: 24
 241   module_size_lines: 16777216
 242   module_size_bytes: 1073741824
 243   module_size_Kbytes: 1.04858e+06
 244   module_size_Mbytes: 1024
 245
 246
 247 Network Configuration
 248 ---------------------
 249 network: SIMPLE_NETWORK
 250 topology: HIERARCHICAL_SWITCH
 251
 252 virtual_net_0: active, ordered
 253 virtual_net_1: active, unordered
 254 virtual_net_2: inactive
 255 virtual_net_3: inactive
 256
 257 --- Begin Topology Print ---
 258
 259 Topology print ONLY indicates the _NETWORK_ latency between two machines
 260 It does NOT include the latency within the machines
 261
 262 L1Cache-0 Network Latencies
 263   L1Cache-0 -> L1Cache-1 net_lat: 9
 264   L1Cache-0 -> L1Cache-2 net_lat: 9
 265   L1Cache-0 -> L1Cache-3 net_lat: 9
 266   L1Cache-0 -> Directory-0 net_lat: 9
 267   L1Cache-0 -> Directory-1 net_lat: 9
 268   L1Cache-0 -> Directory-2 net_lat: 9
 269   L1Cache-0 -> Directory-3 net_lat: 9
 270
 271 L1Cache-1 Network Latencies
 272   L1Cache-1 -> L1Cache-0 net_lat: 9
 273   L1Cache-1 -> L1Cache-2 net_lat: 9
 274   L1Cache-1 -> L1Cache-3 net_lat: 9
 275   L1Cache-1 -> Directory-0 net_lat: 9
 276   L1Cache-1 -> Directory-1 net_lat: 9
 277   L1Cache-1 -> Directory-2 net_lat: 9
 278   L1Cache-1 -> Directory-3 net_lat: 9
 279
 280 L1Cache-2 Network Latencies
 281   L1Cache-2 -> L1Cache-0 net_lat: 9
 282   L1Cache-2 -> L1Cache-1 net_lat: 9
 283   L1Cache-2 -> L1Cache-3 net_lat: 9
 284   L1Cache-2 -> Directory-0 net_lat: 9
 285   L1Cache-2 -> Directory-1 net_lat: 9
 286   L1Cache-2 -> Directory-2 net_lat: 9
 287   L1Cache-2 -> Directory-3 net_lat: 9
 288
 289 L1Cache-3 Network Latencies
 290   L1Cache-3 -> L1Cache-0 net_lat: 9
 291   L1Cache-3 -> L1Cache-1 net_lat: 9
 292   L1Cache-3 -> L1Cache-2 net_lat: 9
 293   L1Cache-3 -> Directory-0 net_lat: 9
 294   L1Cache-3 -> Directory-1 net_lat: 9
 295   L1Cache-3 -> Directory-2 net_lat: 9
 296   L1Cache-3 -> Directory-3 net_lat: 9
 297
 298 Directory-0 Network Latencies
 299   Directory-0 -> L1Cache-0 net_lat: 9
 300   Directory-0 -> L1Cache-1 net_lat: 9
 301   Directory-0 -> L1Cache-2 net_lat: 9
 302   Directory-0 -> L1Cache-3 net_lat: 9
 303   Directory-0 -> Directory-1 net_lat: 9
 304   Directory-0 -> Directory-2 net_lat: 9
 305   Directory-0 -> Directory-3 net_lat: 9
 306
 307 Directory-1 Network Latencies
 308   Directory-1 -> L1Cache-0 net_lat: 9
 309   Directory-1 -> L1Cache-1 net_lat: 9
 310   Directory-1 -> L1Cache-2 net_lat: 9
 311   Directory-1 -> L1Cache-3 net_lat: 9
 312   Directory-1 -> Directory-0 net_lat: 9
 313   Directory-1 -> Directory-2 net_lat: 9
 314   Directory-1 -> Directory-3 net_lat: 9
 315
 316 Directory-2 Network Latencies
 317   Directory-2 -> L1Cache-0 net_lat: 9
 318   Directory-2 -> L1Cache-1 net_lat: 9
 319   Directory-2 -> L1Cache-2 net_lat: 9
 320   Directory-2 -> L1Cache-3 net_lat: 9
 321   Directory-2 -> Directory-0 net_lat: 9
 322   Directory-2 -> Directory-1 net_lat: 9
 323   Directory-2 -> Directory-3 net_lat: 9
 324
 325 Directory-3 Network Latencies
 326   Directory-3 -> L1Cache-0 net_lat: 9
 327   Directory-3 -> L1Cache-1 net_lat: 9
 328   Directory-3 -> L1Cache-2 net_lat: 9
 329   Directory-3 -> L1Cache-3 net_lat: 9
 330   Directory-3 -> Directory-0 net_lat: 9
 331   Directory-3 -> Directory-1 net_lat: 9
 332   Directory-3 -> Directory-2 net_lat: 9
 333
 334 --- End Topology Print ---
 335
 336 Profiler Configuration
 337 ----------------------
 338 periodic_stats_period: 1000000
 339
 340 ================ End RubySystem Configuration Print ================
 341
 342
 343 Real time: May/05/2009 07:34:42
 344
 345 Profiler Stats
 346 --------------
 347 Elapsed_time_in_seconds: 40
 348 Elapsed_time_in_minutes: 0.666667
 349 Elapsed_time_in_hours: 0.0111111
 350 Elapsed_time_in_days: 0.000462963
 351
 352 Virtual_time_in_seconds: 37.33
 353 Virtual_time_in_minutes: 0.622167
 354 Virtual_time_in_hours:   0.0103694
 355 Virtual_time_in_days:    0.0103694
 356
 357 Ruby_current_time: 2480212001
 358 Ruby_start_time: 1
 359 Ruby_cycles: 2480212000
 360
 361 mbytes_resident: 90.6484
 362 mbytes_total: 252.043
 363 resident_ratio: 0.35967
 364
 365 Total_misses: 1949
 366 total_misses: 1949 [ 424 409 702 414 ]
 367 user_misses: 1949 [ 424 409 702 414 ]
 368 supervisor_misses: 0 [ 0 0 0 0 ]
 369
 370 instruction_executed: 4 [ 1 1 1 1 ]
 371 cycles_executed: 4 [ 1 1 1 1 ]
 372 cycles_per_instruction: 2.48021e+09 [ 2.48021e+09 2.48021e+09 2.48021e+09 2.48021e+09 ]
 373 misses_per_thousand_instructions: 487250 [ 424000 409000 702000 414000 ]
 374
 375 transactions_started: 0 [ 0 0 0 0 ]
 376 transactions_ended: 0 [ 0 0 0 0 ]
 377 instructions_per_transaction: 0 [ 0 0 0 0 ]
 378 cycles_per_transaction: 0 [ 0 0 0 0 ]
 379 misses_per_transaction: 0 [ 0 0 0 0 ]
 380
 381 L1D_cache cache stats:
 382   L1D_cache_total_misses: 1340
 383   L1D_cache_total_demand_misses: 1340
 384   L1D_cache_total_prefetches: 0
 385   L1D_cache_total_sw_prefetches: 0
 386   L1D_cache_total_hw_prefetches: 0
 387   L1D_cache_misses_per_transaction: 1340
 388   L1D_cache_misses_per_instruction: 1340
 389   L1D_cache_instructions_per_misses: 0.000746269
 390
 391   L1D_cache_request_type_LD:   47.4627%
 392   L1D_cache_request_type_ST:   38.0597%
 393   L1D_cache_request_type_ATOMIC:   14.4776%
 394
 395   L1D_cache_access_mode_type_UserMode:   1340    100%
 396   L1D_cache_request_size: [binsize: log2 max: 8 count: 1340 average: 3.48881 | standard deviation: 2.44812 | 0 527 4 583 226 ]
 397
 398 L1I_cache cache stats:
 399   L1I_cache_total_misses: 610
 400   L1I_cache_total_demand_misses: 610
 401   L1I_cache_total_prefetches: 0
 402   L1I_cache_total_sw_prefetches: 0
 403   L1I_cache_total_hw_prefetches: 0
 404   L1I_cache_misses_per_transaction: 610
 405   L1I_cache_misses_per_instruction: 610
 406   L1I_cache_instructions_per_misses: 0.00163934
 407
 408   L1I_cache_request_type_IFETCH:   100%
 409
 410   L1I_cache_access_mode_type_UserMode:   610    100%
 411   L1I_cache_request_size: [binsize: log2 max: 4 count: 610 average:     4 | standard deviation: 0 | 0 0 0 610 ]
 412
 413 L2_cache cache stats:
 414   L2_cache_total_misses: 1949
 415   L2_cache_total_demand_misses: 1949
 416   L2_cache_total_prefetches: 0
 417   L2_cache_total_sw_prefetches: 0
 418   L2_cache_total_hw_prefetches: 0
 419   L2_cache_misses_per_transaction: 1949
 420   L2_cache_misses_per_instruction: 1949
 421   L2_cache_instructions_per_misses: 0.000513084
 422
 423   L2_cache_request_type_LD:   32.6321%
 424   L2_cache_request_type_ST:   26.1673%
 425   L2_cache_request_type_ATOMIC:   9.95382%
 426   L2_cache_request_type_IFETCH:   31.2468%
 427
 428   L2_cache_access_mode_type_UserMode:   1949    100%
 429   L2_cache_request_size: [binsize: log2 max: 8 count: 1949 average: 3.64854 | standard deviation: 2.04355 | 0 527 4 1192 226 ]
 430
 431
 432 Busy Controller Counts:
 433 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0
 434 Directory-0:0  Directory-1:0  Directory-2:0  Directory-3:0
 435
 436 Busy Bank Count:0
 437
 438 L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 439 L2TBE_usage: [binsize: 1 max: 0 count: 1949 average:     0 | standard deviation: 0 | 1949 ]
 440 StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 441 sequencer_requests_outstanding: [binsize: 1 max: 1 count: 1950 average:     1 | standard deviation: 0 | 0 1950 ]
 442 store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 443 unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 444
 445 All Non-Zero Cycle Demand Cache Accesses
 446 ----------------------------------------
 447 miss_latency: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ]
 448 miss_latency_LD: [binsize: 1 max: 184 count: 636 average: 57.2925 | standard deviation: 53.9711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 536 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 19 26 17 23 ]
 449 miss_latency_ST: [binsize: 1 max: 184 count: 510 average: 73.749 | standard deviation: 69.6824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 27 26 19 42 ]
 450 miss_latency_ATOMIC: [binsize: 1 max: 183 count: 194 average: 37.7887 | standard deviation: 23.3543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 0 1 ]
 451 miss_latency_IFETCH: [binsize: 1 max: 184 count: 610 average: 181.728 | standard deviation: 7.34165 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113 125 131 117 123 ]
 452 miss_latency_NULL: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ]
 453 miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 454
 455 All Non-Zero Cycle SW Prefetch Requests
 456 ------------------------------------
 457 prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 458 prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 459 multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 460 gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 461 getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 462 explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 463
 464 conflicting_histogram: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 6 7 6 10 37 57 33 164 243 38 123 210 142 218 449 203 ]
 465 conflicting_histogram_percent: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 0.0513084 0 0 0 0 0 0 0 0 0 0 0.0513084 0 0.0513084 0.30785 0.359159 0.30785 0.513084 1.89841 2.92458 1.69318 8.41457 12.4679 1.94972 6.31093 10.7748 7.28579 11.1852 23.0375 10.4156 ]
 466
 467 Request vs. RubySystem State Profile
 468 --------------------------------
 469
 470          I         M      GETS        310       15.9056
 471          I         M      GETX        216       11.0826
 472          I        OS      GETS        142       7.28579
 473          I        OS      GETX         33       1.69318
 474          I       OSS      GETS         54       2.77065
 475          I       OSS      GETX         15      0.769625
 476         NP         C      GETS         75       3.84813
 477         NP         C      GETX        136       6.97794
 478         NP         C GET_INSTR        348       17.8553
 479         NP         M      GETS         17      0.872242
 480         NP         M      GETX         11      0.564392
 481         NP        OS      GETS          6       0.30785
 482         NP       OSS      GETS          7      0.359159
 483         NP         S      GETS          9      0.461775
 484         NP         S GET_INSTR         93       4.77168
 485         NP        SS      GETS         16      0.820934
 486         NP        SS GET_INSTR        168       8.61981
 487          O        OS      GETX         22       1.12878
 488          O       OSS      GETX         60        3.0785
 489          S        OS      GETX        124       6.36224
 490          S       OSS      GETX         70       3.59159
 491          S         S      GETX         17      0.872242
 492
 493 filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 494
 495 Message Delayed Cycles
 496 ----------------------
 497 Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 498 Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 499   virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 500   virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 501   virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 502   virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 503
 504 Resource Usage
 505 --------------
 506 page_size: 4096
 507 user_time: 37
 508 system_time: 0
 509 page_reclaims: 23404
 510 page_faults: 0
 511 swaps: 0
 512 block_inputs: 0
 513 block_outputs: 656
 514 MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:424 full:0
 515 MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:409 full:0
 516 MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:703 full:0
 517 MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:414 full:0
 518
 519 Network Stats
 520 -------------
 521
 522 switch_0_inlinks: 1
 523 switch_0_outlinks: 1
 524 links_utilized_percent_switch_0: 8.82828e-05
 525   links_utilized_percent_switch_0_link_0: 8.82828e-05 bw: 10000 base_latency: 1
 526
 527   outgoing_messages_switch_0_link_0_Control: 424 3392 [ 424 0 0 0 ] base_latency: 1
 528   outgoing_messages_switch_0_link_0_Data: 257 18504 [ 0 257 0 0 ] base_latency: 1
 529
 530 switch_1_inlinks: 1
 531 switch_1_outlinks: 1
 532 links_utilized_percent_switch_1: 8.92504e-05
 533   links_utilized_percent_switch_1_link_0: 8.92504e-05 bw: 10000 base_latency: 1
 534
 535   outgoing_messages_switch_1_link_0_Control: 409 3272 [ 409 0 0 0 ] base_latency: 1
 536   outgoing_messages_switch_1_link_0_Data: 262 18864 [ 0 262 0 0 ] base_latency: 1
 537
 538 switch_2_inlinks: 1
 539 switch_2_outlinks: 1
 540 links_utilized_percent_switch_2: 8.94117e-05
 541   links_utilized_percent_switch_2_link_0: 8.94117e-05 bw: 10000 base_latency: 1
 542
 543   outgoing_messages_switch_2_link_0_Control: 702 5616 [ 702 0 0 0 ] base_latency: 1
 544   outgoing_messages_switch_2_link_0_Data: 230 16560 [ 0 230 0 0 ] base_latency: 1
 545
 546 switch_3_inlinks: 1
 547 switch_3_outlinks: 1
 548 links_utilized_percent_switch_3: 8.76699e-05
 549   links_utilized_percent_switch_3_link_0: 8.76699e-05 bw: 10000 base_latency: 1
 550
 551   outgoing_messages_switch_3_link_0_Control: 414 3312 [ 414 0 0 0 ] base_latency: 1
 552   outgoing_messages_switch_3_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1
 553
 554 switch_4_inlinks: 1
 555 switch_4_outlinks: 1
 556 links_utilized_percent_switch_4: 6.76394e-05
 557   links_utilized_percent_switch_4_link_0: 6.76394e-05 bw: 10000 base_latency: 1
 558
 559   outgoing_messages_switch_4_link_0_Data: 233 16776 [ 0 233 0 0 ] base_latency: 1
 560
 561 switch_5_inlinks: 1
 562 switch_5_outlinks: 1
 563 links_utilized_percent_switch_5: 6.21237e-05
 564   links_utilized_percent_switch_5_link_0: 6.21237e-05 bw: 10000 base_latency: 1
 565
 566   outgoing_messages_switch_5_link_0_Data: 214 15408 [ 0 214 0 0 ] base_latency: 1
 567
 568 switch_6_inlinks: 1
 569 switch_6_outlinks: 1
 570 links_utilized_percent_switch_6: 5.9511e-05
 571   links_utilized_percent_switch_6_link_0: 5.9511e-05 bw: 10000 base_latency: 1
 572
 573   outgoing_messages_switch_6_link_0_Data: 205 14760 [ 0 205 0 0 ] base_latency: 1
 574
 575 switch_7_inlinks: 1
 576 switch_7_outlinks: 1
 577 links_utilized_percent_switch_7: 6.09625e-05
 578   links_utilized_percent_switch_7_link_0: 6.09625e-05 bw: 10000 base_latency: 1
 579
 580   outgoing_messages_switch_7_link_0_Data: 210 15120 [ 0 210 0 0 ] base_latency: 1
 581
 582 switch_8_inlinks: 4
 583 switch_8_outlinks: 1
 584 links_utilized_percent_switch_8: 0.000354615
 585   links_utilized_percent_switch_8_link_0: 0.000354615 bw: 10000 base_latency: 1
 586
 587   outgoing_messages_switch_8_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 588   outgoing_messages_switch_8_link_0_Data: 1005 72360 [ 0 1005 0 0 ] base_latency: 1
 589
 590 switch_9_inlinks: 4
 591 switch_9_outlinks: 1
 592 links_utilized_percent_switch_9: 0.000250237
 593   links_utilized_percent_switch_9_link_0: 0.000250237 bw: 10000 base_latency: 1
 594
 595   outgoing_messages_switch_9_link_0_Data: 862 62064 [ 0 862 0 0 ] base_latency: 1
 596
 597 switch_10_inlinks: 2
 598 switch_10_outlinks: 2
 599 links_utilized_percent_switch_10: 0.000333859
 600   links_utilized_percent_switch_10_link_0: 0.000604852 bw: 10000 base_latency: 1
 601   links_utilized_percent_switch_10_link_1: 6.28656e-05 bw: 10000 base_latency: 1
 602
 603   outgoing_messages_switch_10_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 604   outgoing_messages_switch_10_link_0_Data: 1867 134424 [ 0 1867 0 0 ] base_latency: 1
 605   outgoing_messages_switch_10_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 606
 607 switch_11_inlinks: 1
 608 switch_11_outlinks: 4
 609 links_utilized_percent_switch_11: 0.000198362
 610   links_utilized_percent_switch_11_link_0: 0.000181597 bw: 10000 base_latency: 1
 611   links_utilized_percent_switch_11_link_1: 0.000176082 bw: 10000 base_latency: 1
 612   links_utilized_percent_switch_11_link_2: 0.000257655 bw: 10000 base_latency: 1
 613   links_utilized_percent_switch_11_link_3: 0.000178114 bw: 10000 base_latency: 1
 614
 615   outgoing_messages_switch_11_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 616   outgoing_messages_switch_11_link_0_Data: 409 29448 [ 0 409 0 0 ] base_latency: 1
 617   outgoing_messages_switch_11_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 618   outgoing_messages_switch_11_link_1_Data: 390 28080 [ 0 390 0 0 ] base_latency: 1
 619   outgoing_messages_switch_11_link_2_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 620   outgoing_messages_switch_11_link_2_Data: 671 48312 [ 0 671 0 0 ] base_latency: 1
 621   outgoing_messages_switch_11_link_3_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
 622   outgoing_messages_switch_11_link_3_Data: 397 28584 [ 0 397 0 0 ] base_latency: 1
 623
 624 switch_12_inlinks: 1
 625 switch_12_outlinks: 4
 626 links_utilized_percent_switch_12: 1.57164e-05
 627   links_utilized_percent_switch_12_link_0: 2.37399e-05 bw: 10000 base_latency: 1
 628   links_utilized_percent_switch_12_link_1: 1.05475e-05 bw: 10000 base_latency: 1
 629   links_utilized_percent_switch_12_link_2: 6.87038e-06 bw: 10000 base_latency: 1
 630   links_utilized_percent_switch_12_link_3: 2.17078e-05 bw: 10000 base_latency: 1
 631
 632   outgoing_messages_switch_12_link_0_Control: 736 5888 [ 736 0 0 0 ] base_latency: 1
 633   outgoing_messages_switch_12_link_1_Control: 327 2616 [ 327 0 0 0 ] base_latency: 1
 634   outgoing_messages_switch_12_link_2_Control: 213 1704 [ 213 0 0 0 ] base_latency: 1
 635   outgoing_messages_switch_12_link_3_Control: 673 5384 [ 673 0 0 0 ] base_latency: 1
 636
 637
 638 Chip Stats
 639 ----------
 640
 641  --- L1Cache ---
 642  - Event Counts -
 643 Load  636
 644 Ifetch  610
 645 Store  704
 646 L1_to_L2  3
 647 L2_to_L1D  0
 648 L2_to_L1I  1
 649 L2_Replacement  0
 650 Own_GETS  636
 651 Own_GET_INSTR  609
 652 Own_GETX  704
 653 Own_PUTX  0
 654 Other_GETS  1908
 655 Other_GET_INSTR  1827
 656 Other_GETX  2112
 657 Other_PUTX  0
 658 Data  1867
 659
 660  - Transitions -
 661 NP  Load  130
 662 NP  Ifetch  609
 663 NP  Store  147
 664 NP  Other_GETS  289
 665 NP  Other_GET_INSTR  1323
 666 NP  Other_GETX  514
 667 NP  Other_PUTX  0 <--
 668
 669 I  Load  506
 670 I  Ifetch  0 <--
 671 I  Store  264
 672 I  L1_to_L2  0 <--
 673 I  L2_to_L1D  0 <--
 674 I  L2_to_L1I  0 <--
 675 I  L2_Replacement  0 <--
 676 I  Other_GETS  765
 677 I  Other_GET_INSTR  0 <--
 678 I  Other_GETX  796
 679 I  Other_PUTX  0 <--
 680
 681 S  Load  0 <--
 682 S  Ifetch  1
 683 S  Store  211
 684 S  L1_to_L2  2
 685 S  L2_to_L1D  0 <--
 686 S  L2_to_L1I  1
 687 S  L2_Replacement  0 <--
 688 S  Other_GETS  318
 689 S  Other_GET_INSTR  504
 690 S  Other_GETX  333
 691 S  Other_PUTX  0 <--
 692
 693 O  Load  0 <--
 694 O  Ifetch  0 <--
 695 O  Store  82
 696 O  L1_to_L2  0 <--
 697 O  L2_to_L1D  0 <--
 698 O  L2_to_L1I  0 <--
 699 O  L2_Replacement  0 <--
 700 O  Other_GETS  209
 701 O  Other_GET_INSTR  0 <--
 702 O  Other_GETX  242
 703 O  Other_PUTX  0 <--
 704
 705 M  Load  0 <--
 706 M  Ifetch  0 <--
 707 M  Store  0 <--
 708 M  L1_to_L2  1
 709 M  L2_to_L1D  0 <--
 710 M  L2_to_L1I  0 <--
 711 M  L2_Replacement  0 <--
 712 M  Other_GETS  327
 713 M  Other_GET_INSTR  0 <--
 714 M  Other_GETX  227
 715 M  Other_PUTX  0 <--
 716
 717 IS_AD  Load  0 <--
 718 IS_AD  Ifetch  0 <--
 719 IS_AD  Store  0 <--
 720 IS_AD  L1_to_L2  0 <--
 721 IS_AD  L2_to_L1D  0 <--
 722 IS_AD  L2_to_L1I  0 <--
 723 IS_AD  L2_Replacement  0 <--
 724 IS_AD  Own_GETS  636
 725 IS_AD  Own_GET_INSTR  609
 726 IS_AD  Other_GETS  0 <--
 727 IS_AD  Other_GET_INSTR  0 <--
 728 IS_AD  Other_GETX  0 <--
 729 IS_AD  Other_PUTX  0 <--
 730 IS_AD  Data  0 <--
 731
 732 IM_AD  Load  0 <--
 733 IM_AD  Ifetch  0 <--
 734 IM_AD  Store  0 <--
 735 IM_AD  L1_to_L2  0 <--
 736 IM_AD  L2_to_L1D  0 <--
 737 IM_AD  L2_to_L1I  0 <--
 738 IM_AD  L2_Replacement  0 <--
 739 IM_AD  Own_GETX  411
 740 IM_AD  Other_GETS  0 <--
 741 IM_AD  Other_GET_INSTR  0 <--
 742 IM_AD  Other_GETX  0 <--
 743 IM_AD  Other_PUTX  0 <--
 744 IM_AD  Data  0 <--
 745
 746 SM_AD  Load  0 <--
 747 SM_AD  Ifetch  0 <--
 748 SM_AD  Store  0 <--
 749 SM_AD  L1_to_L2  0 <--
 750 SM_AD  L2_to_L1D  0 <--
 751 SM_AD  L2_to_L1I  0 <--
 752 SM_AD  L2_Replacement  0 <--
 753 SM_AD  Own_GETX  211
 754 SM_AD  Other_GETS  0 <--
 755 SM_AD  Other_GET_INSTR  0 <--
 756 SM_AD  Other_GETX  0 <--
 757 SM_AD  Other_PUTX  0 <--
 758 SM_AD  Data  0 <--
 759
 760 OM_A  Load  0 <--
 761 OM_A  Ifetch  0 <--
 762 OM_A  Store  0 <--
 763 OM_A  L1_to_L2  0 <--
 764 OM_A  L2_to_L1D  0 <--
 765 OM_A  L2_to_L1I  0 <--
 766 OM_A  L2_Replacement  0 <--
 767 OM_A  Own_GETX  82
 768 OM_A  Other_GETS  0 <--
 769 OM_A  Other_GET_INSTR  0 <--
 770 OM_A  Other_GETX  0 <--
 771 OM_A  Other_PUTX  0 <--
 772 OM_A  Data  0 <--
 773
 774 IS_A  Load  0 <--
 775 IS_A  Ifetch  0 <--
 776 IS_A  Store  0 <--
 777 IS_A  L1_to_L2  0 <--
 778 IS_A  L2_to_L1D  0 <--
 779 IS_A  L2_to_L1I  0 <--
 780 IS_A  L2_Replacement  0 <--
 781 IS_A  Own_GETS  0 <--
 782 IS_A  Own_GET_INSTR  0 <--
 783 IS_A  Other_GETS  0 <--
 784 IS_A  Other_GET_INSTR  0 <--
 785 IS_A  Other_GETX  0 <--
 786 IS_A  Other_PUTX  0 <--
 787
 788 IM_A  Load  0 <--
 789 IM_A  Ifetch  0 <--
 790 IM_A  Store  0 <--
 791 IM_A  L1_to_L2  0 <--
 792 IM_A  L2_to_L1D  0 <--
 793 IM_A  L2_to_L1I  0 <--
 794 IM_A  L2_Replacement  0 <--
 795 IM_A  Own_GETX  0 <--
 796 IM_A  Other_GETS  0 <--
 797 IM_A  Other_GET_INSTR  0 <--
 798 IM_A  Other_GETX  0 <--
 799 IM_A  Other_PUTX  0 <--
 800
 801 SM_A  Load  0 <--
 802 SM_A  Ifetch  0 <--
 803 SM_A  Store  0 <--
 804 SM_A  L1_to_L2  0 <--
 805 SM_A  L2_to_L1D  0 <--
 806 SM_A  L2_to_L1I  0 <--
 807 SM_A  L2_Replacement  0 <--
 808 SM_A  Own_GETX  0 <--
 809 SM_A  Other_GETS  0 <--
 810 SM_A  Other_GET_INSTR  0 <--
 811 SM_A  Other_GETX  0 <--
 812 SM_A  Other_PUTX  0 <--
 813
 814 MI_A  Load  0 <--
 815 MI_A  Ifetch  0 <--
 816 MI_A  Store  0 <--
 817 MI_A  L1_to_L2  0 <--
 818 MI_A  L2_to_L1D  0 <--
 819 MI_A  L2_to_L1I  0 <--
 820 MI_A  L2_Replacement  0 <--
 821 MI_A  Own_PUTX  0 <--
 822 MI_A  Other_GETS  0 <--
 823 MI_A  Other_GET_INSTR  0 <--
 824 MI_A  Other_GETX  0 <--
 825 MI_A  Other_PUTX  0 <--
 826
 827 OI_A  Load  0 <--
 828 OI_A  Ifetch  0 <--
 829 OI_A  Store  0 <--
 830 OI_A  L1_to_L2  0 <--
 831 OI_A  L2_to_L1D  0 <--
 832 OI_A  L2_to_L1I  0 <--
 833 OI_A  L2_Replacement  0 <--
 834 OI_A  Own_PUTX  0 <--
 835 OI_A  Other_GETS  0 <--
 836 OI_A  Other_GET_INSTR  0 <--
 837 OI_A  Other_GETX  0 <--
 838 OI_A  Other_PUTX  0 <--
 839
 840 II_A  Load  0 <--
 841 II_A  Ifetch  0 <--
 842 II_A  Store  0 <--
 843 II_A  L1_to_L2  0 <--
 844 II_A  L2_to_L1D  0 <--
 845 II_A  L2_to_L1I  0 <--
 846 II_A  L2_Replacement  0 <--
 847 II_A  Own_PUTX  0 <--
 848 II_A  Other_GETS  0 <--
 849 II_A  Other_GET_INSTR  0 <--
 850 II_A  Other_GETX  0 <--
 851 II_A  Other_PUTX  0 <--
 852
 853 IS_D  Load  0 <--
 854 IS_D  Ifetch  0 <--
 855 IS_D  Store  0 <--
 856 IS_D  L1_to_L2  0 <--
 857 IS_D  L2_to_L1D  0 <--
 858 IS_D  L2_to_L1I  0 <--
 859 IS_D  L2_Replacement  0 <--
 860 IS_D  Other_GETS  0 <--
 861 IS_D  Other_GET_INSTR  0 <--
 862 IS_D  Other_GETX  0 <--
 863 IS_D  Other_PUTX  0 <--
 864 IS_D  Data  1245
 865
 866 IS_D_I  Load  0 <--
 867 IS_D_I  Ifetch  0 <--
 868 IS_D_I  Store  0 <--
 869 IS_D_I  L1_to_L2  0 <--
 870 IS_D_I  L2_to_L1D  0 <--
 871 IS_D_I  L2_to_L1I  0 <--
 872 IS_D_I  L2_Replacement  0 <--
 873 IS_D_I  Other_GETS  0 <--
 874 IS_D_I  Other_GET_INSTR  0 <--
 875 IS_D_I  Other_GETX  0 <--
 876 IS_D_I  Other_PUTX  0 <--
 877 IS_D_I  Data  0 <--
 878
 879 IM_D  Load  0 <--
 880 IM_D  Ifetch  0 <--
 881 IM_D  Store  0 <--
 882 IM_D  L1_to_L2  0 <--
 883 IM_D  L2_to_L1D  0 <--
 884 IM_D  L2_to_L1I  0 <--
 885 IM_D  L2_Replacement  0 <--
 886 IM_D  Other_GETS  0 <--
 887 IM_D  Other_GET_INSTR  0 <--
 888 IM_D  Other_GETX  0 <--
 889 IM_D  Other_PUTX  0 <--
 890 IM_D  Data  411
 891
 892 IM_D_O  Load  0 <--
 893 IM_D_O  Ifetch  0 <--
 894 IM_D_O  Store  0 <--
 895 IM_D_O  L1_to_L2  0 <--
 896 IM_D_O  L2_to_L1D  0 <--
 897 IM_D_O  L2_to_L1I  0 <--
 898 IM_D_O  L2_Replacement  0 <--
 899 IM_D_O  Other_GETS  0 <--
 900 IM_D_O  Other_GET_INSTR  0 <--
 901 IM_D_O  Other_GETX  0 <--
 902 IM_D_O  Other_PUTX  0 <--
 903 IM_D_O  Data  0 <--
 904
 905 IM_D_I  Load  0 <--
 906 IM_D_I  Ifetch  0 <--
 907 IM_D_I  Store  0 <--
 908 IM_D_I  L1_to_L2  0 <--
 909 IM_D_I  L2_to_L1D  0 <--
 910 IM_D_I  L2_to_L1I  0 <--
 911 IM_D_I  L2_Replacement  0 <--
 912 IM_D_I  Other_GETS  0 <--
 913 IM_D_I  Other_GET_INSTR  0 <--
 914 IM_D_I  Other_GETX  0 <--
 915 IM_D_I  Other_PUTX  0 <--
 916 IM_D_I  Data  0 <--
 917
 918 IM_D_OI  Load  0 <--
 919 IM_D_OI  Ifetch  0 <--
 920 IM_D_OI  Store  0 <--
 921 IM_D_OI  L1_to_L2  0 <--
 922 IM_D_OI  L2_to_L1D  0 <--
 923 IM_D_OI  L2_to_L1I  0 <--
 924 IM_D_OI  L2_Replacement  0 <--
 925 IM_D_OI  Other_GETS  0 <--
 926 IM_D_OI  Other_GET_INSTR  0 <--
 927 IM_D_OI  Other_GETX  0 <--
 928 IM_D_OI  Other_PUTX  0 <--
 929 IM_D_OI  Data  0 <--
 930
 931 SM_D  Load  0 <--
 932 SM_D  Ifetch  0 <--
 933 SM_D  Store  0 <--
 934 SM_D  L1_to_L2  0 <--
 935 SM_D  L2_to_L1D  0 <--
 936 SM_D  L2_to_L1I  0 <--
 937 SM_D  L2_Replacement  0 <--
 938 SM_D  Other_GETS  0 <--
 939 SM_D  Other_GET_INSTR  0 <--
 940 SM_D  Other_GETX  0 <--
 941 SM_D  Other_PUTX  0 <--
 942 SM_D  Data  211
 943
 944 SM_D_O  Load  0 <--
 945 SM_D_O  Ifetch  0 <--
 946 SM_D_O  Store  0 <--
 947 SM_D_O  L1_to_L2  0 <--
 948 SM_D_O  L2_to_L1D  0 <--
 949 SM_D_O  L2_to_L1I  0 <--
 950 SM_D_O  L2_Replacement  0 <--
 951 SM_D_O  Other_GETS  0 <--
 952 SM_D_O  Other_GET_INSTR  0 <--
 953 SM_D_O  Other_GETX  0 <--
 954 SM_D_O  Other_PUTX  0 <--
 955 SM_D_O  Data  0 <--
 956
 957  --- Directory ---
 958  - Event Counts -
 959 OtherAddress  0
 960 GETS  636
 961 GET_INSTR  609
 962 GETX  704
 963 PUTX_Owner  0
 964 PUTX_NotOwner  0
 965
 966  - Transitions -
 967 C  OtherAddress  0 <--
 968 C  GETS  75
 969 C  GET_INSTR  348
 970 C  GETX  136
 971
 972 I  GETS  0 <--
 973 I  GET_INSTR  0 <--
 974 I  GETX  0 <--
 975 I  PUTX_NotOwner  0 <--
 976
 977 S  GETS  9
 978 S  GET_INSTR  93
 979 S  GETX  17
 980 S  PUTX_NotOwner  0 <--
 981
 982 SS  GETS  16
 983 SS  GET_INSTR  168
 984 SS  GETX  0 <--
 985 SS  PUTX_NotOwner  0 <--
 986
 987 OS  GETS  148
 988 OS  GET_INSTR  0 <--
 989 OS  GETX  179
 990 OS  PUTX_Owner  0 <--
 991 OS  PUTX_NotOwner  0 <--
 992
 993 OSS  GETS  61
 994 OSS  GET_INSTR  0 <--
 995 OSS  GETX  145
 996 OSS  PUTX_Owner  0 <--
 997 OSS  PUTX_NotOwner  0 <--
 998
 999 M  GETS  327
1000 M  GET_INSTR  0 <--
1001 M  GETX  227
1002 M  PUTX_Owner  0 <--
1003 M  PUTX_NotOwner  0 <--
1004