tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 time_sync_enable=false
   5 time_sync_period=100000000000
   6 time_sync_spin_threshold=100000000
   7
   8 [system]
   9 type=System
  10 children=cpu membus physmem
  11 mem_mode=atomic
  12 memories=system.physmem
  13 num_work_ids=16
  14 physmem=system.physmem
  15 work_begin_ckpt_count=0
  16 work_begin_cpu_id_exit=-1
  17 work_begin_exit_count=0
  18 work_cpus_ckpt_count=0
  19 work_end_ckpt_count=0
  20 work_end_exit_count=0
  21 work_item_id=-1
  22 system_port=system.membus.port[0]
  23
  24 [system.cpu]
  25 type=DerivO3CPU
  26 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
  27 BTBEntries=4096
  28 BTBTagSize=16
  29 LFSTSize=1024
  30 LQEntries=32
  31 LSQCheckLoads=true
  32 LSQDepCheckShift=4
  33 RASSize=16
  34 SQEntries=32
  35 SSITSize=1024
  36 activity=0
  37 backComSize=5
  38 cachePorts=200
  39 checker=Null
  40 choiceCtrBits=2
  41 choicePredictorSize=8192
  42 clock=500
  43 commitToDecodeDelay=1
  44 commitToFetchDelay=1
  45 commitToIEWDelay=1
  46 commitToRenameDelay=1
  47 commitWidth=8
  48 cpu_id=0
  49 decodeToFetchDelay=1
  50 decodeToRenameDelay=1
  51 decodeWidth=8
  52 defer_registration=false
  53 dispatchWidth=8
  54 do_checkpoint_insts=true
  55 do_statistics_insts=true
  56 dtb=system.cpu.dtb
  57 fetchToDecodeDelay=1
  58 fetchTrapLatency=1
  59 fetchWidth=8
  60 forwardComSize=5
  61 fuPool=system.cpu.fuPool
  62 function_trace=false
  63 function_trace_start=0
  64 globalCtrBits=2
  65 globalHistoryBits=13
  66 globalPredictorSize=8192
  67 iewToCommitDelay=1
  68 iewToDecodeDelay=1
  69 iewToFetchDelay=1
  70 iewToRenameDelay=1
  71 instShiftAmt=2
  72 issueToExecuteDelay=1
  73 issueWidth=8
  74 itb=system.cpu.itb
  75 localCtrBits=2
  76 localHistoryBits=11
  77 localHistoryTableSize=2048
  78 localPredictorSize=2048
  79 max_insts_all_threads=0
  80 max_insts_any_thread=0
  81 max_loads_all_threads=0
  82 max_loads_any_thread=0
  83 numIQEntries=64
  84 numPhysFloatRegs=256
  85 numPhysIntRegs=256
  86 numROBEntries=192
  87 numRobs=1
  88 numThreads=1
  89 phase=0
  90 predType=tournament
  91 progress_interval=0
  92 renameToDecodeDelay=1
  93 renameToFetchDelay=1
  94 renameToIEWDelay=2
  95 renameToROBDelay=1
  96 renameWidth=8
  97 smtCommitPolicy=RoundRobin
  98 smtFetchPolicy=SingleThread
  99 smtIQPolicy=Partitioned
 100 smtIQThreshold=100
 101 smtLSQPolicy=Partitioned
 102 smtLSQThreshold=100
 103 smtNumFetchingThreads=1
 104 smtROBPolicy=Partitioned
 105 smtROBThreshold=100
 106 squashWidth=8
 107 store_set_clear_period=250000
 108 system=system
 109 tracer=system.cpu.tracer
 110 trapLatency=13
 111 wbDepth=1
 112 wbWidth=8
 113 workload=system.cpu.workload
 114 dcache_port=system.cpu.dcache.cpu_side
 115 icache_port=system.cpu.icache.cpu_side
 116
 117 [system.cpu.dcache]
 118 type=BaseCache
 119 addr_range=0:18446744073709551615
 120 assoc=2
 121 block_size=64
 122 forward_snoops=true
 123 hash_delay=1
 124 is_top_level=true
 125 latency=1000
 126 max_miss_count=0
 127 mshrs=10
 128 num_cpus=1
 129 prefetch_data_accesses_only=false
 130 prefetch_degree=1
 131 prefetch_latency=10000
 132 prefetch_on_access=false
 133 prefetch_past_page=false
 134 prefetch_policy=none
 135 prefetch_serial_squash=false
 136 prefetch_use_cpu_id=true
 137 prefetcher_size=100
 138 prioritizeRequests=false
 139 repl=Null
 140 size=262144
 141 subblock_size=0
 142 tgts_per_mshr=20
 143 trace_addr=0
 144 two_queue=false
 145 write_buffers=8
 146 cpu_side=system.cpu.dcache_port
 147 mem_side=system.cpu.toL2Bus.port[1]
 148
 149 [system.cpu.dtb]
 150 type=AlphaTLB
 151 size=64
 152
 153 [system.cpu.fuPool]
 154 type=FUPool
 155 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 156 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 157
 158 [system.cpu.fuPool.FUList0]
 159 type=FUDesc
 160 children=opList
 161 count=6
 162 opList=system.cpu.fuPool.FUList0.opList
 163
 164 [system.cpu.fuPool.FUList0.opList]
 165 type=OpDesc
 166 issueLat=1
 167 opClass=IntAlu
 168 opLat=1
 169
 170 [system.cpu.fuPool.FUList1]
 171 type=FUDesc
 172 children=opList0 opList1
 173 count=2
 174 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 175
 176 [system.cpu.fuPool.FUList1.opList0]
 177 type=OpDesc
 178 issueLat=1
 179 opClass=IntMult
 180 opLat=3
 181
 182 [system.cpu.fuPool.FUList1.opList1]
 183 type=OpDesc
 184 issueLat=19
 185 opClass=IntDiv
 186 opLat=20
 187
 188 [system.cpu.fuPool.FUList2]
 189 type=FUDesc
 190 children=opList0 opList1 opList2
 191 count=4
 192 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 193
 194 [system.cpu.fuPool.FUList2.opList0]
 195 type=OpDesc
 196 issueLat=1
 197 opClass=FloatAdd
 198 opLat=2
 199
 200 [system.cpu.fuPool.FUList2.opList1]
 201 type=OpDesc
 202 issueLat=1
 203 opClass=FloatCmp
 204 opLat=2
 205
 206 [system.cpu.fuPool.FUList2.opList2]
 207 type=OpDesc
 208 issueLat=1
 209 opClass=FloatCvt
 210 opLat=2
 211
 212 [system.cpu.fuPool.FUList3]
 213 type=FUDesc
 214 children=opList0 opList1 opList2
 215 count=2
 216 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 217
 218 [system.cpu.fuPool.FUList3.opList0]
 219 type=OpDesc
 220 issueLat=1
 221 opClass=FloatMult
 222 opLat=4
 223
 224 [system.cpu.fuPool.FUList3.opList1]
 225 type=OpDesc
 226 issueLat=12
 227 opClass=FloatDiv
 228 opLat=12
 229
 230 [system.cpu.fuPool.FUList3.opList2]
 231 type=OpDesc
 232 issueLat=24
 233 opClass=FloatSqrt
 234 opLat=24
 235
 236 [system.cpu.fuPool.FUList4]
 237 type=FUDesc
 238 children=opList
 239 count=0
 240 opList=system.cpu.fuPool.FUList4.opList
 241
 242 [system.cpu.fuPool.FUList4.opList]
 243 type=OpDesc
 244 issueLat=1
 245 opClass=MemRead
 246 opLat=1
 247
 248 [system.cpu.fuPool.FUList5]
 249 type=FUDesc
 250 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 251 count=4
 252 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 253
 254 [system.cpu.fuPool.FUList5.opList00]
 255 type=OpDesc
 256 issueLat=1
 257 opClass=SimdAdd
 258 opLat=1
 259
 260 [system.cpu.fuPool.FUList5.opList01]
 261 type=OpDesc
 262 issueLat=1
 263 opClass=SimdAddAcc
 264 opLat=1
 265
 266 [system.cpu.fuPool.FUList5.opList02]
 267 type=OpDesc
 268 issueLat=1
 269 opClass=SimdAlu
 270 opLat=1
 271
 272 [system.cpu.fuPool.FUList5.opList03]
 273 type=OpDesc
 274 issueLat=1
 275 opClass=SimdCmp
 276 opLat=1
 277
 278 [system.cpu.fuPool.FUList5.opList04]
 279 type=OpDesc
 280 issueLat=1
 281 opClass=SimdCvt
 282 opLat=1
 283
 284 [system.cpu.fuPool.FUList5.opList05]
 285 type=OpDesc
 286 issueLat=1
 287 opClass=SimdMisc
 288 opLat=1
 289
 290 [system.cpu.fuPool.FUList5.opList06]
 291 type=OpDesc
 292 issueLat=1
 293 opClass=SimdMult
 294 opLat=1
 295
 296 [system.cpu.fuPool.FUList5.opList07]
 297 type=OpDesc
 298 issueLat=1
 299 opClass=SimdMultAcc
 300 opLat=1
 301
 302 [system.cpu.fuPool.FUList5.opList08]
 303 type=OpDesc
 304 issueLat=1
 305 opClass=SimdShift
 306 opLat=1
 307
 308 [system.cpu.fuPool.FUList5.opList09]
 309 type=OpDesc
 310 issueLat=1
 311 opClass=SimdShiftAcc
 312 opLat=1
 313
 314 [system.cpu.fuPool.FUList5.opList10]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=SimdSqrt
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5.opList11]
 321 type=OpDesc
 322 issueLat=1
 323 opClass=SimdFloatAdd
 324 opLat=1
 325
 326 [system.cpu.fuPool.FUList5.opList12]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdFloatAlu
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList13]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdFloatCmp
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList14]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdFloatCvt
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList15]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdFloatDiv
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList16]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdFloatMisc
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList17]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdFloatMult
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList18]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdFloatMultAcc
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList19]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdFloatSqrt
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList6]
 375 type=FUDesc
 376 children=opList
 377 count=0
 378 opList=system.cpu.fuPool.FUList6.opList
 379
 380 [system.cpu.fuPool.FUList6.opList]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=MemWrite
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList7]
 387 type=FUDesc
 388 children=opList0 opList1
 389 count=4
 390 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 391
 392 [system.cpu.fuPool.FUList7.opList0]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=MemRead
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList7.opList1]
 399 type=OpDesc
 400 issueLat=1
 401 opClass=MemWrite
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList8]
 405 type=FUDesc
 406 children=opList
 407 count=1
 408 opList=system.cpu.fuPool.FUList8.opList
 409
 410 [system.cpu.fuPool.FUList8.opList]
 411 type=OpDesc
 412 issueLat=3
 413 opClass=IprAccess
 414 opLat=3
 415
 416 [system.cpu.icache]
 417 type=BaseCache
 418 addr_range=0:18446744073709551615
 419 assoc=2
 420 block_size=64
 421 forward_snoops=true
 422 hash_delay=1
 423 is_top_level=true
 424 latency=1000
 425 max_miss_count=0
 426 mshrs=10
 427 num_cpus=1
 428 prefetch_data_accesses_only=false
 429 prefetch_degree=1
 430 prefetch_latency=10000
 431 prefetch_on_access=false
 432 prefetch_past_page=false
 433 prefetch_policy=none
 434 prefetch_serial_squash=false
 435 prefetch_use_cpu_id=true
 436 prefetcher_size=100
 437 prioritizeRequests=false
 438 repl=Null
 439 size=131072
 440 subblock_size=0
 441 tgts_per_mshr=20
 442 trace_addr=0
 443 two_queue=false
 444 write_buffers=8
 445 cpu_side=system.cpu.icache_port
 446 mem_side=system.cpu.toL2Bus.port[0]
 447
 448 [system.cpu.itb]
 449 type=AlphaTLB
 450 size=48
 451
 452 [system.cpu.l2cache]
 453 type=BaseCache
 454 addr_range=0:18446744073709551615
 455 assoc=2
 456 block_size=64
 457 forward_snoops=true
 458 hash_delay=1
 459 is_top_level=false
 460 latency=1000
 461 max_miss_count=0
 462 mshrs=10
 463 num_cpus=1
 464 prefetch_data_accesses_only=false
 465 prefetch_degree=1
 466 prefetch_latency=10000
 467 prefetch_on_access=false
 468 prefetch_past_page=false
 469 prefetch_policy=none
 470 prefetch_serial_squash=false
 471 prefetch_use_cpu_id=true
 472 prefetcher_size=100
 473 prioritizeRequests=false
 474 repl=Null
 475 size=2097152
 476 subblock_size=0
 477 tgts_per_mshr=5
 478 trace_addr=0
 479 two_queue=false
 480 write_buffers=8
 481 cpu_side=system.cpu.toL2Bus.port[2]
 482 mem_side=system.membus.port[2]
 483
 484 [system.cpu.toL2Bus]
 485 type=Bus
 486 block_size=64
 487 bus_id=0
 488 clock=1000
 489 header_cycles=1
 490 use_default_range=false
 491 width=64
 492 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 493
 494 [system.cpu.tracer]
 495 type=ExeTracer
 496
 497 [system.cpu.workload]
 498 type=LiveProcess
 499 cmd=hello
 500 cwd=
 501 egid=100
 502 env=
 503 errout=cerr
 504 euid=100
 505 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 506 gid=100
 507 input=cin
 508 max_stack_size=67108864
 509 output=cout
 510 pid=100
 511 ppid=99
 512 simpoint=0
 513 system=system
 514 uid=100
 515
 516 [system.membus]
 517 type=Bus
 518 block_size=64
 519 bus_id=0
 520 clock=1000
 521 header_cycles=1
 522 use_default_range=false
 523 width=64
 524 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 525
 526 [system.physmem]
 527 type=PhysicalMemory
 528 file=
 529 latency=30000
 530 latency_var=0
 531 null=false
 532 range=0:134217727
 533 zero=false
 534 port=system.membus.port[1]
 535