Add support for tsunami with 64 processors and fix some console bugs

I steped on while doing it

console/console.c:
    Allocate more HWRPB pages so we have room for 64 percpu_rpbs
    Fix writing of Console Relocation Block virtual addresses so that
    if they are outside of the first page, which they will be with more
    than 8 processors, the correct adress is written
palcode/Makefile:
    Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
    Add support for tsunami with 64 processors

diff --git a/system/alpha/console/console.c b/system/alpha/console/console.c
index b4afcaae197f1b5c35eb81f416349478923a4656..2ab4c6ec8f065278df9203ef14668fc942f0e617 100644 (file)
--- a/system/alpha/console/console.c
+++ b/system/alpha/console/console.c
@@ -58,7 +58,7 @@ typedef unsigned int uint32;
 /* Kernel write | kernel read | valid */
 #define KPTE(x) ((ul)((((ul)(x)) << 32) | 0x1101))
 
-#define HWRPB_PAGES 4
+#define HWRPB_PAGES 16
 #define MDT_BITMAP_PAGES  4
 
 #define CSERVE_K_JTOKERN       0x18
@@ -480,6 +480,7 @@ unixBoot(int go, int argc, char **argv)
    first[1] = KPTE(PFN(first)); /* Region 3 */
 
    second[SECOND(0x10000000)] = KPTE(PFN(third_rpb));  /* Region 0 */
+
    for (i=0;i<NUM_KERNEL_THIRD;i++) {
       second[SECOND(0x20000000)+i] = KPTE(PFN(third_kernel)+i);        /* Region 1 */
    }
@@ -720,9 +721,10 @@ unixBoot(int go, int argc, char **argv)
   rpb_crb->rpb_map[0].rpb_pgcount = HWRPB_PAGES;
 
 
-  printf_lock("Console Callback at 0x%x, fixup at 0x%x \n",
+  printf_lock("Console Callback at 0x%x, fixup at 0x%x, crb offset: 0x%x\n",
           rpb_crb->rpb_va_disp,
-          rpb_crb->rpb_va_fixup );
+          rpb_crb->rpb_va_fixup,
+          rpb->rpb_crb_off);
 
   rpb_mdt = (struct _xxm_rpb_mdt *) (((ul)rpb_crb) + sizeof(struct rpb_crb));
   rpb->rpb_mdt_off = (ul)rpb_mdt - (ul)rpb;
@@ -811,11 +813,7 @@ unixBoot(int go, int argc, char **argv)
  {
      ul *ptr = (ul*)((char*)rpb_dsr + sizeof(struct rpb_dsr ));
      rpb_crb->rpb_pa_disp = KSEG_TO_PHYS(ptr);
-#if 0
-     rpb_crb->rpb_va_disp = 0x10000000 + ((ul)ptr&(0x2000*HWRPB_PAGES-1));
-#else
-     rpb_crb->rpb_va_disp = 0x10000000 + ((ul)ptr & 0x1fff);
-#endif
+     rpb_crb->rpb_va_disp = 0x10000000 + (((ul)ptr - (ul)rpb) & (0x2000*HWRPB_PAGES-1));
      printf_lock("ConsoleDispatch at virt %x phys %x val %x\n",
              rpb_crb->rpb_va_disp,
             rpb_crb->rpb_pa_disp,
@@ -823,12 +821,9 @@ unixBoot(int go, int argc, char **argv)
      *ptr++ = 0;
      *ptr++ = (ul) consoleCallback;
      rpb_crb->rpb_pa_fixup = KSEG_TO_PHYS(ptr);
-#if 0
-     rpb_crb->rpb_va_fixup = 0x10000000 + ((ul)ptr& (0x2000*HWRPB_PAGES-1));
-#else
-     rpb_crb->rpb_va_fixup = 0x10000000 + ((ul)ptr & 0x1fff);
-#endif
+     rpb_crb->rpb_va_fixup = 0x10000000 + (((ul)ptr - (ul)rpb) & (0x2000*HWRPB_PAGES-1));
      *ptr++ = 0;
+
      *ptr++ = (ul) consoleFixup;
   }
 

diff --git a/system/alpha/palcode/Makefile b/system/alpha/palcode/Makefile
index 2d5e907f11be11fa34cbaeef73553f1613fb8980..3f4dc9b5ee1afc111a63646b46c72b38126a0d48 100644 (file)
--- a/system/alpha/palcode/Makefile
+++ b/system/alpha/palcode/Makefile
@@ -1,21 +1,26 @@
 #Makefile for palcode
 #Works on alpha-linux and builds elf executable
 
-GAS = alpha-elf-as
-CC = alpha-elf-g++
-LD = alpha-elf-ld
+GAS = alpha-linux-as
+CC = alpha-linux-gcc
+LD = alpha-linux-ld
 CFLAGS=-I . -I ../h -D SIMOS -D BUILD_PALCODE -nostdinc -nostdinc++ -Wa,-m21164
 LDFLAGS=-Ttext 0x4000
 
 TLOBJS = osfpal.o  platform_tlaser.o
 TLOBJS_COPY = osfpal_cache_copy.o osfpal_cache_copy_unaligned.o
 TSOBJS = osfpal.o platform_m5.o
+TSBOBJS = osfpal.o platform_m5b.o
 TSOBJS_COPY = osfpal_cache_copy.o osfpal_cache_copy_unaligned.o
 
 %.o: %.S
        $(CC) $(CFLAGS) -o $@ -c $<
 
-all: tlaser tsunami
+all: tsunami tsunami_b64
+       
+platform_m5b.o: platform_m5.S
+       $(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $<
+       
 
 tlaser:  $(TLOBJS)
        $(LD) $(LDFLAGS) -o tl_osfpal osfpal.o platform_tlaser.o
@@ -27,10 +32,13 @@ tlaser_copy: $(TLOBJS_COPY) $(TLOBJS)
 tsunami: $(TSOBJS)
        $(LD) $(LDFLAGS) -o ts_osfpal osfpal.o platform_m5.o
 
+tsunami_b64: $(TSBOBJS)
+       $(LD) $(LDFLAGS) -o tsb_osfpal osfpal.o platform_m5b.o
+
 tsunami_copy: $(TSOBJS) $(TSOBJS_COPY)
        $(LD) $(LDFLAGS) -o ts_osfpal_cache  osfpal_cache_copy.o platform_m5.o
        $(LD) $(LDFLAGS) -o ts_osfpal_unalign osfpal_cache_copy_unaligned.o platform_m5.o
 
 clean:
        rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \
-       ts_osfpal_cache ts_osfpal_unalign
+       ts_osfpal_cache ts_osfpal_unalign tsb_osfpal

diff --git a/system/alpha/palcode/platform_m5.S b/system/alpha/palcode/platform_m5.S
index 6c4e85b1ca5ee08b50887d696633b9eae6e0607f..9a7bf6160ac5d3efa9b81eede6b2d4c42d3327ea 100644 (file)
--- a/system/alpha/palcode/platform_m5.S
+++ b/system/alpha/palcode/platform_m5.S
@@ -71,6 +71,26 @@
 #define osfpcb_q_Ksp pcb_q_ksp
 #define pal_impure_common_size ((0x200 + 7) & 0xfff8)
 
+#ifdef BIG_TSUNAMI
+#define MAXPROC         0x3f
+#define IPIQ_addr       0x800
+#define IPIQ_shift      0
+#define IPIR_addr       0x840
+#define IPIR_shift      0
+#define RTC_addr        0x880
+#define RTC_shift       0
+#define DIR_addr        0xa2
+#else
+#define MAXPROC         0x3
+#define IPIQ_addr       0x080
+#define IPIQ_shift      12
+#define IPIR_addr       0x080
+#define IPIR_shift      8
+#define RTC_addr        0x080
+#define RTC_shift       4
+#define DIR_addr        0xa0
+#endif
+
 #define ALIGN_BLOCK \
         .align 5
 
@@ -431,12 +451,10 @@ EXPORT(sys_wripir)
 //++
 // Convert the processor number to a CPU mask
 //--
-
-        and    r16,0x3, r14            // mask the top stuff (4 CPUs supported)
+        and    r16,MAXPROC, r14        // mask the top stuff (4 or 64 CPUs supported)
         bis    r31,0x1,r16             // get a one
         sll    r16,r14,r14             // shift the bit to the right place
-        sll     r14,12,r14
-
+        sll     r14,IPIQ_shift,r14
 
 //++
 // Build the Broadcast Space base address
@@ -446,7 +464,7 @@ EXPORT(sys_wripir)
         ldah    r13,0xa0(r31)
         sll    r13,8,r13
         bis    r16,r13,r16
-        lda     r16,0x0080(r16)
+        lda     r16,IPIQ_addr(r16)
 
 //++
 // Send out the IP Intr
@@ -748,14 +766,14 @@ sys_int_23:
         sll     r12,16,r12
         lda     r12,0xa000(r12)
         sll     r12,16,r12
-        lda     r12,0x080(r12)
+        lda     r12,IPIR_addr(r12)
 
         mfpr    r10, pt_whami                   // get CPU ID
         extbl  r10, 1, r10                     // Isolate just whami bits
         or      r31,0x1,r14                     // load r14 with bit to clear
         sll     r14,r10,r14                     // left shift by CPU ID
-        sll     r14,8,r14
-        stq_p   r14, 0(r12)                     // clear the rtc interrupt
+        sll     r14,IPIR_shift,r14
+        stq_p   r14, 0(r12)                     // clear the ipi interrupt
 
         br     r31, pal_post_interrupt         // Notify the OS
 
@@ -767,12 +785,13 @@ sys_int_22:
         sll     r12,16,r12
         lda     r12,0xa000(r12)
         sll     r12,16,r12
-        lda     r12,0x080(r12)
+        lda     r12,RTC_addr(r12)
 
         mfpr    r10, pt_whami                   // get CPU ID
         extbl  r10, 1, r10                     // Isolate just whami bits
-        or      r31,0x10,r14                    // load r14 with bit to clear
+        or      r31,0x1,r14                     // load r14 with bit to clear
         sll     r14,r10,r14                     // left shift by CPU ID
+        sll     r14,RTC_shift,r14               // put the bits in the right position
         stq_p   r14, 0(r12)                     // clear the rtc interrupt
 
         br     r31, pal_post_interrupt         // Tell the OS
@@ -810,15 +829,20 @@ sys_int_20:
         ALIGN_BRANCH
 sys_int_21:
 
-    lda     r12,0xf01(r31)
+    lda     r12,0xf01(r31)                // calculate DIRn address
     sll     r12,32,r12
-    ldah    r13,0xa0(r31)
+    ldah    r13,DIR_addr(r31)
     sll            r13,8,r13
     bis            r12,r13,r12
-    lda     r12,0x0080(r12)
+
     mfpr    r13, pt_whami                   // get CPU ID
     extbl   r13, 1, r13                            // Isolate just whami bits
 
+#ifdef BIG_TSUNAMI
+    sll     r13,4,r13
+    or      r12,r13,r12
+#else
+    lda     r12,0x0080(r12)
     and     r13,0x1,r14                     // grab LSB and shift left 6
     sll     r14,6,r14
     and     r13,0x2,r10                     // grabl LSB+1 and shift left 9
@@ -826,9 +850,11 @@ sys_int_21:
 
     mskbl   r12,0,r12                       // calculate DIRn address
     lda     r13,0x280(r31)
-    bis            r12,r13,r12
+    bis     r12,r13,r12
     or      r12,r14,r12
     or      r12,r10,r12
+#endif
+
     ldqp    r13, 0(r12)                     // read DIRn
 
     or      r31,1,r14                       // set bit 55 (ISA Interrupt)