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(parent: fced120) | patch
1 bit extra accuracy in mul if the top bit of mantissa is zero
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 13 Jul 2019 13:21:27 +0000 (14:21 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 13 Jul 2019 13:21:27 +0000 (14:21 +0100)
commitfdefa9d354a0f3e4478db75c880169d949f7f8ed
treec9eb3ef260b6f8d763237afbf6bcd1440ecbe23ftree
parentfced120d60faa951a2392d640c5052e17934ff4bcommit | diff
1 bit extra accuracy in mul if the top bit of mantissa is zero
src/ieee754/fpmul/mul1.py diff | blob | history