disable faulty bit_width reduction logic in DivPipeCore
-rw-r--r-- 78 .gitignore
-rw-r--r-- 2004 .gitlab-ci.yml
-rw-r--r-- 238 .gitmodules
-rw-r--r-- 216 Makefile
-rw-r--r-- 0 NEWS.txt
-rw-r--r-- 1151 README.md
-rw-r--r-- 596 SoftPosit.patch
m--------- - berkeley-softfloat-3
-rw-r--r-- 790 berkeley-softfloat.patch
m--------- - berkeley-testfloat-3
drwxr-xr-x - doc
-rw-r--r-- 1103 setup.py
drwxr-xr-x - src

IEEE754 Floating-Point ALU, in nmigen

This project implements a pipelined IEEE754 floating-point ALU that supports FP16, FP32 and FP64. It is a general-purpose unit that may be used in any project (not limited to one specific processor).


Building sfpy

The standard sfpy will not work without being modified to the type of IEEE754 FP emulation being tested. This FPU is emulating RISC-V, and there is some weirdness in x86 IEEE754 implementations when it comes to FP16 non-canonical NaNs.

The following modifications are required to the sfpy berkeley-softfloat-3 submodule:

cd /path/to/sfpy/berkeley-softfloat-3
git apply /path/to/ieee754fpu/berkeley-softfloat.patch

The following modifications are required to the sfpy SoftPosit Makefile:

cd /path/to/sfpy/SoftPosit
git apply /path/to/ieee754fpu/SoftPosit.patch

Useful resources