run tests in parallel
[ieee754fpu.git] / src / ieee754 / cordic /
drwxr-xr-x   ..
-rw-r--r-- 1316 pipe_data.py
-rw-r--r-- 3895 sin_cos.py
-rw-r--r-- 1823 sin_cos_pipe_stage.py
-rw-r--r-- 1472 sin_cos_pipeline.py
drwxr-xr-x - test
README.md

IEEE754 Floating-Point ALU, in nmigen

This project implements a pipelined IEEE754 floating-point ALU that supports FP16, FP32 and FP64. It is a general-purpose unit that may be used in any project (not limited to one specific processor).

Requirements

Building sfpy

The standard sfpy will not work without being modified to the type of IEEE754 FP emulation being tested. This FPU is emulating RISC-V, and there is some weirdness in x86 IEEE754 implementations when it comes to FP16 non-canonical NaNs.

The following modifications are required to the sfpy berkeley-softfloat-3 submodule:

cd /path/to/sfpy/berkeley-softfloat-3
git apply /path/to/ieee754fpu/berkeley-softfloat.patch

The following modifications are required to the sfpy SoftPosit Makefile:

cd /path/to/sfpy/SoftPosit
git apply /path/to/ieee754fpu/SoftPosit.patch

Useful resources