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[libreriscv.git] / Cesar_Strauss.mdwn
1 # Cesar Strauss
2
3 Contributor
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=cestrauss@gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
6
7 # Status Tracking
8
9 ## Currently working on
10
11 1. ALU CompUnit needs to recognise that RA (src1) can be zero
12 <https://bugs.libre-soc.org/show_bug.cgi?id=336>
13 Status: DONE
14 Unit test Status: in progress
15
16
17 2. Something about the above (5), being optional.
18 <https://bugs.libre-soc.org/show_bug.cgi?id=336#c5>
19 Status: DONE
20 Unit test Status: in progress
21
22 3. CompALUMulti parallel functions unit test
23 <https://bugs.libre-soc.org/show_bug.cgi?id=336#c11>
24 Priority: Medium-to-High
25
26 4. Code-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU
27 <https://bugs.libre-soc.org/show_bug.cgi?id=318#c18>
28 Status: Need a review of Luke's implementation, compared to mine.
29 Priority: Low
30
31 5. Test dual ports (two L0CacheBuffer with two ports, 4-4 as well) which
32 write to the same memory
33 <https://bugs.libre-soc.org/show_bug.cgi?id=318#c11>
34 Status: not started
35 Priority: High
36
37 6. Luke tried two LDs in the score6600 code - they failed.
38 <https://bugs.libre-soc.org/show_bug.cgi?id=318#c17>
39 Status: not started, need to check the [prototype] L0CacheBuffer
40 Priority: High
41
42 7. Fix a bug in the LDSTCompUnit
43 <https://bugs.libre-soc.org/show_bug.cgi?id=318>
44 Status: Luke thinks he fixed it, but needs a review and improving the
45 unit tests.
46 See: <https://bugs.libre-soc.org/show_bug.cgi?id=318#c7>
47 Priority: Medium
48
49 8. LDSTCompUnit parallel functions unit test
50 <https://bugs.libre-soc.org/show_bug.cgi?id=350>
51 Priority: Medium-ish
52
53 10. Find root cause of cxxsim hang
54 <https://bugs.libre-soc.org/show_bug.cgi?id=475#c2>
55 Status: ongoing
56 Priority: High
57
58 11. Formal Proof for CompUnit
59 <https://bugs.libre-soc.org/show_bug.cgi?id=342>
60
61 12. Formal Proof for PartitionedSignal
62 <https://bugs.libre-soc.org/show_bug.cgi?id=565>
63 Status: in progress
64
65 13. Implement simple VL for-loop in nMigen for TestIssuer
66 <https://bugs.libre-soc.org/show_bug.cgi?id=583>
67 Status: in progress
68
69 ## Completed but not yet submitted:
70
71 1. FSM-based ALU example needed (compliant with ALU CompUnit)
72 <https://bugs.libre-soc.org/show_bug.cgi?id=417>
73
74 2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder
75 <https://bugs.libre-soc.org/show_bug.cgi?id=600>
76
77 ## Submitted for NLNet RFP
78
79 ## Paid