about_us.mdwn

   1 # Meet the Team
   2
   3 These are our current members
   4
   5 Also, check out [[The_Mission]].
   6
   7 ## [[Luke Kenneth Casson Leighton|lkcl]]
   8
   9 * Hardware Experience: assembly-level programming, gate-level
  10   circuit design, PCB design, reverse-engineering, embedded systems
  11   design and programming, software engineering, standards development,
  12   libre project management and more.
  13 * Ethical Technology Specialist.  Identifies socio-economic imbalances and
  14   works out if there's an ethical way in which technology can help.  If that
  15   technology doesn't exist, creates it.
  16 * Interests: varied and including particle physics, Medieval and Folk music, and writing poems.
  17 * website: [[http://lkcl.net]]
  18 * github: doesn't have one (because github is a proprietary non-free service),
  19   runs his own git servers, manages projects (several), entirely in a libre
  20   fashion, including managing the server(s).
  21 * Availability: full-time
  22
  23 ## [[Jacob Lifshay|programmerjake]]
  24
  25 * FOSS Software Developer, Hardware Designer, Original Author of Kazan (one of our GPU drivers, also a software-rendered Vulkan implementation that works on most CPUs)
  26 * Built a working RV32I CPU and VGA core that runs a 3D game in 3 weeks: [[https://github.com/programmerjake/rv32]]
  27 * Built an algebraic numbers library: https://crates.io/crates/algebraics
  28 * Built a (non-official) reference implementation of IEEE 754-2019 (binary floating-point): [[https://crates.io/crates/simple-soft-float]]
  29 * Interests: Computer Graphics, Compilers, Simulation, Rust-lang, Anime, Astrophysics, Electronics, Computer Design, Chemistry, Nuclear Physics, Cellular Automatons, Video Game Software Engineering, High-performance Computing
  30 * GitHub: [[https://github.com/programmerjake]]
  31 * Availability: full-time
  32
  33 ## [[Tobias Platen|tplaten]]
  34
  35 * Copyleft Software Developer, Hardware Designer and Reverse Engineer
  36 * Interests: varied and including speech synthesis and cosplay.
  37 * website: [[https://www.platen-software.de/tobias/]]
  38 * github: doesn't have one using notabug instead
  39   [[https://notabug.org/isengaara]]
  40 * Availability: Outside normal working hours.
  41
  42 ## Yann Guidon (whygee)
  43
  44 * Experience: Processor architecture : designer of
  45     F-CPU project since 1999 [[http://f-cpu.org]]
  46     YASEP (16- & 32-bits real-time controller)  [[http://yasep.org]]
  47     YGREC8 (8-bits microcontroller)   [[http://ygrec8.com]]
  48 * Interests: Designer of electronic circuits circuits for industrial
  49   and artistic applications with dedicated workshop for PCB prototyping
  50   with wide range of technologies Algorithmics, including data
  51   compression, signal processing (sound & picture), optimisations,
  52   design for test...
  53
  54 ## [[Lauri Kasanen|lauri]]
  55
  56 * Embedded software engineer
  57 * Interests: niche platforms, embedded, servers, graphics
  58 * github: [[https://github.com/clbr]]
  59 * Availability: part-time
  60
  61 ## [[Veera Kumar|veera]]
  62
  63 * Software developer, programmer and small system administrator
  64 * Knowledge in using Redhat, Fedora, Debian and few others
  65 * Have experience building a custom Linux distribution based on LFS/CLFS
  66 * Experience in Shell, C, Awk, Perl, Python, Lua, HTML, CSS, PHP
  67 * Develop websites, run VPS on Linux
  68 * Build open source softwares from source and test and use it
  69 * Website [[http://www.vkten.in]]
  70 * Availability: part-time
  71
  72 ## [[Jock Tanner|jock_tanner]]
  73
  74 * Expertise: Python developer, full-stack web developer (6+ years)
  75 * My code: [[https://github.com/dmelnichuk/]], [[https://github.com/jock-tanner/]]
  76 * GNU/Linux user/administrator
  77 * Hobbies: electronics, real-time systems, digital music & sound processing, embedded systems, FPGA, retro computing
  78 * Availability: ~20hrs/week
  79 * Time zone: UTC+10:00
  80
  81 ## [[Alain Williams|addw]]
  82
  83 Alain's website: <http://phcomp.co.uk>
  84
  85 ## [[Cesar Strauss|Cesar_Strauss]]
  86
  87 * Experience: Data acquisition and control for scientific instruments
  88 * Programming of microcontrolers and FPGAs
  89 * Digital circuit design
  90 * Availability: Outside normal working hours.
  91
  92 ## [[Cole Poirier|cole]]
  93
  94 * Trying to learn and organize stuff
  95 * GitHub: [[https://github.com/colepoirier]]
  96 * Availability: full-time
  97
  98 ## [[Sanjay A Menon|Sanjay]]
  99
 100 * Skills: Verilog, C/C++, Python, TCL & PERL
 101 * Github Profile: [[https://github.com/Sanjay-A-Menon]]
 102 * LinkedIn Profile: [[https://www.linkedin.com/in/sanjay-menon-91791815a]]
 103 * Availability: ~6hrs/week
 104
 105 ## [[Samuel A Falvo II]]
 106
 107 * Experience in amateur HDL projects (Kestrel-3 homebrew computer
 108    concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB
 109    design.  Extensive experience with test-driven development, Python,
 110    assembly language for a wide variety of CPUs including RISC-V, and Forth.
 111    Very comfortable with nMigen, but still learning things.
 112 * Interests: Forth, Common Lisp, Scheme, assembly language,
 113    {Astro|Semiconductor-}physics, astronomy, martial arts, furry (character: black dragon; name: "Vertigo").
 114 * Websites:
 115   - https://hackaday.io/project/170581-vdc-ii ,
 116   - https://kestrelcomputer.github.io/kestrel/ ,
 117   - http://chiselapp.com/user/kc5tja/repository/kestrel-3/index
 118 * Public Repositories:
 119   - https://github.com/sam-falvo ,
 120   - https://github.com/kestrelcomputer
 121 * Availability: approximately 20 hrs/wk, circumstances permitting.
 122
 123 ## [[Alex Oliva|lxo]]
 124
 125 * Experience: GCC, binutils, glibc, GNU autotools, Free Software activism.
 126 * website: [[https://www.fsfla.org/~lxoliva/]]
 127 * Availability: 10+hrs/week
 128
 129 ## [[Richard Wilbur|rwilbur]]
 130
 131 * Interests:  Libre in hardware and software, low-power, efficiency
 132 * Hardware Experience:  High-speed digital(comb. & FSM), PLD(PALASM), FPGA(VHDL), low-power, analog video, I2C, DDC, PCI, RS-232/422/485, SOC board bring-up, PCB layout, VLSI gate design
 133 * Software Experience:  optimization, 3D geometry transformations, simulation, atomic & multi-threaded, PCI auto-configuration, drivers (serial HW, MPEG encoder/decoder(TS generation/consumption), GPS), OpenGL vertex shader, SQL db, network protocol design, test-driven dev, PCI BIOS, fixed-point division
 134 * Languages:  C, C++, Python, asm, bash, PERL, BASIC, Forth, ruby
 135 * Architectures:  6502/10, 68k, x86_64, PPC, i960, SPARC
 136 * Website:  [[https://launchpad.net/~richard-wilbur]]
 137 * Availability:  10+hrs/week, more is negotiable
 138 * Timezone:  UTC-07:00 (DST UTC-06:00, 2nd Sun of Mar-1st Sun of Nov)
 139
 140 ## [[Mikolaj Wielgus|mikolajw]]
 141
 142 * Interests: Libre software and hardware, analog circuits, RF and microwave circuits, nonlinear systems, oscillators
 143 * Hardware Experience: PCB schematic and layout design, very small amount of IC design
 144 * Software Experience: Data acquisition and processing (LXI, SCPI), GUI development (wxWidgets), Microcontroller programming (AVR, STM32), video game development (Love2D, SDL)
 145 * Languages: Verilog, Asm (AVR), C, C++, C#, D, Python, Octave, Lua, Java, or any other language involving a similar set of abstractions
 146 * GitLab: https://gitlab.com/mwielgus
 147 * Most of my skills are self-taught by making small amateur projects. I have only little industry experience.
 148 * Availability: ~6 hrs/week
 149 * Timezone: UTC+01:00
 150
 151 ## Object Automation
 152
 153 ### [[oa/madan]]
 154
 155 * Interests: Programming in Python and Knowledge of ML algorithms and NLP
 156 * Availability: 5 hours per week
 157 * Statistician
 158
 159
 160 ### [[oa/gautham]]
 161
 162 * Interests: Digital System Design, PCB Layout, Programming, Machine Learning
 163 * Programming Languages: Verilog, C, C++, Python
 164 * Availability: ~8-10 hours/week
 165
 166 ### [[oa/adithya]]
 167
 168 * Interests:Digital System Design,PCB layout, Programming, Machine Learning, IoT
 169 * Programming Languages: Verilog, C, C++, Java, Python3, Julia
 170 * Availability: ~10hrs per week
 171
 172 ### [[oa/Niranjan]]
 173
 174 * Interests: Digital System Design, PCB Layout, Programming
 175 * Programming Languages: Verilog, C, C++, Python
 176 * Availability: ~8-10 hours/week
 177
 178 ### [[oa/Abhishek]]
 179
 180 * Interests: HPC, embedded systems, Digital system design
 181 * Programming Languages: C, Python, Java, VHDL
 182 * Availability: ~8-10 hours/week
 183
 184 ### [[oa/Sukhanshu D]]
 185
 186 * Experience: SOC Verification Intern, Digital Design
 187 * Programming Languages: Python, Verilog, Ng-spice
 188 * Availability: 4-6 hours per week
 189
 190 ### [[oa/Mehul N]]
 191
 192 * Interests: Digital Design, Verification, IC Fabrication
 193 * Programming Languages: Verilog, System Verilog, UVM
 194 * Availability: ~ 6-8 hours/week
 195 * Experience: SoC Verification Intern, Research Intern at KIS
 196
 197 ## 3mdeb
 198
 199 ### [[Dmitry Selyutin|3mdeb/ghostmansd]]
 200
 201 * Interests: OS development, fishing, classical antiquity
 202 * Languages: C, C++, Python
 203 * FW experience: system programming
 204 * Availability: depends on a week (0..10+hrs/week)
 205
 206 ## [[Kyle Lehman|klehman]]
 207
 208 * Languages: C/C++, Java, Python, SQL, assembly
 209 * Interests: Language design, microacrhitecture, OS design, emulation, 3D computation
 210 * Other interests: Nearly anything that floats, flies, or has an engine with wheels
 211
 212 ## [[Andrey Miroshnikov|andreym]]
 213 * Languages: C, Python, Verilog
 214 * Interests: Analogue/digital electronics, RF, mobile comms, compilers, FPGAs, discrete mathematics, microarchitecture, Unix OSs, PCB design
 215 * Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
 216 * Other interests: Lingua Latina, Philosophy, History
 217 * Availability: Full-time
 218 * IRC: octavius
 219
 220 ## [[Manikandan Nagarajan|Manik]]
 221
 222 * Languages: Verilog HDL, VHDL, C, Python & TCL
 223 * Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design.
 224 * LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
 225 * Availability: 8~10hrs/week