lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
  23   - EUR 150
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
  25   - EUR 150
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
  29    - EUR 250
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
  31    - EUR 1250
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  41  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  45    - EUR
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  50  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  51  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  54    - shared with cole
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  56    - EUR 50, shared with samuel 10%
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  58
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  61    - EUR 50, shared with samuel (EUR 350)
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  65  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  67    - EUR 200
  68  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  70    - donated
  71    - parent #198
  72    - EUR 200
  73  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  74   - MultiCompUnit (and Function Units) proof
  75  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  76   - donated
  77   - parent #195
  78  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  79
  80 ## Completed but not yet submitted:
  81
  82 TO SORT
  83
  84 28feb2022
  85
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
  87    * EUR 1500 (shared with [[tplaten]])
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
  89    * EUR 1500 (shared with [[tplaten]])
  90  - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
  91    * EUR 1000 (shared with [[tplaten]])
  92  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
  93    * EUR 500 (shared with [[programmerjake]])
  94  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  95    * EUR 400 (shared with [[programmerjake]])
  96
  97 before that
  98
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
 100    - EUR 1600
 101    - EUR 800 shared with [[klehman]]
 102    - EUR 800 shared with [[lkcl]]
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
 104    - EUR 800
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
 109    - EUR 500
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
 112  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
 114  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
 115
 116
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 118    - EUR 150
 119    - donated
 120  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 121    - EUR 200
 122    - donated
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 124    - EUR 150
 125    - donated
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 127    - EUR 200
 128    - donated
 129  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 130    - EUR 700
 131    - (lip6.fr donated)
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 133    - (total EUR 400 25% donated by LIP6)
 134    - EUR 100 lkcl
 135  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 136    - EUR 900
 137    - shared with [[lxo]]
 138  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 139    - EUR 1100
 140    - shared with lauri, jacob
 141  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 142    - EUR 1250
 143    - Shared 50% with Staf
 144  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 145    - EUR 300
 146    - Shared with Staf, cole
 147  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 148    - EUR 450
 149    - Shared with Staf
 150  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 151  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 152    - Project 2019-10-043 06dec2020 wishbone
 153    - EUR (TBD)
 154
 155 ### Project 2019-10-029 14mar2020 coriolis2
 156
 157  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 158    - (total EUR 100 shared 50% with staf)
 159    - EUR 50 lkcl
 160  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 161    - (total EUR 1500 shared 50% with LIP6)
 162    - EUR 750 lkcl
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 164    - (total EUR 400 shared 75% with LIP6)
 165    - EUR 300 lkcl
 166
 167 ### Project 2019-02-012 06dec2020 Core
 168
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 170    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 171  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 172    - EUR 750 donated
 173  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 174    - EUR 1500
 175
 176 ### Project 2019-10-043 06dec2020 wishbone
 177
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 179    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 181    - EUR 200
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 183    - EUR 100
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 185    - EUR 200
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 187    - EUR 100
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 189    - EUR 200
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 191    - EUR 450
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 193    - EUR 100
 194  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 195    - EUR 200 donated
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 197    - EUR 250 (share with cole)
 198
 199 ### Project 2019-10-032 06dec2020 proofs
 200
 201  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 202    - parent #195
 203    - EUR 400 donated
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 205    - parent #195
 206    - EUR 300 donated
 207  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 208    - EUR 400 donated
 209    - parent #195
 210  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 211    - EUR 400 donated
 212    - parent #195
 213
 214 ## Submitted for NLNet RFP
 215
 216 submitted 2021-dec-09 but not confirmed paid
 217
 218  - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
 219    - EUR 300
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
 221    - EUR 250
 222  - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
 223  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
 224  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
 225    - EUR 800 shared between:
 226    - EUR 500 [[lkcl]]
 227    - EUR 300 [[tplaten]]
 228  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
 229    - EUR 5500 shared between:
 230    - EUR 3850 lkcl
 231    - EUR 1650 Others
 232  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
 233    - EUR 1600
 234  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
 235    - EUR 600
 236  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
 237    - EUR 500 shared between:
 238    - EUR 100 [[lkcl]]
 239    - EUR 325 dmitry
 240    - EUR 75 maciej
 241  - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
 242
 243
 244 ### Project 2019-02-012 04sep2020 Core
 245
 246  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 247    - EUR 2000 total, shared with florent.  EUR 1200
 248
 249 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 250
 251 ## Paid
 252
 253 donation from NLNet confirmed received:
 254
 255 ### coriolis2 2021-apr-04
 256
 257  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 258    - EUR 3000
 259    - shared with Staf 50%
 260
 261 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 262
 263  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 264     - EUR 2000, python POWER9 simulator
 265     - Shared 50% with [[mnolan]], EUR 1000
 266  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 267     - EUR 250, functions needed for simulator
 268     - Shared 20% with [[mnolan]], EUR 50
 269
 270 ### proofs 2019-10-032
 271
 272  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 273    - EUR 500 shared 20% samuel, EUR 100
 274  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 275    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 276  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 277    - EUR 400 shared 25% [[mnolan]] EUR 100
 278  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 279    - EUR 150
 280
 281 ### wishbone 2019-10-043
 282
 283  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 284    - EUR 500
 285  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 286     - EUR 300
 287  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 288     - EUR 250
 289  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 290    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 291  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 292    - EUR 300
 293  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 294    - EUR 400, 50% shared [[programmerjake]] EUR 200
 295  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 296    - EUR 750, 33% shared [[programmerjake]] EUR 250
 297  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 298    - EUR 200 50% shared, cole, EUR 100
 299  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 300    - EUR 200
 301  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 302    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 303  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 304    - EUR 150
 305  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 306    - EUR 400 shared 50% [[mnolan]] EUR 200
 307  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 308    - EUR 250 shared 40% [[mnolan]] EUR 100
 309  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 310    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 311  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 312    - EUR 300 shared 50% [[mnolan]] EUR 150
 313  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 314    - EUR 750
 315  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 316   - EUR 100
 317  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 318   - EUR 100
 319  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 320    - EUR 100
 321  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 322    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 323
 324 ### Project 2019-02-012 28-apr-2020
 325
 326  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 327    - 6600 scoreboard multi-read/write
 328    - EUR 600
 329  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 330    - Partitioned equals and greater than comparison
 331    - Shared 50% with [[mnolan]]
 332    - EUR 200 (each)
 333  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 334    - partitioned scalar/vector shift
 335    - Shared 50% with [[lkcl]]
 336    - EUR 350 (each)
 337
 338 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 339
 340  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 341     - auto-parser of POWER9
 342     - Shared 50% with [[mnolan]]
 343     - EUR 500 (each)
 344
 345 ### Project 2019-10-029 Date 14mar2020
 346
 347 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 348   - EUR 1200
 349
 350 ### Project 2019-02-012 Date 12mar2020
 351
 352 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 353 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 354 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 355 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 356
 357 ### Project 2019-02-012 Date 28jan2020
 358
 359 * admin tasks
 360 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 361