openpower.mdwn

   1 # OpenPOWER
   2
   3 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
   4 This evolved to a specification known as the OpenPOWER ISA. In 2019 IBM made the OpenPOWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors
   5 happen to implement what is now known as the OpenPOWER ISA. The names
   6 POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel
   7 i5, i7, i9 etc. and are frequently conflated with versions of the OpenPOWER ISA (v2.08, v3.0, v3.1).
   8
   9 Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER, thanks to IBM's involvement,
  10 is designed for high performance.
  11
  12 See wikipedia page
  13 <https://en.m.wikipedia.org/wiki/Power_ISA>
  14
  15 very useful resource describing all assembly instructions
  16 <https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set>
  17
  18 # Evaluation
  19
  20 EULA released! looks good.
  21 <https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/>
  22
  23 # Links
  24
  25 * OpenPOWER Membership
  26   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
  27 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  28 * [[openpower/isatables]]
  29 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  30 * [[openpower/gem5]]
  31 * [[openpower/sv]]
  32 * [[openpower/simd_vsx]]
  33 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  34 * [[openpower/pearpc]]
  35 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  36 * [[3d_gpu/architecture/decoder]]
  37 * <https://forums.raptorcs.com/>
  38 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  39 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  40 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  41 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  42 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  43
  44 PowerPC Unit Tests
  45
  46 * <https://github.com/lioncash/DolphinPPCTests>
  47 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  48
  49 Summary
  50
  51 * FP32 is converted to FP64. Requires SimpleV to be active.
  52 * FP16 needed
  53 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  54 * FCVT between 16/32/64 needed
  55 * c++11 atomics not very efficient
  56 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  57 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  58
  59 # What we are *NOT* doing:
  60
  61 * A processor that is fundamentally incompatible (noncompliant) with Power.
  62  (**escape-sequencing requires and guarantees compatibility**).
  63 * Opcode 4 Signal Processing (SPE)
  64 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  65 * Avoidable legacy opcodes
  66 * SIMD. it's awful.
  67
  68 # SimpleV
  69
  70 see [[openpower/sv]].
  71 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  72 register files to "a sequence of elements".  The **one** instruction
  73 (an unmodified **scalar** instruction) is interpreted as a *hardware
  74 for-loop* that issues **multiple** internal instructions with
  75 sequentially-incrementing register numbers.
  76
  77 Thus it is completely unnecessary to add any vector opcodes - at all -
  78 saving hugely on both hardware and compiler development time when
  79 the concept is dropped on top of a pre-existing ISA.
  80
  81 ## Condition Registers
  82
  83 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  84
  85 ## Carry
  86
  87 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
  88
  89 # Integer Overflow / Saturate
  90
  91 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  92
  93 # atomics
  94
  95 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  96
  97 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  98
  99 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
 100
 101 # FP16
 102
 103 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
 104
 105 Usually done with a fmt field, 2 bit, last one is FP128
 106
 107 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
 108
 109 # Escape Sequencing
 110
 111 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
 112 from OpenPower Foundation.
 113
 114 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 115 (including for and by OpenPower Foundation)
 116
 117 ## Branches in namespaces
 118
 119 Branches are fine as it is up to the compiler to decide whether to let the
 120 ISAMUX/NS/escape-sequence countdown run out.
 121
 122 This is all a software / compiler / ABI issue.
 123
 124 ## Function calls in namespaces
 125
 126 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 127
 128 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 129
 130 All of this is a software issue (compiler / ABI).
 131
 132 # Compressed, 48, 64, VBLOCK
 133
 134 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 135
 136 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 137 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 138
 139 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 140 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 141 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 142 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 143
 144 Note that this requires BE instruction encoding (separate from
 145 data BE/LE encoding).  BE encoding always places the major opcode in
 146 the first 2 bytes of the raw (uninterpreted) sequential instruction
 147 byte stream.
 148
 149 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 150 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 151 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 152
 153 It is not possible to distinguish LE-encoded 32-bit instructions
 154 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 155 instructions, the opcode falls into:
 156
 157 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 158   byte stream for a 32-bit instruction
 159 * bytes 0 and 1 for a 16-bit Compressed instruction
 160 * bytes 4 and 5 for a 48-bit SVP P48
 161 * bytes 6 and 7 for a 64-bit SVP P64
 162
 163 Clearly this is an impossible situation, therefore BE is the only
 164 option.  Note: *this is completely separate from BE/LE for data*
 165
 166 # Compressed 16
 167
 168 Further "escape-sequencing".
 169
 170 Only 11 bits available. Idea: have "pages" where one instruction selects
 171 the page number. It also specifies for how long that page is activated
 172 (terminated on a branch)
 173
 174 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 175
 176 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 177
 178 Store activation length in a CSR.
 179
 180 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 181
 182 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 183
 184 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 185
 186 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 187