openpower/isans_letter.mdwn

   1
   2 # Letter regarding ISAMUX / NS
   3
   4 * Revision 1.0: Sat 18 Apr 2020
   5
   6 ## Why has Libre-SOC chosen PowerPC ?
   7
   8 For a hybrid CPU-VPU-GPU, intended for mass-volume adoption in tablets,
   9 netbooks, chromebooks and industrial embedded (SBC) systems, our choice
  10 was between Nyuzi, MIAOW, RISC-V, PowerPC, MIPS and OpenRISC.
  11
  12 Of all the options, the PowerPC architecture is more complete and far more
  13 mature.  It also has a deeper adoption by Linux distributions.
  14
  15 Following IBM's release of the Power Architecture instruction set to the
  16 Linux Foundation in August 2019 the barrier to using it is no more than
  17 that of using RISC-V.  We are encouraged that the OpenPOWER Foundation is
  18 supportive of what we are doing and helping, e.g by putting us in touch
  19 with people who can help us.
  20
  21 ## Summary
  22
  23 * We propose the standardisation of the way that the PowerPC Instruction
  24   Set Architecture (PPC ISA) is extended, enabling many different flavours
  25   within a well supported family to co-exist, long-term, without conflict,
  26   right across the board.
  27 * This is about more than just our project. Our proposals will facilitate
  28   the use of PPC in novel or niche applications without breaking the PPC
  29   ISA into incompatible islands.
  30 * PPC will gain a competitive market advantage by removing the need
  31   for separate VPU or GPU functions in RTL or ASICs thus enabling lower
  32   cost systems.  Libre-SOC's project is to extend the PPC to integrate
  33   the GPU and VPU functionality directly as part of the PPC ISA (example:
  34   Broadcom VideoCore IV being based around extensions to an ARC core).
  35 * Libre-SOC's extensions will be easily adopted, as the standard GNU/Linux
  36   distributions will very deliberately run unmodified on our ISA,
  37   including full compatibility with illegal instruction trap requirements.
  38
  39 ## One CPU multiple ISAs
  40
  41 This is a quick overview of the way that we would like to add changes
  42 that we are proposing to the PowerPC instruction set (ISA).  It is based on
  43 a Open Standardisation of the way that existing "mode switches",
  44 already found in the POWER instruction set, are added:
  45
  46 * FPSCR's "NI" bit, setting non-IEEE754 FP mode
  47 * MSR's "LE" bit (and associated HILE bit), setting little-endian mode
  48 * MSR's "SF" bit, setting either 32-bit or 64-bit mode
  49 * PCR's "compatibility" bits 60-62, V2.05 V2.06 V2.07 mode
  50
  51 [It is well-noted that unless each "mode switch" bit is set, any
  52 alternative (additional) instructions (and functionality) are completely
  53 inaccessible, and will result in "illegal instruction" traps being thrown.
  54 This is recognised as being critically important.]
  55
  56 These bits effectively create multiple, incompatible run-time switchable ISAs
  57 within one CPU.  They are selectable for the needs of the individual
  58 program (or OS) being run.
  59
  60 All of these bits are set by an instruction, that, once set, radically
  61 changes the entire behaviour and characteristics of subsequent instructions.
  62
  63 With these (and other) long-established precedents already in POWER,
  64 there is therefore essentially conceptually nothing new about what we
  65 propose: we simply seek that the process by which such "switching" is
  66 added is formalised and standardised, such that we (and others, including
  67 IBM itself) have a clear, well-defined standards-non-disruptive, atomic
  68 and non-intrusive path to extend the POWER ISA for use in markets that
  69 it presently cannot enter.
  70
  71 We advocate that some of "mode-setting" (escape-sequencing) bits be
  72 binary encoded, some unary encoded, and that some space marked for
  73 "offical" use, some "experimental", some "custom" and some "reserved".
  74 The available space in a suitably-chosen SPR to be formalised, and
  75 recommend the OpenPOWER Foundation be given the IANA-like role in
  76 atomically allocating mode bits.
  77
  78 Instructions that we need to add, which are a normal part of GPUs,
  79 include ATAN2, LOG, NORMALISE, YUV2RGB, Khronos Compliance FP mode
  80 (different from both IEEE754 and "NI" mode), and many more.  Many of
  81 these may turn out to be useful in a wider context: they however need
  82 to be fully isolated behind "mode-setting".
  83
  84 Some mode-setting instructions are privileged, ie can only be set by
  85 the kernel (eg 32 or 64 bit mode). Most of the escape sequences that we
  86 propose will be (have to be) usable without the need for an expensive
  87 system call overhead (because some of the instructions needed will be
  88 in extremely tight inner loops).
  89
  90 # About Libre-SOC Commercial Project
  91
  92 The Libre-SOC Commercial Product is a hybrid GPU-GPU-VPU intended for
  93 mass-volume production.  There is no separate GPU, because the CPU
  94 *is* the GPU.  There is no separate VPU, because the CPU *is* the GPU.
  95 There is not even a separate pipeline: the CPU pipelines *are* the
  96 GPU and VPU pipelines.
  97
  98 Closest equivalents include the ARC core (which has VPU extensions and
  99 3D extensions in the form of Broadcom's VideoCore IV) and the ICubeCorp
 100 IC3128.  Both are considered "hybrid" CPU-GPU-VPU processors.
 101
 102 "Normal" Commercial GPUs are entirely separate processors.  The development
 103 cost and complexity purely in terms of Software Drivers alone is immense.
 104 We reject that approach (and as a small team we do not have the resources
 105 anyway).
 106
 107 With the project being Libre - not proprietary and secretive and never
 108 to be published, ever - it is no good having the extensions as "custom"
 109 because "custom" is specifically for the cases where the augmented
 110 toolchain is never, under any circumstances, published and made public by
 111 the proprietary company (and would never be accepted upstream anyway).
 112 For business commercial reasons, Libre-SOC is the total opposite of this
 113 proprietary, secretive approach.
 114
 115 Therefore, to meet our business objectives:
 116
 117 * As shown from Nyuzi and Larrabee, although ideally suited to high
 118   performance compute tasks, a "traditional" general-purpose full
 119   IEEE754-compliant Vector ISA (such as that in POWER9) is not an adequate
 120   basis for a commercially competitive GPU.  Nyuzi's conclusion is that
 121   using such general-purpose Vector ISAs results in reaching only 25%
 122   performance (or requiring 4-fold increase in power consumption) to
 123   achieve par with current commercial-grade GPUs.
 124 * We are not going the "traditional" (separate custom GPU) route because
 125   it is not practical for a new team to design hardware and spend 8+
 126   man-years on massively complex inter-processor driver development as well
 127 * We cannot meet our objectives with a "custom extension" because the
 128   financial burden on our team to maintain a total hard fork of not just
 129   toolchains, but also entire GNU/Linux Distros, is highly undesirable,
 130   and completely impractical (and Redhat would strongly object anyway)
 131 * We cannot "go ahead anyway" because to do so would be highly irresponsible
 132   and cause massive disruption to the POWER community.
 133
 134 With all impractical options eliminated the only remaining responsible
 135 option is to extend the POWER ISA in an atomically-managed (IANA-style)
 136 formal fashion, whilst (critically and absolutely essentially) always
 137 providing a PCR compatibility mode that is fully POWER compliant, including
 138 all illegal instruction traps.
 139