openpower/isans_letter.mdwn

   1 # Letter regarding ISAMUX / NS
   2
   3 * Revision 0.0 draft: 03 Mar 2020
   4 * Revision 0.1 addw review: 16 Apr 2020
   5 * Revision 0.9 pre-final: 18 Apr 2020
   6 * Revision 0.91 mention dual ISA: 22 Apr 2020
   7 * Revision 0.92 mention countdown idea: 22 Apr 2020
   8
   9 ## Why has Libre-SOC chosen PowerPC ?
  10
  11 For a hybrid CPU-VPU-GPU, intended for mass-volume adoption in tablets,
  12 netbooks, chromebooks and industrial embedded (SBC) systems, our choice
  13 was between Nyuzi, MIAOW, RISC-V, PowerPC, MIPS and OpenRISC.
  14
  15 Of all the options, the PowerPC architecture is more complete and far more
  16 mature.  It also has a deeper adoption by Linux distributions.
  17
  18 Following IBM's release of the Power Architecture instruction set to the
  19 Linux Foundation in August 2019 the barrier to using it is no more than
  20 that of using RISC-V.  We are encouraged that the OpenPOWER Foundation is
  21 supportive of what we are doing and helping, e.g by putting us in touch
  22 with people who can help us.
  23
  24 ## Summary
  25
  26 * We propose the standardisation of the way that the PowerPC Instruction
  27   Set Architecture (PPC ISA) is extended, enabling many different flavours
  28   within a well supported family to co-exist, long-term, without conflict,
  29   right across the board.
  30 * This is about more than just our project. Our proposals will facilitate
  31   the use of PPC in novel or niche applications without breaking the PPC
  32   ISA into incompatible islands.
  33 * PPC will gain a competitive market advantage by removing the need
  34   for separate VPU or GPU functions in RTL or ASICs thus enabling lower
  35   cost systems.  Libre-SOC's project is to extend the PPC to integrate
  36   the GPU and VPU functionality directly as part of the PPC ISA (example:
  37   Broadcom VideoCore IV being based around extensions to an ARC core).
  38 * Libre-SOC's extensions will be easily adopted, as the standard GNU/Linux
  39   distributions will very deliberately run unmodified on our ISA,
  40   including full compatibility with illegal instruction trap requirements.
  41
  42 ## One CPU multiple ISAs
  43
  44 This is a quick overview of the way that we would like to add changes
  45 that we are proposing to the PowerPC instruction set (ISA).  It is based on
  46 a Open Standardisation of the way that existing "mode switches",
  47 already found in the POWER instruction set, are added:
  48
  49 * FPSCR's "NI" bit, setting non-IEEE754 FP mode
  50 * MSR's "LE" bit (and associated HILE bit), setting little-endian mode
  51 * MSR's "SF" bit, setting either 32-bit or 64-bit mode
  52 * PCR's "compatibility" bits 60-62, V2.05 V2.06 V2.07 mode
  53
  54 [It is well-noted that unless each "mode switch" bit is set, any
  55 alternative (additional) instructions (and functionality) are completely
  56 inaccessible, and will result in "illegal instruction" traps being thrown.
  57 This is recognised as being critically important.]
  58
  59 These bits effectively create multiple, incompatible run-time switchable ISAs
  60 within one CPU.  They are selectable for the needs of the individual
  61 program (or OS) being run.
  62
  63 All of these bits are set by an instruction, that, once set, radically
  64 changes the entire behaviour and characteristics of subsequent instructions.
  65
  66 With these (and other) long-established precedents already in POWER,
  67 there is therefore essentially conceptually nothing new about what we
  68 propose: we simply seek that the process by which such "switching" is
  69 added is formalised and standardised, such that we (and others, including
  70 IBM itself) have a clear, well-defined standards-non-disruptive, atomic
  71 and non-intrusive path to extend the POWER ISA for use in markets that
  72 it presently cannot enter.
  73
  74 We advocate that some of "mode-setting" (escape-sequencing) bits be
  75 binary encoded, some unary encoded, and that some space marked for
  76 "offical" use, some "experimental", some "custom" and some "reserved".
  77 The available space in a suitably-chosen SPR to be formalised, and
  78 recommend the OpenPOWER Foundation be given the IANA-like role in
  79 atomically allocating mode bits.
  80
  81 We also advocate to consider reserving some bits as a "countdown" where the new mode will be enabled only for a certain *number* of instructions. This avoids an explicit need to "flip back", reducing binary code size. Note that it is not a good idea to let the counter cross a branch or other change in PC (illegal instruction trap). However traps and exceptions will need to save (and restore) the counter just as the rest of the PCR and other modeswitching bits need to be saved.
  82
  83 Instructions that we need to add, which are a normal part of GPUs,
  84 include ATAN2, LOG, NORMALISE, YUV2RGB, Khronos Compliance FP mode
  85 (different from both IEEE754 and "NI" mode), and many more.  Many of
  86 these may turn out to be useful in a wider context: they however need
  87 to be fully isolated behind "mode-setting" before being in any way
  88 considered for Standards-track formal adoption.
  89
  90 Some mode-setting instructions are privileged, i.e can only be set by
  91 the kernel (e.g 32 or 64 bit mode). Most of the escape sequences that we
  92 propose will be (have to be) usable without the need for an expensive
  93 system call overhead (because some of the instructions needed will be
  94 in extremely tight inner loops).
  95
  96 # About Libre-SOC Commercial Project
  97
  98 The Libre-SOC Commercial Product is a hybrid GPU-GPU-VPU intended for
  99 mass-volume production.  There is no separate GPU, because the CPU
 100 *is* the GPU.  There is no separate VPU, because the CPU *is* the GPU.
 101 There is not even a separate pipeline: the CPU pipelines *are* the
 102 GPU and VPU pipelines.
 103
 104 Closest equivalents include the ARC core (which has VPU extensions and
 105 3D extensions in the form of Broadcom's VideoCore IV) and the ICubeCorp
 106 IC3128.  Both are considered "hybrid" CPU-GPU-VPU processors.
 107
 108 "Normal" Commercial GPUs are entirely separate processors.  The development
 109 cost and complexity purely in terms of Software Drivers alone is immense.
 110 We reject that approach (and as a small team we do not have the resources
 111 anyway).
 112
 113 With the project being Libre - not proprietary and secretive and never
 114 to be published, ever - it is no good having the extensions as "custom"
 115 because "custom" is specifically for the cases where the augmented
 116 toolchain is never, under any circumstances, published and made public by
 117 the proprietary company (and would never be accepted upstream anyway).
 118 For business commercial reasons, Libre-SOC is the total opposite of this
 119 proprietary, secretive approach.
 120
 121 Therefore, to meet our business objectives:
 122
 123 * As shown from Nyuzi and Larrabee, although ideally suited to high
 124   performance compute tasks, a "traditional" general-purpose full
 125   IEEE754-compliant Vector ISA (such as that in POWER9) is not an adequate
 126   basis for a commercially competitive GPU.  Nyuzi's conclusion is that
 127   using such general-purpose Vector ISAs results in reaching only 25%
 128   performance (or requiring 4-fold increase in power consumption) to
 129   achieve par with current commercial-grade GPUs.
 130 * We are not going the "traditional" (separate custom GPU) route because
 131   it is not practical for a new team to design hardware and spend 8+
 132   man-years on massively complex inter-processor driver development as well
 133 * We cannot meet our objectives with a "custom extension" because the
 134   financial burden on our team to maintain a total hard fork of not just
 135   toolchains, but also entire GNU/Linux Distros, is highly undesirable,
 136   and completely impractical (we know for certain that Redhat would
 137   strongly object to any efforts to hard-fork Fedora)
 138 * We could invent our own custom GPU instruction set (or use and extend an existing one, to save a man-decade on toolchain development) however even to switch over to that "Dual ISA" GPU instruction set in the next clock cycle *still requires a PCR modeswitch bit* in order to avoid needing a full Inter-Processor Bus Architecture like on "traditional" GPUs.
 139 * If extending any instruction set, rather than have a Dual ISA (which needs the PCR modeswitch bit to access it) we would rather extend POWER.
 140 * We cannot "go ahead anyway" because to do so would be highly irresponsible
 141   and cause massive disruption to the POWER community.
 142
 143 With all impractical options eliminated the only remaining responsible
 144 option is to extend the POWER ISA in an atomically-managed (IANA-style)
 145 formal fashion, whilst (critically and absolutely essentially) always
 146 providing a PCR compatibility mode that is fully POWER compliant, including
 147 all illegal instruction traps.
 148