openpower/sv/bitmanip.mdwn

   1 [[!tag standards]]
   2
   3 # Implementation Log
   4
   5 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
   6 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
   7 * remove Rc=1 from ternlog due to conflicts in encoding as well
   8   as saving space <https://bugs.libre-soc.org/show_bug.cgi?id=753#c5>
   9
  10 # bitmanipulation
  11
  12 **DRAFT STATUS**
  13
  14 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.  Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
  15 Vectorisation Context is provided by [[openpower/sv]].
  16
  17 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years).  Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
  18
  19 ternlogv is experimental and is the only operation that may be considered a "Packed SIMD".  It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs.  Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
  20
  21 general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science.  however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added.  The expectation is that these operations would all be covered by the same pipeline.
  22
  23 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
  24 the [[sv/av_opcodes]] as well as [[sv/setvl]]
  25
  26 Useful resource:
  27
  28 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
  29 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
  30
  31 # summary
  32
  33 minor opcode allocation
  34
  35     |  28.30 |31| name      |
  36     | ------ |--| --------- |
  37     |   00   |0 | ternlogi  |
  38     |  000   |1 | ternlog   |
  39     |  100   |1 | reserved  |
  40     |  010   |Rc| bitmask   |
  41     |  011   |Rc| gf*       |
  42     |  101   |1 | ternlogv  |
  43     |  101   |0 | ternlogcr |
  44     |  110   |Rc| 1/2-op    |
  45     |  111   |Rc| 3-op      |
  46
  47 1-op and variants
  48
  49 | dest | src1 | subop | op       |
  50 | ---- | ---- | ----- | -------- |
  51 | RT   | RA   | ..    | bmatflip |
  52
  53 2-op and variants
  54
  55 | dest | src1 | src2 | subop | op       |
  56 | ---- | ---- | ---- | ----- | -------- |
  57 | RT   | RA   | RB   | or    | bmatflip |
  58 | RT   | RA   | RB   | xor   | bmatflip |
  59 | RT   | RA   | RB   |       | grev  |
  60 | RT   | RA   | RB   |       | clmul*  |
  61 | RT   | RA   | RB   |       | gorc |
  62 | RT   | RA   | RB   | shuf  | shuffle |
  63 | RT   | RA   | RB   | unshuf| shuffle |
  64 | RT   | RA   | RB   | width | xperm  |
  65 | RT   | RA   | RB   | type | minmax |
  66 | RT   | RA   | RB   |      | av abs avgadd  |
  67 | RT   | RA   | RB   | type | vmask ops |
  68 | RT   | RA   | RB   |  |  |
  69
  70 3 ops
  71
  72 * bitmask set/extract
  73 * ternlog bitops
  74 * GF
  75
  76 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
  77 | -- | -- | --- | --- | ----- | -------- |--| ------ |
  78 | NN | RT | RA  | RB  | RC    | mode 000 |1 | ternlog |
  79 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |0 | ternlogi |
  80 | NN | RS | RA  | RB  | RC    | 00  011  |Rc| gfmul |
  81 | NN | RS | RA  | RB  | RC    | 01  011  |Rc| gfadd |
  82 | NN | RT | RA  | RB  | deg   | 10  011  |Rc| gfinv |
  83 | NN | RS | RA  | RB  | deg   | 11  011  |Rc| gfmuli |
  84 | NN | RS | RA  | RB  | deg   | 11  111  |Rc| gfaddi |
  85
  86 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
  87 | -- | -- | --- | ----- | ---- | ----- |--| ------ |
  88 | NN | RT | RA  | imm   | mask | 101   |1 | ternlogv |
  89
  90 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
  91 | -- | -- | --- | --- |- |-----|----- | -----|--| -------|
  92 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 | ternlogcr |
  93
  94 ops (note that av avg and abs as well as vec scalar mask
  95 are included here)
  96
  97 | 0.5|6.10|11.15|16.20| 21.22 | 23 | 24....30 |31| name |
  98 | -- | -- | --- | --- | ----- | -- | -------- |--| ---- |
  99 | NN | RA | RB  |     |       | 0  | 0000 110 |Rc| rsvd   |
 100 | NN | RA | RB  | RC  | itype | 1  | 0000 110 |Rc| xperm |
 101 | NN | RA | RB  | RC  | itype | 0  | 0100 110 |Rc| minmax |
 102 | NN | RA | RB  | RC  |   00  | 1  | 0100 110 |Rc| av avgadd |
 103 | NN | RA | RB  | RC  |   01  | 1  | 0100 110 |Rc| av abs |
 104 | NN | RA | RB  |     |   10  | 1  | 0100 110 |Rc| rsvd |
 105 | NN | RA | RB  |     |   11  | 1  | 0100 110 |Rc| rsvd |
 106 | NN | RA | RB  | sh  | itype | SH | 1000 110 |Rc| bmopsi |
 107 | NN | RA | RB  |     |       |    | 1100 110 |Rc| rsvd |
 108 | NN | RA | RB  |     |       | 1  | 0001 110 |Rc| rsvd |
 109 | NN | RA | RB  | RC  |   00  | 0  | 0001 110 |Rc| vec sbfm |
 110 | NN | RA | RB  | RC  |   01  | 0  | 0001 110 |Rc| vec sofm |
 111 | NN | RA | RB  | RC  |   10  | 0  | 0001 110 |Rc| vec sifm |
 112 | NN | RA | RB  | RC  |   11  | 0  | 0001 110 |Rc| vec cprop |
 113 | NN | RA | RB  |     |       | 0  | 0101 110 |Rc| rsvd |
 114 | NN | RA | RB  | RC  | 00    | 0  | 0010 110 |Rc| gorc |
 115 | NN | RA | RB  | sh  | 00    | SH | 1010 110 |Rc| gorci |
 116 | NN | RA | RB  | RC  | 00    | 0  | 0110 110 |Rc| gorcw |
 117 | NN | RA | RB  | sh  | 00    | 0  | 1110 110 |Rc| gorcwi |
 118 | NN | RA | RB  | RC  | 00    | 1  | 1110 110 |Rc| bmator  |
 119 | NN | RA | RB  | RC  | 01    | 0  | 0010 110 |Rc| grev |
 120 | NN | RA | RB  | RC  | 01    | 1  | 0010 110 |Rc| clmul |
 121 | NN | RA | RB  | sh  | 01    | SH | 1010 110 |Rc| grevi |
 122 | NN | RA | RB  | RC  | 01    | 0  | 0110 110 |Rc| grevw |
 123 | NN | RA | RB  | sh  | 01    | 0  | 1110 110 |Rc| grevwi |
 124 | NN | RA | RB  | RC  | 01    | 1  | 1110 110 |Rc| bmatxor   |
 125 | NN | RA | RB  | RC  | 10    | 0  | 0010 110 |Rc| shfl |
 126 | NN | RA | RB  | sh  | 10    | SH | 1010 110 |Rc| shfli |
 127 | NN | RA | RB  | RC  | 10    | 0  | 0110 110 |Rc| shflw |
 128 | NN | RA | RB  | RC  | 10    |    | 1110 110 |Rc| rsvd   |
 129 | NN | RA | RB  | RC  | 11    | 0  | 1110 110 |Rc| clmulr  |
 130 | NN | RA | RB  | RC  | 11    | 1  | 1110 110 |Rc| clmulh  |
 131 | NN |    |     |     |       |    | --11 110 |Rc| setvl  |
 132
 133 # bit to byte permute
 134
 135 similar to matrix permute in RV bitmanip, which has XOR and OR variants
 136
 137     do j = 0 to 7
 138       do k = 0 to 7
 139          b = VSR[VRB+32].dword[i].byte[k].bit[j]
 140          VSR[VRT+32].dword[i].byte[j].bit[k] = b
 141
 142 # int min/max
 143
 144 signed and unsigned min/max for integer.  this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned.  when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
 145
 146 signed/unsigned min/max gives more flexibility.
 147
 148 ```
 149 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
 150 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
 151 }
 152 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
 153 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
 154 }
 155 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
 156 { return rs1 < rs2 ? rs1 : rs2;
 157 }
 158 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
 159 { return rs1 > rs2 ? rs1 : rs2;
 160 }
 161 ```
 162
 163
 164 # ternlog bitops
 165
 166 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
 167
 168 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
 169
 170 ## ternlogi
 171
 172 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 173 | -- | -- | --- | --- | ----- | -------- |--|
 174 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |0 |
 175
 176     for i in range(64):
 177         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 178         RT[i] = (imm & (1<<idx)) != 0
 179
 180 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 181
 182 ## ternlog
 183
 184 a 4 operand variant which becomes more along the lines of an FPGA:
 185
 186 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
 187 | -- | -- | --- | --- | --- | -------- |--|
 188 | NN | RT | RA  | RB  | RC  | mode 100 |1 |
 189
 190     for i in range(64):
 191         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 192         RT[i] = (RC & (1<<idx)) != 0
 193
 194 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
 195 3 modes.
 196
 197 ## ternlogv
 198
 199 also, another possible variant involving swizzle and vec4:
 200
 201 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
 202 | -- | -- | --- | ----- | ---- | ----- |--|
 203 | NN | RT | RA  | imm   | mask | 101   |1 |
 204
 205     for i in range(8):
 206         idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
 207         res = (imm & (1<<idx)) != 0
 208         for j in range(3):
 209              if mask[j]: RT[i+j*8] = res
 210
 211 ## ternlogcr
 212
 213 another mode selection would be CRs not Ints.
 214
 215 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|
 216 | -- | -- | --- | --- |- |-----|----- | -----|--|
 217 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 |
 218
 219     for i in range(4):
 220         if not mask[i] continue
 221         idx = crregs[BA][i] << 2 |
 222               crregs[BB][i] << 1 |
 223               crregs[BC][i]
 224         crregs[BA][i] = (imm & (1<<idx)) != 0
 225
 226 ## cmix
 227
 228 based on RV bitmanip, covered by ternlog bitops
 229
 230 ```
 231 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
 232     return (RA & RB) | (RC & ~RB);
 233 }
 234 ```
 235
 236
 237 # bitmask set
 238
 239 based on RV bitmanip singlebit set, instruction format similar to shift
 240 [[isa/fixedshift]].  bmext is actually covered already (shift-with-mask rldicl but only immediate version).
 241 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
 242
 243 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate.  for the immediate version this does not matter, so a bmexti is not required.
 244 bmrev however there is no direct equivalent and consequently a bmrevi is required.
 245
 246 bmset (register for mask amount) is particularly useful for creating
 247 predicate masks where the length is a dynamic runtime quantity.
 248 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
 249
 250 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 251 | -- | -- | --- | --- | --- | ------- |--| ----- |
 252 | NN | RT | RA  | RB  | RC  | mode 010 |Rc| bm*   |
 253 | NN | RT | RA  | RB  | RC  | 0 1  111 |Rc| bmrev |
 254
 255
 256 ```
 257 uint_xlen_t bmset(RA, RB, sh)
 258 {
 259     int shamt = RB & (XLEN - 1);
 260     mask = (2<<sh)-1;
 261     return RA | (mask << shamt);
 262 }
 263
 264 uint_xlen_t bmclr(RA, RB, sh)
 265 {
 266     int shamt = RB & (XLEN - 1);
 267     mask = (2<<sh)-1;
 268     return RA & ~(mask << shamt);
 269 }
 270
 271 uint_xlen_t bminv(RA, RB, sh)
 272 {
 273     int shamt = RB & (XLEN - 1);
 274     mask = (2<<sh)-1;
 275     return RA ^ (mask << shamt);
 276 }
 277
 278 uint_xlen_t bmext(RA, RB, sh)
 279 {
 280     int shamt = RB & (XLEN - 1);
 281     mask = (2<<sh)-1;
 282     return mask & (RA >> shamt);
 283 }
 284 ```
 285
 286 bitmask extract with reverse.  can be done by bitinverting all of RA and getting bits of RA from the opposite end.
 287
 288 ```
 289 msb = rb[5:0];
 290 rev[0:msb] = ra[msb:0];
 291 rt = ZE(rev[msb:0]);
 292
 293 uint_xlen_t bmextrev(RA, RB, sh)
 294 {
 295     int shamt = (RB & (XLEN - 1));
 296     shamt = (XLEN-1)-shamt;  # shift other end
 297     bra = bitreverse(RA)     # swap LSB-MSB
 298     mask = (2<<sh)-1;
 299     return mask & (bra >> shamt);
 300 }
 301 ```
 302
 303 | 0.5|6.10|11.15|16.20|21.26| 27..30  |31| name   |
 304 | -- | -- | --- | --- | --- | ------- |--| ------ |
 305 | NN | RT | RA  | RB  | sh  | 0   111 |Rc| bmrevi |
 306
 307
 308
 309 # grev
 310
 311 based on RV bitmanip
 312
 313 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
 314
 315 ```
 316 uint64_t grev64(uint64_t RA, uint64_t RB)
 317 {
 318     uint64_t x = RA;
 319     int shamt = RB & 63;
 320     if (shamt & 1) x = ((x &  0x5555555555555555LL) <<  1) |
 321                         ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);
 322     if (shamt & 2) x = ((x &  0x3333333333333333LL) <<  2) |
 323                         ((x & 0xCCCCCCCCCCCCCCCCLL) >>  2);
 324     if (shamt & 4) x = ((x &  0x0F0F0F0F0F0F0F0FLL) <<  4) |
 325                         ((x & 0xF0F0F0F0F0F0F0F0LL) >>  4);
 326     if (shamt & 8) x = ((x &  0x00FF00FF00FF00FFLL) <<  8) |
 327                         ((x & 0xFF00FF00FF00FF00LL) >>  8);
 328     if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
 329                         ((x & 0xFFFF0000FFFF0000LL) >> 16);
 330     if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
 331                         ((x & 0xFFFFFFFF00000000LL) >> 32);
 332     return x;
 333 }
 334
 335 ```
 336
 337 # shuffle / unshuffle
 338
 339 based on RV bitmanip
 340
 341 ```
 342 uint32_t shfl32(uint32_t RA, uint32_t RB)
 343 {
 344     uint32_t x = RA;
 345     int shamt = RB & 15;
 346     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 347     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 348     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 349     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 350     return x;
 351 }
 352 uint32_t unshfl32(uint32_t RA, uint32_t RB)
 353 {
 354     uint32_t x = RA;
 355     int shamt = RB & 15;
 356     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 357     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 358     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 359     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 360     return x;
 361 }
 362
 363 uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
 364 {
 365     uint64_t x = src & ~(maskL | maskR);
 366     x |= ((src << N) & maskL) | ((src >> N) & maskR);
 367     return x;
 368 }
 369 uint64_t shfl64(uint64_t RA, uint64_t RB)
 370 {
 371     uint64_t x = RA;
 372     int shamt = RB & 31;
 373     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 374                                            0x00000000ffff0000LL, 16);
 375     if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 376                                            0x0000ff000000ff00LL, 8);
 377     if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 378                                            0x00f000f000f000f0LL, 4);
 379     if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
 380                                            0x0c0c0c0c0c0c0c0cLL, 2);
 381     if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
 382                                            0x2222222222222222LL, 1);
 383     return x;
 384 }
 385 uint64_t unshfl64(uint64_t RA, uint64_t RB)
 386 {
 387     uint64_t x = RA;
 388     int shamt = RB & 31;
 389     if (shamt &  1) x = shuffle64_stage(x, 0x4444444444444444LL,
 390                                            0x2222222222222222LL, 1);
 391     if (shamt &  2) x = shuffle64_stage(x, 0x3030303030303030LL,
 392                                            0x0c0c0c0c0c0c0c0cLL, 2);
 393     if (shamt &  4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 394                                            0x00f000f000f000f0LL, 4);
 395     if (shamt &  8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 396                                            0x0000ff000000ff00LL, 8);
 397     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 398                                            0x00000000ffff0000LL, 16);
 399     return x;
 400 }
 401 ```
 402
 403 # xperm
 404
 405 based on RV bitmanip
 406
 407 ```
 408 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
 409 {
 410     uint_xlen_t r = 0;
 411     uint_xlen_t sz = 1LL << sz_log2;
 412     uint_xlen_t mask = (1LL << sz) - 1;
 413     for (int i = 0; i < XLEN; i += sz) {
 414         uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
 415         if (pos < XLEN)
 416             r |= ((RA >> pos) & mask) << i;
 417     }
 418     return r;
 419 }
 420 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
 421 {  return xperm(RA, RB, 2); }
 422 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
 423 {  return xperm(RA, RB, 3); }
 424 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
 425 {  return xperm(RA, RB, 4); }
 426 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
 427 {  return xperm(RA, RB, 5); }
 428 ```
 429
 430 # gorc
 431
 432 based on RV bitmanip
 433
 434 ```
 435 uint32_t gorc32(uint32_t RA, uint32_t RB)
 436 {
 437     uint32_t x = RA;
 438     int shamt = RB & 31;
 439     if (shamt & 1) x |= ((x & 0x55555555) << 1)   |  ((x &  0xAAAAAAAA) >> 1);
 440     if (shamt & 2) x |= ((x & 0x33333333) << 2)   |  ((x &  0xCCCCCCCC) >> 2);
 441     if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4)   |  ((x &  0xF0F0F0F0) >> 4);
 442     if (shamt & 8) x |= ((x & 0x00FF00FF) << 8)   |  ((x &  0xFF00FF00) >> 8);
 443     if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) |  ((x &  0xFFFF0000) >> 16);
 444     return x;
 445 }
 446 uint64_t gorc64(uint64_t RA, uint64_t RB)
 447 {
 448     uint64_t x = RA;
 449     int shamt = RB & 63;
 450     if (shamt & 1) x |= ((x & 0x5555555555555555LL)   <<   1) |
 451                          ((x & 0xAAAAAAAAAAAAAAAALL)  >>  1);
 452     if (shamt & 2) x |= ((x & 0x3333333333333333LL)   <<   2) |
 453                          ((x & 0xCCCCCCCCCCCCCCCCLL)  >>  2);
 454     if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL)   <<   4) |
 455                          ((x & 0xF0F0F0F0F0F0F0F0LL)  >>  4);
 456     if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL)   <<   8) |
 457                          ((x & 0xFF00FF00FF00FF00LL)  >>  8);
 458     if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL)  << 16) |
 459                          ((x & 0xFFFF0000FFFF0000LL)  >> 16);
 460     if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL)  << 32) |
 461                          ((x & 0xFFFFFFFF00000000LL)  >> 32);
 462     return x;
 463 }
 464
 465 ```
 466
 467 # Galois Field
 468
 469 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
 470
 471 ## Multiply
 472
 473 this requires 3 parameters and a "degree"
 474
 475     RT = GFMUL(RA, RB, gfdegree, modulo=RC)
 476
 477 realistically with the degree also needing to be an immediate it should be brought down to an overwrite version:
 478
 479     RS = GFMUL(RS, RA, gfdegree, modulo=RC)
 480     RS = GFMUL(RS, RA, gfdegree=RB, modulo=RC)
 481
 482 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31|
 483 | -- | -- | --- | --- | --- | ------- |--|
 484 | NN | RS | RA  | deg | RC  | 00  011 |Rc|
 485 | NN | RS | RA  | RB  | RC  | 11  011 |Rc|
 486
 487 where the SimpleV variant may override RS-as-src differently from RS-as-dest
 488
 489
 490
 491 ```
 492 from functools import reduce
 493
 494 # constants used in the multGF2 function
 495 mask1 = mask2 = polyred = None
 496
 497 def setGF2(degree, irPoly):
 498     """Define parameters of binary finite field GF(2^m)/g(x)
 499        - degree: extension degree of binary field
 500        - irPoly: coefficients of irreducible polynomial g(x)
 501     """
 502     def i2P(sInt):
 503         """Convert an integer into a polynomial"""
 504         return [(sInt >> i) & 1
 505                 for i in reversed(range(sInt.bit_length()))]
 506
 507     global mask1, mask2, polyred
 508     mask1 = mask2 = 1 << degree
 509     mask2 -= 1
 510     polyred = reduce(lambda x, y: (x << 1) + y, i2P(irPoly)[1:])
 511
 512 def multGF2(p1, p2):
 513     """Multiply two polynomials in GF(2^m)/g(x)"""
 514     p = 0
 515     while p2:
 516         if p2 & 1:
 517             p ^= p1
 518         p1 <<= 1
 519         if p1 & mask1:
 520             p1 ^= polyred
 521         p2 >>= 1
 522     return p & mask2
 523
 524 if __name__ == "__main__":
 525
 526     # Define binary field GF(2^3)/x^3 + x + 1
 527     setGF2(3, 0b1011)
 528
 529     # Evaluate the product (x^2 + x + 1)(x^2 + 1)
 530     print("{:02x}".format(multGF2(0b111, 0b101)))
 531
 532     # Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
 533     # (used in the Advanced Encryption Standard-AES)
 534     setGF2(8, 0b100011011)
 535
 536     # Evaluate the product (x^7)(x^7 + x + 1)
 537     print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
 538 ```
 539 ## GF add
 540
 541     RS = GFADDI(RS, RA|0, gfdegree, modulo=RC)
 542     RS = GFADD(RS, RA|0, gfdegree=RB, modulo=RC)
 543
 544 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 545 | -- | -- | --- | --- | --- | ------- |--| ----- |
 546 | NN | RS | RA  | deg | RC  | 0 1  011 |Rc| gfaddi |
 547 | NN | RS | RA  | RB  | RC  | 1 1  111 |Rc| gfadd |
 548
 549 GFMOD is a pseudo-op where RA=0
 550
 551 ## gf invert
 552
 553 ```
 554 def gf_degree(a) :
 555   res = 0
 556   a >>= 1
 557   while (a != 0) :
 558     a >>= 1;
 559     res += 1;
 560   return res
 561
 562 def gf_invert(a, mod=0x1B) :
 563   v = mod
 564   g1 = 1
 565   g2 = 0
 566   j = gf_degree(a) - 8
 567
 568   while (a != 1) :
 569     if (j < 0) :
 570       a, v = v, a
 571       g1, g2 = g2, g1
 572       j = -j
 573
 574     a ^= v << j
 575     g1 ^= g2 << j
 576
 577     a %= 256  # Emulating 8-bit overflow
 578     g1 %= 256 # Emulating 8-bit overflow
 579
 580     j = gf_degree(a) - gf_degree(v)
 581
 582   return g1
 583 ```
 584
 585 ## carryless mul
 586
 587 based on RV bitmanip
 588 see https://en.wikipedia.org/wiki/CLMUL_instruction_set
 589
 590 these are GF2 operations with the modulo set to 2^degree.
 591 they are worth adding as their own non-overwrite operations
 592 (in the same pipeline).
 593
 594 ```
 595 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
 596 {
 597     uint_xlen_t x = 0;
 598     for (int i = 0; i < XLEN; i++)
 599         if ((RB >> i) & 1)
 600             x ^= RA << i;
 601     return x;
 602 }
 603 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
 604 {
 605     uint_xlen_t x = 0;
 606     for (int i = 1; i < XLEN; i++)
 607         if ((RB >> i) & 1)
 608             x ^= RA >> (XLEN-i);
 609     return x;
 610 }
 611 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
 612 {
 613     uint_xlen_t x = 0;
 614     for (int i = 0; i < XLEN; i++)
 615         if ((RB >> i) & 1)
 616             x ^= RA >> (XLEN-i-1);
 617     return x;
 618 }
 619 ```
 620
 621 # bitmatrix
 622
 623 ```
 624 uint64_t bmatflip(uint64_t RA)
 625 {
 626     uint64_t x = RA;
 627     x = shfl64(x, 31);
 628     x = shfl64(x, 31);
 629     x = shfl64(x, 31);
 630     return x;
 631 }
 632 uint64_t bmatxor(uint64_t RA, uint64_t RB)
 633 {
 634     // transpose of RB
 635     uint64_t RBt = bmatflip(RB);
 636     uint8_t u[8]; // rows of RA
 637     uint8_t v[8]; // cols of RB
 638     for (int i = 0; i < 8; i++) {
 639         u[i] = RA >> (i*8);
 640         v[i] = RBt >> (i*8);
 641     }
 642     uint64_t x = 0;
 643     for (int i = 0; i < 64; i++) {
 644         if (pcnt(u[i / 8] & v[i % 8]) & 1)
 645             x |= 1LL << i;
 646     }
 647     return x;
 648 }
 649 uint64_t bmator(uint64_t RA, uint64_t RB)
 650 {
 651     // transpose of RB
 652     uint64_t RBt = bmatflip(RB);
 653     uint8_t u[8]; // rows of RA
 654     uint8_t v[8]; // cols of RB
 655     for (int i = 0; i < 8; i++) {
 656         u[i] = RA >> (i*8);
 657         v[i] = RBt >> (i*8);
 658     }
 659     uint64_t x = 0;
 660     for (int i = 0; i < 64; i++) {
 661         if ((u[i / 8] & v[i % 8]) != 0)
 662             x |= 1LL << i;
 663     }
 664     return x;
 665 }
 666
 667 ```
 668
 669 # Already in POWER ISA
 670
 671 ## count leading/trailing zeros with mask
 672
 673 in v3.1 p105
 674
 675 ```
 676 count = 0
 677 do i = 0 to 63 if((RB)i=1) then do
 678 if((RS)i=1) then break end end count ← count + 1
 679 RA ← EXTZ64(count)
 680 ```
 681
 682 ##  bit deposit
 683
 684 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
 685
 686     do while(m < 64)
 687        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
 688           result = VSR[VRA+32].dword[i].bit[63-k]
 689           VSR[VRT+32].dword[i].bit[63-m] = result
 690           k = k + 1
 691        m = m + 1
 692
 693 ```
 694
 695 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
 696 {
 697     uint_xlen_t r = 0;
 698     for (int i = 0, j = 0; i < XLEN; i++)
 699         if ((RB >> i) & 1) {
 700             if ((RA >> j) & 1)
 701                 r |= uint_xlen_t(1) << i;
 702             j++;
 703         }
 704     return r;
 705 }
 706
 707 ```
 708
 709 # bit extract
 710
 711 other way round: identical to RV bext, found in v3.1 p196
 712
 713 ```
 714 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
 715 {
 716     uint_xlen_t r = 0;
 717     for (int i = 0, j = 0; i < XLEN; i++)
 718         if ((RB >> i) & 1) {
 719             if ((RA >> i) & 1)
 720                 r |= uint_xlen_t(1) << j;
 721             j++;
 722         }
 723     return r;
 724 }
 725 ```
 726
 727 # centrifuge
 728
 729 found in v3.1 p106 so not to be added here
 730
 731 ```
 732 ptr0 = 0
 733 ptr1 = 0
 734 do i = 0 to 63
 735     if((RB)i=0) then do
 736        resultptr0 = (RS)i
 737     end
 738     ptr0 = ptr0 + 1
 739     if((RB)63-i==1) then do
 740         result63-ptr1 = (RS)63-i
 741     end
 742     ptr1 = ptr1 + 1
 743 RA = result
 744 ```
 745