openpower/sv/bitmanip.mdwn

   1 [[!tag standards]]
   2
   3 # Implementation Log
   4
   5 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
   6 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
   7 * remove Rc=1 from ternlog due to conflicts in encoding as well
   8   as saving space <https://bugs.libre-soc.org/show_bug.cgi?id=753#c5>
   9
  10 # bitmanipulation
  11
  12 **DRAFT STATUS**
  13
  14 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.  Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
  15 Vectorisation Context is provided by [[openpower/sv]].
  16
  17 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years).  Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
  18
  19 ternlogv is experimental and is the only operation that may be considered a "Packed SIMD".  It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs.  Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
  20
  21 general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science.  however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added.  The expectation is that these operations would all be covered by the same pipeline.
  22
  23 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
  24 the [[sv/av_opcodes]] as well as [[sv/setvl]]
  25
  26 Useful resource:
  27
  28 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
  29 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
  30
  31 # summary
  32
  33 minor opcode allocation
  34
  35     |  28.30 |31| name      |
  36     | ------ |--| --------- |
  37     |   00   |0 | ternlogi  |
  38     |  000   |1 | ternlog   |
  39     |  100   |1 | reserved  |
  40     |  010   |Rc| bitmask   |
  41     |  011   |Rc| gf*       |
  42     |  101   |1 | ternlogv  |
  43     |  101   |0 | ternlogcr |
  44     |  110   |Rc| 1/2-op    |
  45     |  111   |Rc| 3-op      |
  46
  47 1-op and variants
  48
  49 | dest | src1 | subop | op       |
  50 | ---- | ---- | ----- | -------- |
  51 | RT   | RA   | ..    | bmatflip |
  52
  53 2-op and variants
  54
  55 | dest | src1 | src2 | subop | op       |
  56 | ---- | ---- | ---- | ----- | -------- |
  57 | RT   | RA   | RB   | or    | bmatflip |
  58 | RT   | RA   | RB   | xor   | bmatflip |
  59 | RT   | RA   | RB   |       | grev  |
  60 | RT   | RA   | RB   |       | clmul*  |
  61 | RT   | RA   | RB   |       | gorc |
  62 | RT   | RA   | RB   | shuf  | shuffle |
  63 | RT   | RA   | RB   | unshuf| shuffle |
  64 | RT   | RA   | RB   | width | xperm  |
  65 | RT   | RA   | RB   | type | minmax |
  66 | RT   | RA   | RB   |      | av abs avgadd  |
  67 | RT   | RA   | RB   | type | vmask ops |
  68 | RT   | RA   | RB   |  |  |
  69
  70 3 ops
  71
  72 * bitmask set/extract
  73 * ternlog bitops
  74 * GF
  75
  76 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
  77 | -- | -- | --- | --- | ----- | -------- |--| ------ |
  78 | NN | RT | RA  | RB  | RC    | mode 000 |1 | ternlog |
  79 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |0 | ternlogi |
  80 | NN | RS | RA  | RB  | RC    | 00  011  |Rc| gfmul |
  81 | NN | RS | RA  | RB  | RC    | 01  011  |Rc| gfadd |
  82 | NN | RT | RA  | RB  | deg   | 10  011  |Rc| gfinv |
  83 | NN | RS | RA  | RB  | deg   | 11  011  |Rc| gfmuli |
  84 | NN | RS | RA  | RB  | deg   | 11  111  |Rc| gfaddi |
  85
  86 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
  87 | -- | -- | --- | ----- | ---- | ----- |--| ------ |
  88 | NN | RT | RA  | imm   | mask | 101   |1 | ternlogv |
  89
  90 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
  91 | -- | -- | --- | --- |- |-----|----- | -----|--| -------|
  92 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 | ternlogcr |
  93
  94 ops (note that av avg and abs as well as vec scalar mask
  95 are included here)
  96
  97 | 0.5|6.10|11.15|16.20| 21.22 | 23 | 24....30 |31| name |
  98 | -- | -- | --- | --- | ----- | -- | -------- |--| ---- |
  99 | NN | RA | RB  |     |       | 0  | 0000 110 |Rc| rsvd   |
 100 | NN | RA | RB  | RC  | itype | 1  | 0000 110 |Rc| xperm |
 101 | NN | RA | RB  | RC  | itype | 0  | 0100 110 |Rc| minmax |
 102 | NN | RA | RB  | RC  |   00  | 1  | 0100 110 |Rc| av avgadd |
 103 | NN | RA | RB  | RC  |   01  | 1  | 0100 110 |Rc| av abs |
 104 | NN | RA | RB  |     |   10  | 1  | 0100 110 |Rc| rsvd |
 105 | NN | RA | RB  |     |   11  | 1  | 0100 110 |Rc| rsvd |
 106 | NN | RA | RB  | sh  | itype | SH | 1000 110 |Rc| bmopsi |
 107 | NN | RA | RB  |     |       |    | 1100 110 |Rc| rsvd |
 108 | NN | RA | RB  |     |       | 1  | 0001 110 |Rc| rsvd |
 109 | NN | RA | RB  | RC  |   00  | 0  | 0001 110 |Rc| vec sbfm |
 110 | NN | RA | RB  | RC  |   01  | 0  | 0001 110 |Rc| vec sofm |
 111 | NN | RA | RB  | RC  |   10  | 0  | 0001 110 |Rc| vec sifm |
 112 | NN | RA | RB  | RC  |   11  | 0  | 0001 110 |Rc| vec cprop |
 113 | NN | RA | RB  |     |       | 0  | 0101 110 |Rc| rsvd |
 114 | NN | RA | RB  | RC  | 00    | 0  | 0010 110 |Rc| gorc |
 115 | NN | RA | RB  | sh  | 00    | SH | 1010 110 |Rc| gorci |
 116 | NN | RA | RB  | RC  | 00    | 0  | 0110 110 |Rc| gorcw |
 117 | NN | RA | RB  | sh  | 00    | 0  | 1110 110 |Rc| gorcwi |
 118 | NN | RA | RB  | RC  | 00    | 1  | 1110 110 |Rc| bmator  |
 119 | NN | RA | RB  | RC  | 01    | 0  | 0010 110 |Rc| grev |
 120 | NN | RA | RB  | RC  | 01    | 1  | 0010 110 |Rc| clmul |
 121 | NN | RA | RB  | sh  | 01    | SH | 1010 110 |Rc| grevi |
 122 | NN | RA | RB  | RC  | 01    | 0  | 0110 110 |Rc| grevw |
 123 | NN | RA | RB  | sh  | 01    | 0  | 1110 110 |Rc| grevwi |
 124 | NN | RA | RB  | RC  | 01    | 1  | 1110 110 |Rc| bmatxor   |
 125 | NN | RA | RB  | RC  | 10    | 0  | 0010 110 |Rc| shfl |
 126 | NN | RA | RB  | sh  | 10    | SH | 1010 110 |Rc| shfli |
 127 | NN | RA | RB  | RC  | 10    | 0  | 0110 110 |Rc| shflw |
 128 | NN | RA | RB  | RC  | 10    |    | 1110 110 |Rc| rsvd   |
 129 | NN | RA | RB  | RC  | 11    | 0  | 1110 110 |Rc| clmulr  |
 130 | NN | RA | RB  | RC  | 11    | 1  | 1110 110 |Rc| clmulh  |
 131 | NN |    |     |     |       |    | --11 110 |Rc| setvl  |
 132
 133 # count leading/trailing zeros with mask
 134
 135 in v3.1 p105
 136
 137 ```
 138 count = 0
 139 do i = 0 to 63 if((RB)i=1) then do
 140 if((RS)i=1) then break end end count ← count + 1
 141 RA ← EXTZ64(count)
 142 ```
 143
 144 # bit to byte permute
 145
 146 similar to matrix permute in RV bitmanip, which has XOR and OR variants
 147
 148     do j = 0 to 7
 149       do k = 0 to 7
 150          b = VSR[VRB+32].dword[i].byte[k].bit[j]
 151          VSR[VRT+32].dword[i].byte[j].bit[k] = b
 152
 153 #  bit deposit
 154
 155 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
 156
 157     do while(m < 64)
 158        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
 159           result = VSR[VRA+32].dword[i].bit[63-k]
 160           VSR[VRT+32].dword[i].bit[63-m] = result
 161           k = k + 1
 162        m = m + 1
 163
 164 ```
 165
 166 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
 167 {
 168     uint_xlen_t r = 0;
 169     for (int i = 0, j = 0; i < XLEN; i++)
 170         if ((RB >> i) & 1) {
 171             if ((RA >> j) & 1)
 172                 r |= uint_xlen_t(1) << i;
 173             j++;
 174         }
 175     return r;
 176 }
 177
 178 ```
 179
 180 # bit extract
 181
 182 other way round: identical to RV bext, found in v3.1 p196
 183
 184 ```
 185 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
 186 {
 187     uint_xlen_t r = 0;
 188     for (int i = 0, j = 0; i < XLEN; i++)
 189         if ((RB >> i) & 1) {
 190             if ((RA >> i) & 1)
 191                 r |= uint_xlen_t(1) << j;
 192             j++;
 193         }
 194     return r;
 195 }
 196 ```
 197
 198 # centrifuge
 199
 200 found in v3.1 p106 so not to be added here
 201
 202 ```
 203 ptr0 = 0
 204 ptr1 = 0
 205 do i = 0 to 63
 206     if((RB)i=0) then do
 207        resultptr0 = (RS)i
 208     end
 209     ptr0 = ptr0 + 1
 210     if((RB)63-i==1) then do
 211         result63-ptr1 = (RS)63-i
 212     end
 213     ptr1 = ptr1 + 1
 214 RA = result
 215 ```
 216
 217 # int min/max
 218
 219 signed and unsigned min/max for integer.  this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned.  when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
 220
 221 signed/unsigned min/max gives more flexibility.
 222
 223 ```
 224 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
 225 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
 226 }
 227 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
 228 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
 229 }
 230 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
 231 { return rs1 < rs2 ? rs1 : rs2;
 232 }
 233 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
 234 { return rs1 > rs2 ? rs1 : rs2;
 235 }
 236 ```
 237
 238
 239 # ternlog bitops
 240
 241 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
 242
 243 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
 244
 245 ## ternlogi
 246
 247 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 248 | -- | -- | --- | --- | ----- | -------- |--|
 249 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |0 |
 250
 251     for i in range(64):
 252         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 253         RT[i] = (imm & (1<<idx)) != 0
 254
 255 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 256
 257 ## ternlog
 258
 259 a 4 operand variant which becomes more along the lines of an FPGA:
 260
 261 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
 262 | -- | -- | --- | --- | --- | -------- |--|
 263 | NN | RT | RA  | RB  | RC  | mode 100 |1 |
 264
 265     for i in range(64):
 266         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 267         RT[i] = (RC & (1<<idx)) != 0
 268
 269 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
 270 3 modes.
 271
 272 ## ternlogv
 273
 274 also, another possible variant involving swizzle and vec4:
 275
 276 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
 277 | -- | -- | --- | ----- | ---- | ----- |--|
 278 | NN | RT | RA  | imm   | mask | 101   |1 |
 279
 280     for i in range(8):
 281         idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
 282         res = (imm & (1<<idx)) != 0
 283         for j in range(3):
 284              if mask[j]: RT[i+j*8] = res
 285
 286 ## ternlogcr
 287
 288 another mode selection would be CRs not Ints.
 289
 290 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|
 291 | -- | -- | --- | --- |- |-----|----- | -----|--|
 292 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 |
 293
 294     for i in range(4):
 295         if not mask[i] continue
 296         idx = crregs[BA][i] << 2 |
 297               crregs[BB][i] << 1 |
 298               crregs[BC][i]
 299         crregs[BA][i] = (imm & (1<<idx)) != 0
 300
 301 # bitmask set
 302
 303 based on RV bitmanip singlebit set, instruction format similar to shift
 304 [[isa/fixedshift]].  bmext is actually covered already (shift-with-mask rldicl but only immediate version).
 305 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
 306
 307 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate.  for the immediate version this does not matter, so a bmexti is not required.
 308 bmrev however there is no direct equivalent and consequently a bmrevi is required.
 309
 310 bmset (register for mask amount) is particularly useful for creating
 311 predicate masks where the length is a dynamic runtime quantity.
 312 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
 313
 314 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 315 | -- | -- | --- | --- | --- | ------- |--| ----- |
 316 | NN | RT | RA  | RB  | RC  | mode 010 |Rc| bm*   |
 317 | NN | RT | RA  | RB  | RC  | 0 1  111 |Rc| bmrev |
 318
 319
 320 ```
 321 uint_xlen_t bmset(RA, RB, sh)
 322 {
 323     int shamt = RB & (XLEN - 1);
 324     mask = (2<<sh)-1;
 325     return RA | (mask << shamt);
 326 }
 327
 328 uint_xlen_t bmclr(RA, RB, sh)
 329 {
 330     int shamt = RB & (XLEN - 1);
 331     mask = (2<<sh)-1;
 332     return RA & ~(mask << shamt);
 333 }
 334
 335 uint_xlen_t bminv(RA, RB, sh)
 336 {
 337     int shamt = RB & (XLEN - 1);
 338     mask = (2<<sh)-1;
 339     return RA ^ (mask << shamt);
 340 }
 341
 342 uint_xlen_t bmext(RA, RB, sh)
 343 {
 344     int shamt = RB & (XLEN - 1);
 345     mask = (2<<sh)-1;
 346     return mask & (RA >> shamt);
 347 }
 348 ```
 349
 350 bitmask extract with reverse.  can be done by bitinverting all of RA and getting bits of RA from the opposite end.
 351
 352 ```
 353 msb = rb[5:0];
 354 rev[0:msb] = ra[msb:0];
 355 rt = ZE(rev[msb:0]);
 356
 357 uint_xlen_t bmextrev(RA, RB, sh)
 358 {
 359     int shamt = (RB & (XLEN - 1));
 360     shamt = (XLEN-1)-shamt;  # shift other end
 361     bra = bitreverse(RA)     # swap LSB-MSB
 362     mask = (2<<sh)-1;
 363     return mask & (bra >> shamt);
 364 }
 365 ```
 366
 367 | 0.5|6.10|11.15|16.20|21.26| 27..30  |31| name   |
 368 | -- | -- | --- | --- | --- | ------- |--| ------ |
 369 | NN | RT | RA  | RB  | sh  | 0   111 |Rc| bmrevi |
 370
 371
 372
 373 # grev
 374
 375 based on RV bitmanip
 376
 377 ```
 378 uint64_t grev64(uint64_t RA, uint64_t RB)
 379 {
 380     uint64_t x = RA;
 381     int shamt = RB & 63;
 382     if (shamt & 1) x = ((x &  0x5555555555555555LL) <<  1) |
 383                         ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);
 384     if (shamt & 2) x = ((x &  0x3333333333333333LL) <<  2) |
 385                         ((x & 0xCCCCCCCCCCCCCCCCLL) >>  2);
 386     if (shamt & 4) x = ((x &  0x0F0F0F0F0F0F0F0FLL) <<  4) |
 387                         ((x & 0xF0F0F0F0F0F0F0F0LL) >>  4);
 388     if (shamt & 8) x = ((x &  0x00FF00FF00FF00FFLL) <<  8) |
 389                         ((x & 0xFF00FF00FF00FF00LL) >>  8);
 390     if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
 391                         ((x & 0xFFFF0000FFFF0000LL) >> 16);
 392     if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
 393                         ((x & 0xFFFFFFFF00000000LL) >> 32);
 394     return x;
 395 }
 396
 397 ```
 398
 399 # shuffle / unshuffle
 400
 401 based on RV bitmanip
 402
 403 ```
 404 uint32_t shfl32(uint32_t RA, uint32_t RB)
 405 {
 406     uint32_t x = RA;
 407     int shamt = RB & 15;
 408     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 409     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 410     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 411     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 412     return x;
 413 }
 414 uint32_t unshfl32(uint32_t RA, uint32_t RB)
 415 {
 416     uint32_t x = RA;
 417     int shamt = RB & 15;
 418     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 419     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 420     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 421     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 422     return x;
 423 }
 424
 425 uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
 426 {
 427     uint64_t x = src & ~(maskL | maskR);
 428     x |= ((src << N) & maskL) | ((src >> N) & maskR);
 429     return x;
 430 }
 431 uint64_t shfl64(uint64_t RA, uint64_t RB)
 432 {
 433     uint64_t x = RA;
 434     int shamt = RB & 31;
 435     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 436                                            0x00000000ffff0000LL, 16);
 437     if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 438                                            0x0000ff000000ff00LL, 8);
 439     if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 440                                            0x00f000f000f000f0LL, 4);
 441     if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
 442                                            0x0c0c0c0c0c0c0c0cLL, 2);
 443     if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
 444                                            0x2222222222222222LL, 1);
 445     return x;
 446 }
 447 uint64_t unshfl64(uint64_t RA, uint64_t RB)
 448 {
 449     uint64_t x = RA;
 450     int shamt = RB & 31;
 451     if (shamt &  1) x = shuffle64_stage(x, 0x4444444444444444LL,
 452                                            0x2222222222222222LL, 1);
 453     if (shamt &  2) x = shuffle64_stage(x, 0x3030303030303030LL,
 454                                            0x0c0c0c0c0c0c0c0cLL, 2);
 455     if (shamt &  4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 456                                            0x00f000f000f000f0LL, 4);
 457     if (shamt &  8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 458                                            0x0000ff000000ff00LL, 8);
 459     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 460                                            0x00000000ffff0000LL, 16);
 461     return x;
 462 }
 463 ```
 464
 465 # xperm
 466
 467 based on RV bitmanip
 468
 469 ```
 470 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
 471 {
 472     uint_xlen_t r = 0;
 473     uint_xlen_t sz = 1LL << sz_log2;
 474     uint_xlen_t mask = (1LL << sz) - 1;
 475     for (int i = 0; i < XLEN; i += sz) {
 476         uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
 477         if (pos < XLEN)
 478             r |= ((RA >> pos) & mask) << i;
 479     }
 480     return r;
 481 }
 482 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
 483 {  return xperm(RA, RB, 2); }
 484 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
 485 {  return xperm(RA, RB, 3); }
 486 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
 487 {  return xperm(RA, RB, 4); }
 488 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
 489 {  return xperm(RA, RB, 5); }
 490 ```
 491
 492 # gorc
 493
 494 based on RV bitmanip
 495
 496 ```
 497 uint32_t gorc32(uint32_t RA, uint32_t RB)
 498 {
 499     uint32_t x = RA;
 500     int shamt = RB & 31;
 501     if (shamt & 1) x |= ((x & 0x55555555) << 1)   |  ((x &  0xAAAAAAAA) >> 1);
 502     if (shamt & 2) x |= ((x & 0x33333333) << 2)   |  ((x &  0xCCCCCCCC) >> 2);
 503     if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4)   |  ((x &  0xF0F0F0F0) >> 4);
 504     if (shamt & 8) x |= ((x & 0x00FF00FF) << 8)   |  ((x &  0xFF00FF00) >> 8);
 505     if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) |  ((x &  0xFFFF0000) >> 16);
 506     return x;
 507 }
 508 uint64_t gorc64(uint64_t RA, uint64_t RB)
 509 {
 510     uint64_t x = RA;
 511     int shamt = RB & 63;
 512     if (shamt & 1) x |= ((x & 0x5555555555555555LL)   <<   1) |
 513                          ((x & 0xAAAAAAAAAAAAAAAALL)  >>  1);
 514     if (shamt & 2) x |= ((x & 0x3333333333333333LL)   <<   2) |
 515                          ((x & 0xCCCCCCCCCCCCCCCCLL)  >>  2);
 516     if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL)   <<   4) |
 517                          ((x & 0xF0F0F0F0F0F0F0F0LL)  >>  4);
 518     if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL)   <<   8) |
 519                          ((x & 0xFF00FF00FF00FF00LL)  >>  8);
 520     if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL)  << 16) |
 521                          ((x & 0xFFFF0000FFFF0000LL)  >> 16);
 522     if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL)  << 32) |
 523                          ((x & 0xFFFFFFFF00000000LL)  >> 32);
 524     return x;
 525 }
 526
 527 ```
 528
 529 # cmix
 530
 531 based on RV bitmanip, covered by ternlog bitops
 532
 533 ```
 534 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
 535     return (RA & RB) | (RC & ~RB);
 536 }
 537 ```
 538
 539 # carryless mul
 540
 541 based on RV bitmanip
 542 see https://en.wikipedia.org/wiki/CLMUL_instruction_set
 543
 544 ```
 545 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
 546 {
 547     uint_xlen_t x = 0;
 548     for (int i = 0; i < XLEN; i++)
 549         if ((RB >> i) & 1)
 550             x ^= RA << i;
 551     return x;
 552 }
 553 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
 554 {
 555     uint_xlen_t x = 0;
 556     for (int i = 1; i < XLEN; i++)
 557         if ((RB >> i) & 1)
 558             x ^= RA >> (XLEN-i);
 559     return x;
 560 }
 561 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
 562 {
 563     uint_xlen_t x = 0;
 564     for (int i = 0; i < XLEN; i++)
 565         if ((RB >> i) & 1)
 566             x ^= RA >> (XLEN-i-1);
 567     return x;
 568 }
 569 ```
 570 # Galois Field
 571
 572 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
 573
 574 ## Multiply
 575
 576 this requires 3 parameters and a "degree"
 577
 578     RT = GFMUL(RA, RB, gfdegree, modulo=RC)
 579
 580 realistically with the degree also needing to be an immediate it should be brought down to an overwrite version:
 581
 582     RS = GFMUL(RS, RA, gfdegree, modulo=RC)
 583     RS = GFMUL(RS, RA, gfdegree=RB, modulo=RC)
 584
 585 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31|
 586 | -- | -- | --- | --- | --- | ------- |--|
 587 | NN | RS | RA  | deg | RC  | 00  011 |Rc|
 588 | NN | RS | RA  | RB  | RC  | 11  011 |Rc|
 589
 590 where the SimpleV variant may override RS-as-src differently from RS-as-dest
 591
 592
 593
 594 ```
 595 from functools import reduce
 596
 597 # constants used in the multGF2 function
 598 mask1 = mask2 = polyred = None
 599
 600 def setGF2(degree, irPoly):
 601     """Define parameters of binary finite field GF(2^m)/g(x)
 602        - degree: extension degree of binary field
 603        - irPoly: coefficients of irreducible polynomial g(x)
 604     """
 605     def i2P(sInt):
 606         """Convert an integer into a polynomial"""
 607         return [(sInt >> i) & 1
 608                 for i in reversed(range(sInt.bit_length()))]
 609
 610     global mask1, mask2, polyred
 611     mask1 = mask2 = 1 << degree
 612     mask2 -= 1
 613     polyred = reduce(lambda x, y: (x << 1) + y, i2P(irPoly)[1:])
 614
 615 def multGF2(p1, p2):
 616     """Multiply two polynomials in GF(2^m)/g(x)"""
 617     p = 0
 618     while p2:
 619         if p2 & 1:
 620             p ^= p1
 621         p1 <<= 1
 622         if p1 & mask1:
 623             p1 ^= polyred
 624         p2 >>= 1
 625     return p & mask2
 626
 627 if __name__ == "__main__":
 628
 629     # Define binary field GF(2^3)/x^3 + x + 1
 630     setGF2(3, 0b1011)
 631
 632     # Evaluate the product (x^2 + x + 1)(x^2 + 1)
 633     print("{:02x}".format(multGF2(0b111, 0b101)))
 634
 635     # Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
 636     # (used in the Advanced Encryption Standard-AES)
 637     setGF2(8, 0b100011011)
 638
 639     # Evaluate the product (x^7)(x^7 + x + 1)
 640     print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
 641 ```
 642 ## GF add
 643
 644     RS = GFADDI(RS, RA|0, gfdegree, modulo=RC)
 645     RS = GFADD(RS, RA|0, gfdegree=RB, modulo=RC)
 646
 647 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 648 | -- | -- | --- | --- | --- | ------- |--| ----- |
 649 | NN | RS | RA  | deg | RC  | 0 1  011 |Rc| gfaddi |
 650 | NN | RS | RA  | RB  | RC  | 1 1  111 |Rc| gfadd |
 651
 652 GFMOD is a pseudo-op where RA=0
 653
 654 ## gf invert
 655
 656 ```
 657 def gf_degree(a) :
 658   res = 0
 659   a >>= 1
 660   while (a != 0) :
 661     a >>= 1;
 662     res += 1;
 663   return res
 664
 665 def gf_invert(a, mod=0x1B) :
 666   v = mod
 667   g1 = 1
 668   g2 = 0
 669   j = gf_degree(a) - 8
 670
 671   while (a != 1) :
 672     if (j < 0) :
 673       a, v = v, a
 674       g1, g2 = g2, g1
 675       j = -j
 676
 677     a ^= v << j
 678     g1 ^= g2 << j
 679
 680     a %= 256  # Emulating 8-bit overflow
 681     g1 %= 256 # Emulating 8-bit overflow
 682
 683     j = gf_degree(a) - gf_degree(v)
 684
 685   return g1
 686 ```
 687
 688 # bitmatrix
 689
 690 ```
 691 uint64_t bmatflip(uint64_t RA)
 692 {
 693     uint64_t x = RA;
 694     x = shfl64(x, 31);
 695     x = shfl64(x, 31);
 696     x = shfl64(x, 31);
 697     return x;
 698 }
 699 uint64_t bmatxor(uint64_t RA, uint64_t RB)
 700 {
 701     // transpose of RB
 702     uint64_t RBt = bmatflip(RB);
 703     uint8_t u[8]; // rows of RA
 704     uint8_t v[8]; // cols of RB
 705     for (int i = 0; i < 8; i++) {
 706         u[i] = RA >> (i*8);
 707         v[i] = RBt >> (i*8);
 708     }
 709     uint64_t x = 0;
 710     for (int i = 0; i < 64; i++) {
 711         if (pcnt(u[i / 8] & v[i % 8]) & 1)
 712             x |= 1LL << i;
 713     }
 714     return x;
 715 }
 716 uint64_t bmator(uint64_t RA, uint64_t RB)
 717 {
 718     // transpose of RB
 719     uint64_t RBt = bmatflip(RB);
 720     uint8_t u[8]; // rows of RA
 721     uint8_t v[8]; // cols of RB
 722     for (int i = 0; i < 8; i++) {
 723         u[i] = RA >> (i*8);
 724         v[i] = RBt >> (i*8);
 725     }
 726     uint64_t x = 0;
 727     for (int i = 0; i < 64; i++) {
 728         if ((u[i / 8] & v[i % 8]) != 0)
 729             x |= 1LL << i;
 730     }
 731     return x;
 732 }
 733
 734 ```