1 [[!tag standards]]

3 # FPR-to-GPR and GPR-to-FPR

5 TODO special constants instruction (e, tau/N, ln 2, sqrt 2, etc.) -- exclude any constants available through fmvis

7 **Draft Status** under development, for submission as an RFC

9 Links:

11 * <https://bugs.libre-soc.org/show_bug.cgi?id=650>

12 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c71>

13 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c74>

14 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c76>

15 * <https://bugs.libre-soc.org/show_bug.cgi?id=887> fmvis

16 * <https://bugs.libre-soc.org/show_bug.cgi?id=1015> int-fp RFC

17 * [[int_fp_mv/appendix]]

18 * [[sv/rfc/ls002]] - `fmvis` and `fishmv` External RFC Formal Submission

19 * [[sv/rfc/ls006]] - int-fp-mv External RFC Formal Submission

21 Trademarks:

23 * Rust is a Trademark of the Rust Foundation

24 * Java and Javascript are Trademarks of Oracle

25 * LLVM is a Trademark of the LLVM Foundation

26 * SPIR-V is a Trademark of the Khronos Group

27 * OpenCL is a Trademark of Apple, Inc.

29 Referring to these Trademarks within this document

30 is by necessity, in order to put the semantics of each language

31 into context, and is considered "fair use" under Trademark

32 Law.

34 Introduction:

36 High-performance CPU/GPU software needs to often convert between integers

37 and floating-point, therefore fast conversion/data-movement instructions

38 are needed. Also given that initialisation of floats tends to take up

39 considerable space (even to just load 0.0) the inclusion of two compact

40 format float immediate instructions is up for consideration using 16-bit

41 immediates. BF16 is one of the formats: a second instruction allows a full

42 accuracy FP32 to be constructed.

44 Libre-SOC will be compliant with the

45 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,

46 and with its focus on modern 3D GPU hybrid workloads represents an

47 important new potential use-case for OpenPOWER.

49 Prior to the formation of the Compliancy Levels first introduced

50 in v3.0C and v3.1

51 the progressive historic development of the Scalar parts of the Power ISA assumed

52 that VSX would always be there to complement it. However With VMX/VSX

53 **not available** in the newly-introduced SFFS Compliancy Level, the

54 existing non-VSX conversion/data-movement instructions require

55 a Vector of load/store

56 instructions (slow and expensive) to transfer data between the FPRs and

57 the GPRs. For a modern 3D GPU this kills any possibility of a

58 competitive edge.

59 Also, because SimpleV needs efficient scalar instructions in

60 order to generate efficient vector instructions, adding new instructions

61 for data-transfer/conversion between FPRs and GPRs multiplies the savings.

63 In addition, the vast majority of GPR <-> FPR data-transfers are as part

64 of a FP <-> Integer conversion sequence, therefore reducing the number

65 of instructions required is a priority.

67 Therefore, we are proposing adding:

69 * FPR load-immediate instructions, one equivalent to `BF16`, the

70 other increasing accuracy to `FP32`

71 * FPR <-> GPR data-transfer instructions that just copy bits without conversion

72 * FPR <-> GPR combined data-transfer/conversion instructions that do

73 Integer <-> FP conversions

75 If adding new Integer <-> FP conversion instructions,

76 the opportunity may be taken to modernise the instructions and make them

77 well-suited for common/important conversion sequences:

79 * **standard IEEE754** - used by most languages and CPUs

80 * **standard OpenPOWER** - saturation with NaN

81 converted to minimum valid integer

82 * **Java** - saturation with NaN converted to 0

83 * **JavaScript** - modulo wrapping with Inf/NaN converted to 0

85 The assembly listings in the [[int_fp_mv/appendix]] show how costly

86 some of these language-specific conversions are: Javascript, the

87 worst case, is 32 scalar instructions including seven branch instructions.

89 # Proposed New Scalar Instructions

91 All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR. All integers however are sourced/stored in the *GPR*.

93 Integer operands and results being in the GPR is the key differentiator between the proposed instructions

94 (the entire rationale) compared to existing Scalar Power ISA.

95 In all existing Power ISA Scalar conversion instructions, all

96 operands are FPRs, even if the format of the source or destination

97 data is actually a scalar integer.

99 *(The existing Scalar instructions being FP-FP only is based on an assumption

100 that VSX will be implemented, and VSX is not part of the SFFS Compliancy

101 Level. An earlier version of the Power ISA used to have similar

102 FPR<->GPR instructions to these:

103 they were deprecated due to this incorrect assumption that VSX would

104 always be present).*

106 Note that source and destination widths can be overridden by SimpleV

107 SVP64, and that SVP64 also has Saturation Modes *in addition*

108 to those independently described here. SVP64 Overrides and Saturation

109 work on *both* Fixed *and* Floating Point operands and results.

110 The interactions with SVP64

111 are explained in the [[int_fp_mv/appendix]]

113 # Float load immediate <a name="fmvis"></a>

115 These are like a variant of `fmvfg` and `oris`, combined.

116 Power ISA currently requires a large

117 number of instructions to get Floating Point constants into registers.

118 `fmvis` on its own is equivalent to BF16 to FP32/64 conversion,

119 but if followed up by `fishmv` an additional 16 bits of accuracy in the

120 mantissa may be achieved.

122 These instructions **always** save

123 resources compared to FP-load for exactly the same reason

124 that `li` saves resources: an L1-Data-Cache and memory read

125 is avoided.

127 *IBM may consider it worthwhile to extend these two instructions to

128 v3.1 Prefixed (`pfmvis` and `pfishmv`: 8RR, imm0 extended).

129 If so it is recommended that

130 `pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high

131 missing exponent bits (numbered 8 to 10) and the lower additional

132 29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.

133 Strictly speaking the sequence `fmvis fishmv pfishmv` achieves the

134 same effect in the same number of bytes as `pfmvis pfishmv`,

135 making `pfmvis` redundant.*

137 Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv.

138 As fishmv is specifically intended to work in conjunction with fmvis

139 to provide additional accuracy, all bits other than those which

140 would have been set by a prior fmvis instruction are deliberately ignored.

141 (If these instructions involved reading from registers rather than immediates

142 it would be a different story).

144 ## Load BF16 Immediate

146 `fmvis FRS, D`

148 Reinterprets `D << 16` as a 32-bit float, which is then converted to a

149 64-bit float and written to `FRS`. This is equivalent to reinterpreting

150 `D` as a `BF16` and converting to 64-bit float.

151 There is no need for an Rc=1 variant because this is an immediate loading

152 instruction.

154 Example:

156 ```

157 # clearing a FPR

158 fmvis f4, 0 # writes +0.0 to f4

159 # loading handy constants

160 fmvis f4, 0x8000 # writes -0.0 to f4

161 fmvis f4, 0x3F80 # writes +1.0 to f4

162 fmvis f4, 0xBF80 # writes -1.0 to f4

163 fmvis f4, 0xBFC0 # writes -1.5 to f4

164 fmvis f4, 0x7FC0 # writes +qNaN to f4

165 fmvis f4, 0x7F80 # writes +Infinity to f4

166 fmvis f4, 0xFF80 # writes -Infinity to f4

167 fmvis f4, 0x3FFF # writes +1.9921875 to f4

169 # clearing 128 FPRs with 2 SVP64 instructions

170 # by issuing 32 vec4 (subvector length 4) ops

171 setvli VL=MVL=32

172 sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127

173 ```

174 Important: If the float load immediate instruction(s) are left out,

175 change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)

176 to instead write `+0.0` if `RA` is register `0`, at least

177 allowing clearing FPRs.

179 `fmvis` fits with DX-Form:

181 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |

182 |--------|------|-------|-------|-------|-----|---------|

183 | Major | FRS | d1 | d0 | XO | d2 | DX-Form |

185 Pseudocode:

187 bf16 = d0 || d1 || d2 # create BF16 immediate

188 fp32 = bf16 || [0]*16 # convert BF16 to FP32

189 FRS = DOUBLE(fp32) # convert FP32 to FP64

191 Special registers altered:

193 None

195 ## Float Immediate Second-Half MV <a name="fishmv"></a>

197 `fishmv FRS, D`

199 DX-Form:

201 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |

202 |--------|------|-------|-------|-------|-----|---------|

203 | Major | FRS | d1 | d0 | XO | d2 | DX-Form |

205 Strategically similar to how `oris` is used to construct

206 32-bit Integers, an additional 16-bits of immediate is

207 inserted into `FRS` to extend its accuracy to

208 a full FP32 (stored as usual in FP64 Format within the FPR).

209 If a prior `fmvis` instruction had been used to

210 set the upper 16-bits of an FP32 value, `fishmv` contains the

211 lower 16-bits.

213 The key difference between using `li` and `oris` to construct 32-bit

214 GPR Immediates and `fishmv` is that the `fmvis` will have converted

215 the `BF16` immediate to FP64 (Double) format.

216 This is taken into consideration

217 as can be seen in the pseudocode below.

219 Pseudocode:

221 fp32 <- SINGLE((FRS)) # convert to FP32

222 fp32[16:31] <- d0 || d1 || d2 # replace LSB half

223 FRS <- DOUBLE(fp32) # convert back to FP64

225 Special registers altered:

227 None

229 **This instruction performs a Read-Modify-Write.** *FRS is read, the additional

230 16 bit immediate inserted, and the result also written to FRS*

232 Example:

234 ```

235 # these two combined instructions write 0x3f808000

236 # into f4 as an FP32 to be converted to an FP64.

237 # actual contents in f4 after conversion: 0x3ff0_1000_0000_0000

238 # first the upper bits, happens to be +1.0

239 fmvis f4, 0x3F80 # writes +1.0 to f4

240 # now write the lower 16 bits of an FP32

241 fishmv f4, 0x8000 # writes +1.00390625 to f4

242 ```

244 # Moves & Generalized Bit Reverses

246 These instructions perform a generalized bit reverse on the underlying bits in

247 FPRs, optionally moving between FPR/GPR register files. These instructions are

248 designed to replace using a store/load pair to `memcpy`/transmute the bitwise

249 representation of floating-point values, with optional endian swaps.

251 # FPR to FPR Generalized Bit Reverse

252 * `fgrevi FRT, FRA, SH` XS-form

253 * `fgrevi. FRT, FRA, SH` XS-form

254 * `fgrevisd FRT, FRA, SH` XS-form

255 * `fgrevisd. FRT, FRA, SH` XS-form

256 * `fgrevids FRT, FRA, SH` XS-form

257 * `fgrevids. FRT, FRA, SH` XS-form

258 * `fgrevis FRT, FRA, SH` XS-form

259 * `fgrevis. FRT, FRA, SH` XS-form

261 Jacob: maybe leave out sd/ds forms?

263 read a 32/64-bit float from `FRA`, do a generalized bit reverse on the

264 zero-extended bitwise representation, then write the result as a 32/64-bit

265 float to `FRT`.

266 This can be used to do any combination of endian swaps, which are useful

267 for emulating a big-endian `memcpy`/transmute e.g. from `f32x2` to `f64` or

268 from the MSB half of `f64` to `f32` or similar.

270 Pseudo-code:

272 ```

273 v <- (FRA)

274 if insn in ["fgrevisd", "fgrevisd.", "fgrevis", "fgrevis."] then

275 v <- [0] * 32 || SINGLE(v)

276 v <- GREV64(v, SH)

277 if insn in ["fgrevids", "fgrevids.", "fgrevis", "fgrevis."] then

278 FRT <- DOUBLE(v[32:63])

279 else

280 FRT <- v

281 ```

283 All instructions, including `*s` forms, are explicitly XS-form and have 6-bit

284 SH immediates, this allows having `f32` values in the MSB 32-bits of the

285 input/result.

287 Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.

289 # GPR to FPR moves & Generalized Bit Reverses

291 * `fgrevfgi FRT, RA, SH` XS-form

292 * `fgrevfgi. FRT, RA, SH` XS-form

293 * `fgrevfgis FRT, RA, SH` XS-form

294 * `fgrevfgis. FRT, RA, SH` XS-form

296 read from a GPR and do a generalized bit reverse (grev) on

297 the bits, writing the resulting bits as a 32/64-bit float to a FPR.

298 This can be used to do a bitwise copy from a GPR to a FPR.

299 This can also be used to do any combination of endian swaps, which are useful

300 for emulating a big-endian `memcpy`/transmute e.g. from `u32x2` to `f64` or

301 from `i8x4` to `f32` or similar.

303 Pseudo-code:

305 ```

306 v <- GREV64((RA), SH)

307 if insn = "fgrevfgis" or insn = "fgrevfgis." then

308 FRT <- DOUBLE(v[32:63])

309 else

310 FRT <- v

311 ```

313 Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.

315 Note `fgrevfgis` is explicitly XS-form and has a 6-bit SH immediate, this

316 allows taking the `f32` value from the MSB 32-bits of the input GPR.

318 # FPR to GPR Moves & Generalized Bit Reverses

320 * `fgrevtgi RT, FRA, SH` XS-form

321 * `fgrevtgi. RT, FRA, SH` XS-form

322 * `fgrevtgis RT, FRA, SH` XS-form

323 * `fgrevtgis. RT, FRA, SH` XS-form

325 read a 32/64-bit float from a FPR and do a generalized bit reverse (grev) on

326 the zero-extended bitwise bits, writing the result to a GPR. This can be used

327 to do a bitwise copy from a FPR to a GPR. This can also be used to do any

328 combination of endian swaps, which are useful for emulating a big-endian

329 `memcpy`/transmute, e.g. from `f64` to `u32x2` or from `f32` to `i8x4` or

330 similar.

332 Pseudo-code:

334 ```

335 v <- (FRA)

336 if insn = "fgrevtgis" or insn = "fgrevtgis." then

337 v <- [0] * 32 || SINGLE(v)

338 RT <- GREV64(v, SH)

339 ```

341 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point

342 operations.

344 Note `fgrevtgis` is explicitly XS-form and has a 6-bit SH immediate, this

345 allows putting the `f32` value into the MSB 32-bits of the result.

347 * `fmvtg RT, FRA` (alias of `fgrevtgi RT, FRA, 0`)

348 * `fmvtg. RT, FRA` (alias of `fgrevtgi. RT, FRA, 0`)

350 move a 64-bit float from a FPR to a GPR, just copying bits directly.

351 As a direct bitcopy, no exceptions occur and no status flags are set.

353 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point

354 operations.

356 * `fmvtgs RT, FRA` (alias of `fgrevtgis RT, FRA, 0`)

357 * `fmvtgs. RT, FRA` (alias of `fgrevtgis. RT, FRA, 0`)

359 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the

360 64-bit float in `FRA` to a 32-bit float, using the same method as `stfs`,

361 then writes the 32-bit float to `RT`, setting the high 32-bits to zeros.

362 Effectively, `fmvtgs` is a macro-fusion of `stfs` and `lwz` and therefore

363 does not behave like `frsp` and does not set any fp exception flags.

365 Since RT is a GPR, Rc=1 follows standard *integer* behaviour, i.e.

366 tests RT and sets CR0.

368 # GPR to FPR moves & Generalized Bit Reverses

370 * `fgrevfgi FRT, RA, SH` XS-form

371 * `fgrevfgi. FRT, RA, SH` XS-form

372 * `fgrevfgis FRT, RA, SH` XS-form

373 * `fgrevfgis. FRT, RA, SH` XS-form

375 read from a GPR and do a generalized bit reverse (grev) on

376 the bits, writing the resulting bits as a 32/64-bit float to a FPR.

377 This can be used to do a bitwise copy from a GPR to a FPR.

378 This can also be used to do any combination of endian swaps, which are useful

379 for emulating a big-endian `memcpy`/transmute e.g. from `u32x2` to `f64` or

380 from `i8x4` to `f32` or similar.

382 Pseudo-code:

384 ```

385 v <- GREV64((RA), SH)

386 if insn = "fgrevfgis" or insn = "fgrevfgis." then

387 FRT <- DOUBLE(v[32:63])

388 else

389 FRT <- v

390 ```

392 Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.

394 Note `fgrevfgis` is explicitly XS-form and has a 6-bit SH immediate, this

395 allows taking the `f32` value from the MSB 32-bits of the input GPR.

397 * `fmvfg FRT, RA` (alias of `fgrevfgi FRT, RA, 0`)

398 * `fmvfg. FRT, RA` (alias of `fgrevfgi. FRT, RA, 0`)

400 move a 64-bit float from a GPR to a FPR, just copying bits. No exceptions

401 are raised, no flags are altered of any kind.

403 Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.

405 * `fmvfgs FRT, RA` (alias of `fgrevfgis FRT, RA, 0`)

406 * `fmvfgs. FRT, RA` (alias of `fgrevfgis. FRT, RA, 0`)

408 move a 32-bit float from a GPR to a FPR, just copying bits. Converts the

409 32-bit float in `RA` to a 64-bit float, using the same method as `lfs`,

410 then writes the 64-bit float to `FRT`. Effectively, `fmvfgs` is a

411 macro-fusion of `stw` and `lfs` and therefore no fp exception flags are set.

413 Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.

415 # Conversions

417 Unlike the move instructions

418 these instructions perform conversions between Integer and

419 Floating Point. Truncation can therefore occur, as well

420 as exceptions.

422 Mode values:

424 | Mode | `rounding_mode` | Semantics |

425 |------|-----------------|----------------------------------|

426 | 000 | from `FPSCR` | [OpenPower semantics] |

427 | 001 | Truncate | [OpenPower semantics] |

428 | 010 | from `FPSCR` | [Java semantics] |

429 | 011 | Truncate | [Java semantics] |

430 | 100 | from `FPSCR` | [JavaScript semantics] |

431 | 101 | Truncate | [JavaScript semantics] |

432 | rest | -- | illegal instruction trap for now |

434 [OpenPower semantics]: #fp-to-int-openpower-conversion-semantics

435 [Java semantics]: #fp-to-int-java-conversion-semantics

436 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics

438 ## GPR to FPR conversions

440 **Format**

442 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |

443 |--------|------|--------|-------|-------|----|------|

444 | Major | FRT | //Mode | RA | XO | Rc |X-Form|

446 All of the following GPR to FPR conversions use the rounding mode from `FPSCR`.

448 * `fcvtfgw FRT, RA`

449 Convert from 32-bit signed integer in the GPR `RA` to 64-bit float in

450 `FRT`.

451 * `fcvtfgws FRT, RA`

452 Convert from 32-bit signed integer in the GPR `RA` to 32-bit float in

453 `FRT`.

454 * `fcvtfguw FRT, RA`

455 Convert from 32-bit unsigned integer in the GPR `RA` to 64-bit float in

456 `FRT`.

457 * `fcvtfguws FRT, RA`

458 Convert from 32-bit unsigned integer in the GPR `RA` to 32-bit float in

459 `FRT`.

460 * `fcvtfgd FRT, RA`

461 Convert from 64-bit signed integer in the GPR `RA` to 64-bit float in

462 `FRT`.

463 * `fcvtfgds FRT, RA`

464 Convert from 64-bit signed integer in the GPR `RA` to 32-bit float in

465 `FRT`.

466 * `fcvtfgud FRT, RA`

467 Convert from 64-bit unsigned integer in the GPR `RA` to 64-bit float in

468 `FRT`.

469 * `fcvtfguds FRT, RA`

470 Convert from 64-bit unsigned integer in the GPR `RA` to 32-bit float in

471 `FRT`.

473 ## FPR to GPR (Integer) conversions

475 <div id="fpr-to-gpr-conversion-mode"></div>

477 Different programming languages turn out to have completely different

478 semantics for FP to Integer conversion. Below is an overview

479 of the different variants, listing the languages and hardware that

480 implements each variant.

482 **Standard IEEE754 conversion**

484 This conversion is outlined in the IEEE754 specification. It is used

485 by nearly all programming languages and CPUs. In the case of OpenPOWER,

486 the rounding mode is read from FPSCR

488 **Standard OpenPower conversion**

490 This conversion, instead of exact IEEE754 Compliance, performs

491 "saturation with NaN converted to minimum valid integer". This

492 is also exactly the same as the x86 ISA conversion semantics.

493 OpenPOWER however has instructions for both:

495 * rounding mode read from FPSCR

496 * rounding mode always set to truncate

498 **Java conversion**

500 For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by Java's semantics (and Rust's `as` operator) will be referred to as

501 [Java conversion semantics](#fp-to-int-java-conversion-semantics).

503 Those same semantics are used in some way by all of the following languages (not necessarily for the default conversion method):

505 * Java's

506 [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)

507 * Rust's FP -> Integer conversion using the

508 [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)

509 * LLVM's

510 [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and

511 [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics

512 * SPIR-V's OpenCL dialect's

513 [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and

514 [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)

515 instructions when decorated with

516 [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).

517 * WebAssembly has also introduced

518 [trunc_sat_u](ttps://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-u) and

519 [trunc_sat_s](https://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-s)

521 **JavaScript conversion**

523 For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by JavaScripts's `ToInt32` abstract operation will be referred to as [JavaScript conversion semantics](#fp-to-int-javascript-conversion-semantics).

525 This instruction is present in ARM assembler as FJCVTZS

526 <https://developer.arm.com/documentation/dui0801/g/hko1477562192868>

528 **Format**

530 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |

531 |--------|------|--------|-------|-------|----|------|

532 | Major | RT | //Mode | FRA | XO | Rc |X-Form|

534 **Rc=1 and OE=1**

536 All of these insructions have an Rc=1 mode which sets CR0

537 in the normal way for any instructions producing a GPR result.

538 Additionally, when OE=1, if the numerical value of the FP number

539 is not 100% accurately preserved (due to truncation or saturation

540 and including when the FP number was NaN) then this is considered

541 to be an integer Overflow condition, and CR0.SO, XER.SO and XER.OV

542 are all set as normal for any GPR instructions that overflow.

544 **Instructions**

546 * `fcvttgw RT, FRA, Mode`

547 Convert from 64-bit float to 32-bit signed integer, writing the result

548 to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiw` or `fctiwz`

549 * `fcvttguw RT, FRA, Mode`

550 Convert from 64-bit float to 32-bit unsigned integer, writing the result

551 to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiwu` or `fctiwuz`

552 * `fcvttgd RT, FRA, Mode`

553 Convert from 64-bit float to 64-bit signed integer, writing the result

554 to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctid` or `fctidz`

555 * `fcvttgud RT, FRA, Mode`

556 Convert from 64-bit float to 64-bit unsigned integer, writing the result

557 to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctidu` or `fctiduz`

558 * `fcvtstgw RT, FRA, Mode`

559 Convert from 32-bit float to 32-bit signed integer, writing the result

560 to the GPR `RT`. Converts using [mode `Mode`]

561 * `fcvtstguw RT, FRA, Mode`

562 Convert from 32-bit float to 32-bit unsigned integer, writing the result

563 to the GPR `RT`. Converts using [mode `Mode`]

564 * `fcvtstgd RT, FRA, Mode`

565 Convert from 32-bit float to 64-bit signed integer, writing the result

566 to the GPR `RT`. Converts using [mode `Mode`]

567 * `fcvtstgud RT, FRA, Mode`

568 Convert from 32-bit float to 64-bit unsigned integer, writing the result

569 to the GPR `RT`. Converts using [mode `Mode`]

571 [mode `Mode`]: #fpr-to-gpr-conversion-mode

573 ## FP to Integer Conversion Pseudo-code

575 Key for pseudo-code:

577 | term | result type | definition |

578 |---------------------------|-------------|----------------------------------------------------------------------------------------------------|

579 | `fp` | -- | `f32` or `f64` (or other types from SimpleV) |

580 | `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) |

581 | `uint` | -- | the unsigned integer of the same bit-width as `int` |

582 | `int::BITS` | `int` | the bit-width of `int` |

583 | `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` |

584 | `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` |

585 | `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` |

586 | `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` |

587 | `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. |

588 | `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |

590 <div id="fp-to-int-openpower-conversion-semantics"></div>

591 OpenPower conversion semantics (section A.2 page 999 (page 1023) of OpenPower ISA v3.1):

593 ```

594 def fp_to_int_open_power<fp, int>(v: fp) -> int:

595 if v is NaN:

596 return int::MIN_VALUE

597 if v >= int::MAX_VALUE:

598 return int::MAX_VALUE

599 if v <= int::MIN_VALUE:

600 return int::MIN_VALUE

601 return (int)rint(v, rounding_mode)

602 ```

604 <div id="fp-to-int-java-conversion-semantics"></div>

605 [Java conversion semantics](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)

606 /

607 [Rust semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)

608 (with adjustment to add non-truncate rounding modes):

610 ```

611 def fp_to_int_java<fp, int>(v: fp) -> int:

612 if v is NaN:

613 return 0

614 if v >= int::MAX_VALUE:

615 return int::MAX_VALUE

616 if v <= int::MIN_VALUE:

617 return int::MIN_VALUE

618 return (int)rint(v, rounding_mode)

619 ```

621 <div id="fp-to-int-javascript-conversion-semantics"></div>

622 Section 7.1 of the ECMAScript / JavaScript

623 [conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32) (with adjustment to add non-truncate rounding modes):

625 ```

626 def fp_to_int_java_script<fp, int>(v: fp) -> int:

627 if v is NaN or infinite:

628 return 0

629 v = rint(v, rounding_mode) # assume no loss of precision in result

630 v = v mod int::VALUE_COUNT # 2^32 for i32, 2^64 for i64, result is non-negative

631 bits = (uint)v

632 return (int)bits

633 ```