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[libreriscv.git] / openpower / sv / sbf.py
1 def sbf(RA, mask=None, zero=False):
2 RT = RA if mask is not None and not zero else 0
3 i = 0
4 # start setting if no predicate or if 1st predicate bit set
5 setting_mode = mask is None
6 while i < 16:
7 bit = 1<<i
8 if not setting_mode and mask is not None and (mask & bit):
9 setting_mode = True # back into "setting" mode
10 if setting_mode and mask is not None and not (mask & bit):
11 setting_mode = False # disable when no mask bit
12 if setting_mode:
13 if RA & bit: # found a bit in rs1: stop setting RT
14 setting_mode = False
15 else:
16 RT |= bit
17 i += 1
18 return RT
19
20 if __name__ == '__main__':
21 m = 0b11000011
22 v3 = 0b10010100 # vmsbf.m v2, v3
23 v2 = 0b01000011 # v2
24 RT = sbf(v3, m, zero=True)
25 print(bin(v3), bin(v2), bin(RT))
26 v3 = 0b10010100 # vmsbf.m v2, v3
27 v2 = 0b00000011 # v2 contents
28 RT = sbf(v3)
29 print(bin(v3), bin(v2), bin(RT))
30 v3 = 0b10010101 # vmsbf.m v2, v3
31 v2 = 0b00000000 # v2
32 RT = sbf(v3)
33 print(bin(v3), bin(v2), bin(RT))
34 v3 = 0b00000000 # vmsbf.m v2, v3
35 v2 = 0b11111111 # v2
36 RT = sbf(v3)
37 print(bin(v3), bin(v2), bin(RT))