svp64-primer/summary.tex

   1 \section{Summary}
   2 Specification for hardware for-loop that ONLY uses scalar instructions
   3
   4 \subsection{What is SIMD?}
   5 \textit{(for clarity only 64-bit registers will be discussed here, however 128-, 256-, and 512-bit implementations also exist)}
   6
   7 \ac{SIMD} is a way of partitioning existing \ac{CPU} registers of 64-bit length into smaller 8-, 16-, 32-bit pieces \cite{SIMD_HARM}\cite{SIMD_HPC}. These partitions can then be operated on simultaneously, and the initial values and results being stored as entire 64-bit registers. The SIMD instruction opcode includes the data width and the operation to perform.\par
   8
   9 \begin{figure}[h]
  10         \includegraphics[width=\linewidth]{simd_axb}
  11         \caption{SIMD multiplication}
  12         \label{fig:simd_axb}
  13 \end{figure}
  14
  15 This method can have a huge advantage for rapid processing of vector-type data (image/video, physics simulations, cryptography, etc.)\cite{SIMD_WASM}, and thus on paper is very attractive compared to scalar-only instructions.\par
  16
  17 SIMD registers are of a fixed length and thus to achieve greater performance, CPU architects typically increase the width of registers (to 128-, 256-, 512-bit etc) for more partitions.\par
  18 Additionally, binary compatibility is an important feature, and thus each doubling of SIMD registers also expands the instruction set. The number of instructions quickly balloons and this can be seen in popular \ac{ISA}, for example IA-32 expanding from 80 to about 1400 instructions since 1978\cite{SIMD_HARM}.\par
  19
  20 \subsection{Vector Architectures}
  21 An older alternative exists to utilise data parallelism - vector architectures. Vector CPUs collect operands from the main memory, and store them in large, sequential vector registers.\par
  22
  23 Pipelined execution units then perform parallel computations on these vector registers. The result vector is then broken up into individual results which are sent back into the main memory.\par
  24
  25 A simple vector processor might operate on one element at a time, however as the operations are independent by definition \textbf{(where is this from?)}, a processor could be made to compute all of the vector's elements simultaneously.\par
  26
  27 Typically, today's vector processors can execute two, four, or eight 64-bit elements per clock cycle\cite{SIMD_HARM}. Such processors can also deal with (in hardware) fringe cases where the vector length is not a multiple of the number of elements. The element data width is variable (just like in SIMD). Fig \ref{fig:vl_reg_n} shows the relationship between number of elements, data width and register vector length.
  28
  29 \begin{figure}[h]
  30         \includegraphics[width=\linewidth]{vl_reg_n}
  31         \caption{Vector length, data width, number of elements}
  32         \label{fig:vl_reg_n}
  33 \end{figure}
  34
  35 RISCV Vector extension supports a VL of up to $2^{16}$ or $65536$ bits, which can fit 1024 64-bit words \cite{riscv-v-spec}.
  36
  37 \subsection{Comparison Between SIMD and Vector}
  38 \textit{(Need to add more here, use example from \cite{SIMD_HARM}?)}
  39
  40 \subsubsection{Code Example}
  41 \begin{verbatim}
  42 test test
  43 \end{verbatim}
  44
  45 \subsection{Shortfalls of SIMD}
  46 The following are just some of the reasons why SIMD is unsustainable as the number of instructions increase:
  47 \begin{itemize}
  48         \item Hardware design, ASIC routing etc.
  49         \item Compiler design
  50         \item Documentation of the ISA
  51         \item Manual coding and optimisation
  52         \item Time to support the platform
  53 \end{itemize}
  54
  55 \subsection{Simple Vectorisation}
  56 \ac{SV} is a Scalable Vector ISA designed for hybrid workloads (CPU, GPU, VPU, 3D?).
  57 Includes features normally found only on Cray Supercomputers (Cray-1, NEC SX-Aurora) and GPUs.
  58 Keeps a strictly simple RISC leveraging a scalar ISA by using "Prefixing"
  59 No dedicated vector opcodes exist in SV!
  60
  61 Main design principles
  62 \begin{itemize}
  63         \item Introduce by implementing on top of existing Power ISA
  64         \item Effectively a \textbf{hardware for-loop}, pauses main PC, issues multiple scalar op's
  65         \item Preserves underlying scalar execution dependencies as the for-loop had been expanded as actual scalar instructions ("preserving Program Order")
  66         \item Augments existing instructions by adding "tags" - provides Vectorisation "context" rather than adding new opcodes.
  67         \item Does not modify or deviate from the underlying scalar Power ISA unless there's a significant performance boost or other advantage in the vector space (see \ref{subsubsec:add_to_pow_isa})
  68         \item Aimed at Supercomputing: avoids creating significant \textit{sequential dependency hazards}, allowing \textbf{high performance superscalar microarchitectures} to be deployed.
  69 \end{itemize}
  70
  71 Advantages include:
  72 \begin{itemize}
  73         \item Easy to create first (and sometimes only) implementation as a literal for-loop in hardware, simulators, and compilers.
  74         \item Hardware Architects may understand and implement SV as being an extra pipeline stage, inserted between decode and issue. Essentially a simple for-loop issuing element-level sub-instructions.
  75         \item More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks, leveraging existing Multi-Issue Infrastructure.
  76         \item Mostly high-level "context" which does not significantly deviate from scalar Power ISA and, in its purest form being a "for-loop around scalar instructions". Thus SV is minimally-disruptive and consequently has a reasonable chance of broad community adoption and acceptance.
  77         \item Obliterates SIMD opcode proliferation ($O(N^6)$\textbf{[source?]}) as well as dedicated Vectorisation ISAs. No more separate vector instructions.
  78 \end{itemize}
  79
  80 \subsubsection{Deviations from Power ISA}
  81 \label{subsubsec:add_to_pow_isa}
  82 \textit{(TODO: EXPAND)}
  83 dropping XER.SO for example
  84
  85 \subsubsection{Prefix 64 - SVP64}
  86
  87 SVP64, is a specification designed to rival existing SIMD implementations by:
  88 \begin{itemize}
  89         \item Simplifying the hardware design
  90         \item Reducing maintenance overhead
  91         \item Easier for compilers, coders, documentation
  92         \item Time to support platform is a fraction of conventional SIMD (Less money on R\&D, faster to deliver)
  93 \end{itemize}
  94
  95 - Intel SIMD is designed to be more capable and has more features, and thus has a greater complexity (?)
  96
  97
  98 - What are we going to gain?
  99
 100 -for loop, increment registers RT, RA, RB
 101 -few instructions, easier to implement and maintain
 102 -example assembly code
 103 -ARM has already started to add to libC SVE2 support
 104
 105 1970 x86 comparison