----------
-# Moves
+# Move To/From Floating-Point Register Instructions
-These instructions perform a straight unaltered bit-level copy from one Register
-File to another.
+These instructions perform a copy from one register file to another, as if by
+using a GPR/FPR store, followed by a FPR/GPR load.
-## Move From FPR
+## Move From Floating-Point Register
```
mffpr RT, FRB
RT <- (FRB)
```
-Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754
-representation directly. This is equivalent to `stfd` followed by `ld`.
-As `mffpr` is just copying bits, `FPSCR` is not affected in any way. `mffpr` is
-similar to `mfvsrd`, except doesn't require VSX, which is useful for SFFS
-implementations.
-
-Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
-operations.
+The contents of `FPR[FRB]` are placed into `GPR[RT]`.
Special Registers altered:
CR0 (if Rc=1)
```
+Architecture Note:
+
+`mffpr` is equivalent to the combination of `stfd` followed by `ld`.
+
+Architecture Note:
+
+`mffpr` is a separate instruction from `mfvsrd` because `mfvsrd` requires
+VSX which may not be available on simpler implementations.
+Additionally, SVP64 may treat VSX instructions differently than SFFS
+instructions in a future version of the architecture.
+
----------
-## Move From FPR Single
+## Move From Floating-Point Register Single
```
mffprs RT, FRB
| PO | RT | // | FRB | XO | Rc | X-Form |
```
- RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses
+ RT <- [0] * 32 || SINGLE((FRB))
```
-Move a BFP32 from a FPR to a GPR, by using `SINGLE` to extract the standard
-`BFP32` form from FRB and zero-extending the result to 64-bits and storing to
-RT. This is equivalent to `stfs` followed by `lwz`.
-As `mffprs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
-
-Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
-operations.
+The contents of `FPR[FRB]` are converted to BFP32 by using `SINGLE`, then
+zero-extended to 64-bits, and the result stored in `GPR[RT]`.
Special Registers altered:
CR0 (if Rc=1)
```
+Architecture Note:
+
+`mffprs` is equivalent to the combination of `stfs` followed by `lwz`.
+
----------
\newpage{}
-## Move To FPR
+## Move To Floating-Point Register
```
mtfpr FRT, RB
FRT <- (RB)
```
-move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754
-representation directly. This is equivalent to `std` followed by `lfd`.
-As `mtfpr` is just copying bits, `FPSCR` is not affected in any way. `mtfpr` is
-similar to `mtvsrd`, except doesn't require VSX, which is useful for SFFS
-implementations.
+The contents of `GPR[RB]` are placed into `FPR[FRT]`.
Special Registers altered:
None
```
+Architecture Note:
+
+`mtfpr` is equivalent to the combination of `std` followed by `lfd`.
+
+Architecture Note:
+
+`mtfpr` is a separate instruction from `mtvsrd` because `mtvsrd` requires
+VSX which may not be available on simpler implementations.
+Additionally, SVP64 may treat VSX instructions differently than SFFS
+instructions in a future version of the architecture.
+
----------
-## Move To FPR Single
+## Move To Floating-Point Register Single
```
mtfprs FRT, RB
| PO | FRT | // | RB | XO | // | X-Form |
```
- FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses
+ FRT <- DOUBLE((RB)[32:63])
```
-Move a BFP32 from a GPR to a FPR, by using `DOUBLE` on the least significant
-32-bits of RB to do the standard BFP32 in BFP64 trick and store the result in
-FRT. This is equivalent to `stw` followed by `lfs`.
-As `mtfprs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
+The contents of bits 32:63 of `GPR[RB]` are converted to BFP64 by using
+`DOUBLE`, then the result is stored in `GPR[RT]`.
Special Registers altered:
None
```
+Architecture Note:
+
+`mtfprs` is equivalent to the combination of `stw` followed by `lfs`.
+
----------
\newpage{}
-# Conversions
-
-Unlike the move instructions
-these instructions perform conversions between Integer and
-Floating Point. Truncation can therefore occur, as well
-as exceptions.
+# Conversion To/From Floating-Point Register Instructions
-## Convert To FPR
+## Convert To Floating-Point Register
```
ctfpr FRT, RB, IT
### Assembly Aliases
-| Assembly Alias | Full Instruction |
-|----------------------|----------------------|
-| `ctfprw FRT, RB` | `ctfpr FRT, RB, 0` |
-| `ctfprw. FRT, RB` | `ctfpr. FRT, RB, 0` |
-| `ctfpruw FRT, RB` | `ctfpr FRT, RB, 1` |
-| `ctfpruw. FRT, RB` | `ctfpr. FRT, RB, 1` |
-| `ctfprd FRT, RB` | `ctfpr FRT, RB, 2` |
-| `ctfprd. FRT, RB` | `ctfpr. FRT, RB, 2` |
-| `ctfprud FRT, RB` | `ctfpr FRT, RB, 3` |
-| `ctfprud. FRT, RB` | `ctfpr. FRT, RB, 3` |
+| Assembly Alias | Full Instruction |
+|--------------------|---------------------|
+| `ctfprw FRT, RB` | `ctfpr FRT, RB, 0` |
+| `ctfprw. FRT, RB` | `ctfpr. FRT, RB, 0` |
+| `ctfpruw FRT, RB` | `ctfpr FRT, RB, 1` |
+| `ctfpruw. FRT, RB` | `ctfpr. FRT, RB, 1` |
+| `ctfprd FRT, RB` | `ctfpr FRT, RB, 2` |
+| `ctfprd. FRT, RB` | `ctfpr. FRT, RB, 2` |
+| `ctfprud FRT, RB` | `ctfpr FRT, RB, 3` |
+| `ctfprud. FRT, RB` | `ctfpr. FRT, RB, 3` |
----------
\newpage{}
-## Convert To FPR Single
+## Convert To Floating-Point Register Single
```
ctfprs FRT, RB, IT
### Assembly Aliases
-| Assembly Alias | Full Instruction |
-|----------------------|----------------------|
+| Assembly Alias | Full Instruction |
+|---------------------|---------------------|
| `ctfprws FRT, RB` | `ctfpr FRT, RB, 0` |
| `ctfprws. FRT, RB` | `ctfpr. FRT, RB, 0` |
| `ctfpruws FRT, RB` | `ctfpr FRT, RB, 1` |
Key for pseudo-code:
-| term | result type | definition |
-|---------------------------|-------------|----------------------------------------------------------------------------------------------------|
-| `fp` | -- | `f32` or `f64` (or other types from SimpleV) |
-| `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) |
-| `uint` | -- | the unsigned integer of the same bit-width as `int` |
-| `int::BITS` | `int` | the bit-width of `int` |
-| `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` |
-| `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` |
-| `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` |
-| `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` |
-| `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. |
-| `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
+| term | result type | definition |
+|---------------------------|-------------|-----------------------------------------------------------------------------------------------|
+| `fp` | -- | `f32` or `f64` (or other types from SimpleV) |
+| `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) |
+| `uint` | -- | the unsigned integer of the same bit-width as `int` |
+| `int::BITS` | `int` | the bit-width of `int` |
+| `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` |
+| `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` |
+| `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` |
+| `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` |
+| `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. |
+| `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
<div id="fp-to-int-openpower-conversion-semantics"></div>
OpenPower conversion semantics (section A.2 page 1009 (page 1035) of
\newpage{}
-## Convert From FPR
+## Convert From Floating-Point Register
```
cffpr RT, FRB, CVM, IT
### Assembly Aliases
-| Assembly Alias | Full Instruction |
-|---------------------------|----------------------------|
+| Assembly Alias | Full Instruction |
+|--------------------------|---------------------------|
| `cffprw RT, FRB, CVM` | `cffpr RT, FRB, CVM, 0` |
| `cffprw. RT, FRB, CVM` | `cffpr. RT, FRB, CVM, 0` |
| `cffprwo RT, FRB, CVM` | `cffpro RT, FRB, CVM, 0` |
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