- heavily depending on python OO (not possible with VHDL or Verilog)
- leap-frogging ahead by not reinventing the wheel
-## What is being developed? Roadmap
+## Why is it different from other SoCs?
+
+* LibreSOC is a hybrid CPU-VPU-GPU architecture.
+ - OpenPOWER ISA *itself* is extended to include 3D and Video instructions
+ - (SIN, ATAN2, YUV2RGB, Texture Interpolation)
+ - Only after approval of OpenPOWER Foundation!
+ - Massively simplifies driver development and application debugging
+* Vectorisation is "Simple-V" (VSX not being implemented)
+ - VSX is SIMD and is considered harmful
+ - https://www.sigarch.org/simd-instructions-considered-harmful/
+* Developed in python HDL called "nmigen"
+ - OO programming techniques can be deployed
+ - Impossible to do in VHDL or Verilog
+ - yosys converts nmigen to verilog for standard tools.
+
+## What is being developed? (Roadmap)
* First simple core achieved in simulation Sep 2020
- FPGA (ECP5) target followed shortly