(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 6ef96a6cffe5e67ee68e974bebdaeee5a87fa58f..3cced7dd8002414c4b626606ff6b07efa70b99a9 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -72,7 +72,7 @@ An autogenerator containing CSV files is available so that the task of creating
 
 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
 * power-gem5: TODO
-* TestIssuer: TODO
+* TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
 * Microwatt: TODO
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
@@ -132,7 +132,7 @@ Due to the need for exceptions to occur in the middle, the loop should *not* be
 
 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 * power-gem5: TODO
-* TestIssuer: TODO
+* TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 * Microwatt: TODO
 
 ## Increasing register file sizes