Recent work

[libresoc-isa-manual.git] / powerpc-add / src / glossary.tex

diff --git a/powerpc-add/src/glossary.tex b/powerpc-add/src/glossary.tex
index 5aed0b3838911e011b3e225499f217f7dbbf5416..941adf20182f233f699ff28b7d9f63dc7420011d 100644 (file)
--- a/powerpc-add/src/glossary.tex
+++ b/powerpc-add/src/glossary.tex
@@ -125,6 +125,15 @@
     }
 }
 
+\newglossaryentry{ICubeCorpIC3128}
+{
+  name=ICubeCorp IC3128,
+  description={
+    A \gls{SoC} from ICube that has both \gls{CPU} and \gls{GPU} on a single chip.
+    See: \href{https://www.cnx-software.com/2014/10/15/icube-mvp-socs-combine-cpu-and-gpu-into-a-single-unified-processing-unit-upu/}{CNX Software}
+    }
+}
+
 \newglossaryentry{IEEE754}
 {
   name=IEEE754,
@@ -136,6 +145,17 @@
     }
 }
 
+\newglossaryentry{IOMMU}
+{
+  name=IOMMU,
+  description={
+    Input Output Memory Management Unit.
+    Mediates between Input/Output devices and main memory mapping virtual
+    addresses to physical ones and, maybe, enforcing protection restrictions.
+    See: \href{https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit}{Wikipedia}
+    }
+}
+
 \newglossaryentry{ISA}
 {
   name=ISA,
@@ -148,6 +168,28 @@
     }
 }
 
+\newglossaryentry{ISAMUX}
+{
+  name=ISAMUX,
+  description={
+    \gls{ISA} \gls{MUX} -- having the same bits in the ISA mean different things.
+    }
+}
+
+\newglossaryentry{H.265}
+{
+  name=H.265,
+  description={
+    High Efficiency Video Coding, also known as HEVC \& MPEG-H Part 2.
+    Released in 2013.
+    Its data compression is better, for the same video quality, than previous standards:
+    AVC, H.264, or MPEG-4 Part 10.
+    Patent license may be required for H.265 use.
+    See: \gls{VP9}
+    \href{https://en.wikipedia.org/wiki/High_Efficiency_Video_Coding}{Wikipedia}
+    }
+}
+
 \newglossaryentry{JIT}
 {
   name=JIT,
@@ -183,6 +225,29 @@
     }
 }
 
+\newglossaryentry{MISA}
+{
+  name=MISA,
+  description={
+    Multiple Instruction Sets Architecture.
+    The ability to run more than one \gls{ISA} on the same hardware.
+    A setting in a \gls{CSR} controls which instructions will be
+    recognised at any time.
+    See: \href{}{}
+    }
+}
+% https://ieeexplore.ieee.org/document/6136696 - paywalled
+% https://www.researchgate.net/figure/Overview-of-the-MISA-instructional-system-design-method_fig2_245165034
+% https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.pdf page 15
+
+\newglossaryentry{MUX}
+{
+  name=MUX,
+  description={
+    Multiplex, a way of compressing several things into the same data.
+%    See: \href{}{}
+    }
+}
 
 \newglossaryentry{PowerPC}
 {
@@ -245,12 +310,33 @@
     }
 }
 
+\newglossaryentry{VideoCoreIV}
+{
+  name=VideoCore IV,
+  description={
+    Low power \gls{SoC} from Broadcom. ARM CPU that is used in the Raspberry Pi.
+    See: \href{https://en.wikipedia.org/wiki/VideoCore}{Wikipedia}
+    }
+}
+
+\newglossaryentry{VP9}
+{
+  name=VP9,
+  description={
+    Video encoding format released by Google in 2013.
+    Released open \& royalty free although Sisvel has made some claims.
+    See: \href{https://en.wikipedia.org/wiki/VP9}{Wikipedia}
+    }
+}
+
+% https://libre-soc.org/vpu/
 \newglossaryentry{VPU}
 {
   name=VPU,
   description={
-    Video Processing Unit and Visual Processing Unit and Vector Processing Unit
-    Contrast with \gls{CPU} and \gls{GPU}.
+     Video Processing Unit.
+     Similar to a \gls{CPU} but has extra hardware instructions to speed up things
+     like the decoding and encoding of \gls{H.265}, or \gls{VP9}.
 %    See: \href{}{}
     }
 }
@@ -270,8 +356,23 @@
 % namespace
 % MSB
 % PCR
+% SIMD
+% ALU
+% RA
+% RB
+% microwatt    https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl
+% 6600         https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
+% DAG          Directed Acyclic Graph
+% SR latch
+% FU           Functional Unit
+% FPU          float point unit
+% WAR          https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ #10
+% ALU
+% FU-FU function to function   https://libre-soc.org/3d_gpu/architecture/6600scoreboard/       #14
+% GORD GOWR    GO read/write
 % ISANS
+%  Unified Processing Unit (UPU)
+%  MVP (Multi-thread Virtual Pipeline
 % SIE
-% MISA
 % WARL
 % WLRL